Summary:
- I noticed that the getcoreid macro in the latest esp-idf
is much simpler than the current NuttX's.
- This commit replaces the macro with the latest esp-idf's
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
Summary:
- According to the Xtensa ISA document, this ISYNC instruction
between WSR SCOMPARE1 and S32C1I is unnecessary
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that DEBUGASSERT sometimes happens in nxsem_wait()
when testing Wi-Fi with esp32-devkitc:wsifi_smp
- The call stack was not from an interrupt handler and actually
g_current_regs[] were correct, even though asserted with
(up_interrupt_handler() == false)
- Finally, I found that we need to call rsync after we set
a new value to the PS register which is described in the
Xtensa document.
- This commit fixes this issue
Impact:
- All xtensa architectures
Testing:
- Tested with esp32-devkitc:wifi_smp and esp32-devkitc:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- SP_SECTION was introduced to allocate spinlock in non-cachable
region mainly for Cortex-A to stabilize the NuttX SMP kernel
- However, all spinlocks are now allocated in cachable area and
works without any problems
- So SP_SECTION should be removed to simplify the kernel code
Impact:
- None
Testing:
- Build test only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code
Impact:
- All SMP configurations
Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)
Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
This config is only useful when there is a > 4MB PSRAM and thus needs to
be selected by the user explicitly.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
arch: Allocate the space from the beginning in up_stack_frame
and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
I've seen a module with 16 bytes .rodata alignment for xmm operations.
It was getting SEGV on sim/Linux because of the alignment issue.
The same module binary seems working fine after applying this patch.
Also, tested on sim/macOS and esp32 on qemu,
using a module with an artificially large alignment. (64 bytes)
Some ESP32 GPIO pins (2, 4, 12, 13, 25, 27, 32) weren't accepting
pull-up/pull-down resistors. These pins are RTC GPIO pins and need
to have pull-up/pull-down configured in the RTC registers.
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Espressif Systems has submitted the SGA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Previously SPI interrupts were enabled on DMA initialization. But since
the addition of SPI Mixed mode it created a side-effect, breaking
polling transfers. So now interrupts are enabled before the DMA
transactions and disabled once they are finished.
Furthermore, the transaction done flag is also cleared before a new
transaction starts.
Commit 6382b2ba introduced the possibility of using SPI in Mixed mode,
i.e. performing SPI transfers via both polling and interrupts. However,
setbits was only applying the configuration if DMA was not enabled.
is enabled.
That region is technically part of the PRO CPU and we should be able to
allocate it early. However, QEMU uses a slightly different bootloader
image that uses the same part for both CPU. So, when APP CPU starts
during the SMP bring up it will corrupt some data.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
In case CONFIG_MM_REGIONS doesn't include all the available memory
regions the user will have a warning to increase it.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Internal heap was occupying the region straight after .data up to
HEAP_REGION1. The issue with this is if static allocation is large,
we'll end up with too little memory left for the internal heap.
Moving it to the beginning of region 2 gives us more room to play with.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Bug description:
CONFIG_SMP=y
Suppose we have 2 cores in SMP, here is the ps return:
PID GROUP CPU PRI POLICY TYPE NPX STATE STACK USED FILLED COMMAND
0 0 0 0 FIFO Kthread N-- Assigned 004076 000748 18.3% CPU0 IDLE
1 0 1 0 FIFO Kthread N-- Running 004096 000540 13.1% CPU1 IDLE
nsh> kill -4 0
or:
nsh> kill -4 1
system blocked.
Reason:
In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.
Fix:
Add condition to cover saved_irqcount == 0.
Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
This seems to fix esp32_readdata_encrypted() with spiram "buffer".
Note: I'm not sure if this is the right fix or not.
I couldn't find any documentation about Cache_Flush.
You can find them used in the ROM version of memcpy.
While it might be controversial if it's a good idea to use the ROM version
of these functions, it's nicer to support more instructions here anyway.
Summary:
- This commit fixes a compile warning if CONFIG_ARCH_INTERRUPTSTACK is set
Impact:
- None
Testing:
- Built with esp32-devkitc:smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Recently I noticed that ESP32-DevKitC-32D suddenly stops
during receiving ping packets from PC after 10-20mins
- Actually, sometimes memory leak happened when some device
sent a big broadcast packet periodically on the network
- This commit fixes this issue by calling esp_wifi_free_eb()
in the case that the packet exceeds WLAN_BUF_SIZE.
- Also, this commit applies the same logic in the case that
the Wi-Fi interface is down
Impact:
- None
Testing:
- Tested with esp32-devkitc:wapi
Suggested-by: YAMAMOTO Takashi <yamamoto@midokura.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
g_irq_spin for backword compatibility (In this case, NULL must be specified)
Impact:
- None
Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
The static memory is now divided at almost the middle to not override
the ROM data. The old 0x28000 will take all of what's left for heap
region1.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Summary:
- This commit fixes compile errors in esp32_spiflash.c and
esp32_wifi_adapter.c with CONFIG_SMP=y
Impact:
- SMP only
Testing:
- Tested with esp32-devkitc:wapi
- NOTE: the following configs need to be added.
+CONFIG_SMP=y
+CONFIG_SMP_IDLETHREAD_STACKSIZE=3072
+CONFIG_SMP_NCPUS=2
+CONFIG_SPINLOCK_IRQ=y
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
SMP was broken because the ROM memory wasn't set correctly. Some
regions were shared with the ROM code.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Requiring the size to be a multiple of 3 is a very strange restriction.
It doesn't even work with the default value of SPI_SLAVE_BUFSIZE.
I guess it was a typo.
The original assertion was wrong because:
* cpuint numbers for edge interrupts are not dense
(while ESP32_CPUINT_NEDGEPERIPHS is 4, EPS32_CPUINT_EDGESET is not 0xf.)
* This function is used for level interrupts too
1. when sending a message in a group fails, exit immediately
2. when catch I2C error interrupt, close interrupt
3. clear clock configuration when deinit I2C
4. free I2C interrupt when deinit I2C
wget is missing from some system (like macOS and Windows native),
it's better to use curl to simplify build environment.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
section too early before context switching which resulted in
selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
from nxtask_exit() to up_exit() and also removing
spin_setbit() and spin_clrbit() from nxtask_exit()
because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
were done for all CPU architectures
Impact:
- This commit affects all CPU architectures regardless of SMP
Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Fix the following error:
CC: chip/esp32_wifi_adapter.c
In file included from /Users/yamamoto/git/nuttx/nuttx/include/nuttx/mm/shm.h:45,
from /Users/yamamoto/git/nuttx/nuttx/include/nuttx/sched.h:42,
from /Users/yamamoto/git/nuttx/nuttx/include/sched.h:35,
from /Users/yamamoto/git/nuttx/nuttx/include/stdio.h:48,
from chip/esp32_wifi_adapter.c:28:
chip/esp32_wifi_adapter.c: In function 'phy_printf':
chip/esp32_wifi_adapter.c:3952:10: error: expected ')' before 'format'
wlinfo(format, arg);
^~~~~~
Summary:
- This commit fixes global IRQ control logic
- In previous implementation, g_cpu_irqset for a remote CPU was
set in sched_add_readytorun(), sched_remove_readytorun() and
up_schedule_sigaction()
- In this implementation, they are removed.
- Instead, in the pause handler, call enter_critical_setion()
which will call up_cpu_paused() then acquire g_cpu_irqlock
- So if a new task with irqcount > 1 restarts on the remote CPU,
the CPU will only hold a critical section. Thus, the issue such as
'POSSIBLE FOR TWO CPUs TO HOLD A CRITICAL SECTION' could be resolved.
- Fix nxsched_resume_scheduler() so that it does not call spin_clrbit()
if a CPU does not hold a g_cpu_irqset
- Fix nxtask_exit() so that it acquires g_cpu_irqlock
- Update TODO
Impact:
- All SMP implementations
Testing:
- Tested with smp, ostest with the following configurations
- Tested with spresense:wifi_smp (NCPUS=2,4)
- Tested with sabre-6quad:smp (QEMU, dev board)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with esp32-core:smp (QEMU)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
1. function "stop" should really stop repeat timer
2. delete timer really in rt-timer task to avoid resource being broken
3. timer triggers when stopping/deleting it and skip it in ISR
cfsetispeed() now stores baud rate to c_cflag member of
struct termios, so it must not be overridden later on.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Summary:
- This commit fixes crash on startup introduced by commit 232aa62f03
Impact:
- Affects all use cases for esp32
Testing:
- Tested with esp32-core:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
pads go through the same GPIO matrix to select one of the 6 possible functions.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Both CPUs are soft-reset with a call to board_reset. This is actually a
Core Reset, so both cores and all registers are reset. The only
exception is RTC.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Summary:
- Apply the same fix for Arm SMP
Impact:
- Affects SMP only
Testing:
- Tested with esp32-core:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
and remove the special handling in the stack dump
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
EXTRAFLAGS is already applied to *FLAGS in board's Make.defs (and
it applies to whole build, not just arch-code). EXTRAFLAGS is passed
around each make call to the complete build.
KDEFINE is already added to EXTRAFLAGS in main Makefile so no need
to add it again in arch-level Makefile
1.Reduce the default size of task_group_s(~512B each task)
2.Scale better between simple and complex application
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia872137504fddcf64d89c48d6f0593d76d582710
Summary:
- ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP
- At that time, i.MX6 (quad Cortex-A9) did not use this config
- However, this option is now used for all CPUs which support SMP
- So it's good timing for refactoring the code
Impact:
- Should have no impact because the logic is the same for SMP
Testing:
- Tested with board: spresense:smp, spresense:wifi_smp
- Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp
- Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
PR #1450 broke the Cygwin build. Refer to Issue #1672.
The use of of logic like:
EXTRA_LIBPATHS += -L "${dir ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcc.a}}"
fails when the Toolchain $(CC) is a native Windows toolchain. That is because the returned path is a Windows-style patch which cannot be handled by the make 'dir' command. Commit 4910d43ab0 reorganized a lot of definitions and replaced the correct code with the use of the limit make 'dir' command. The original code used the Bash dirname command which does not suffer from this limitation; it can handle both POSIX and Windows paths.
This was verified using the stm32f4discover:nsh toolchain with the Windows native ARM Embedded toolchain. That toolchain returns:
arm-none-eabi-gcc --print-file-name=libgcc.a
c:/program files (x86)/gnu tools arm embedded/9 2019-q4-major/bin/../lib/gcc/arm-none-eabi/9.2.1/libgcc.a
Master:
1. add DMA RX/TX support
2. add software chip selection
3. add user defined chip selection
4. add IOMUX check and IO map
Slave:
1. add DMA RX/TX support
2. add IOMUX check and IO map
3. use full 256 bit SPI TX/RX cache in non-DMA mode
to save the preserved space(1KB) and also avoid the heap overhead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I694073f68e1bd63960cedeea1ddec441437be025
ESP32 runs code in a SPI Flash, so users can also use it to store
data directly or mount some parts into a filesystem.
The SPI Flash usually use SPI0.
This driver was implemented by Dong Heng dongheng@espressif.com
and modified to fix coding style by Alan Carvalho de Assis.
This driver was implemented by Dong Heng <dongheng@espressif.com>
and modified to fix coding style by Alan Carvalho de Assis.
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@gmail.com>
Make.dep file should be updated by .config changed after first make.
There are 2 cases affected for this problem:
1) Add source files by config symbol
2) Include header files in #ifdef directive
These 2 cases may not be included in Make.dep and this may prevent the
differential build from working correctly.
1.It make sense to let Toolchain.defs give the default value
2.The board can still change if the default isn't suitable
3.Avoid the same definition spread more than 200 Make.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic2649f1c7689bcf59c105ca8db61cad45b6e0e64
since exit will be only callable from userspace and change
the 1st argument from "const uint8_t *" to "const char *"
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I86487d57210ab63109148232da71dbc4d60a563b
ASAN trace:
...
==32087==ERROR: AddressSanitizer: heap-buffer-overflow on address 0xf4502120 at pc 0x56673ca3 bp 0xff9b6a08 sp 0xff9b69f8
WRITE of size 1 at 0xf4502120 thread T0
#0 0x56673ca2 in strcpy string/lib_strcpy.c:64
0xf4502120 is located 0 bytes to the right of 8224-byte region [0xf4500100,0xf4502120)
allocated by thread T0 here:
#0 0xf7a60f54 in malloc (/usr/lib32/libasan.so.4+0xe5f54)
#1 0x5667725d in up_create_stack sim/up_createstack.c:135
#2 0x56657ed8 in nxthread_create task/task_create.c:125
#3 0x566580bb in kthread_create task/task_create.c:297
#4 0x5665935f in work_start_highpri wqueue/kwork_hpthread.c:149
#5 0x56656f31 in nx_workqueues init/nx_bringup.c:181
#6 0x56656fc6 in nx_bringup init/nx_bringup.c:436
#7 0x56656e95 in nx_start init/nx_start.c:809
#8 0x566548d4 in main sim/up_head.c:95
#9 0xf763ae80 in __libc_start_main (/lib/i386-linux-gnu/libc.so.6+0x18e80)
CALLSTACK:
#8 0xf79de7a5 in __asan_report_store1 () from /usr/lib32/libasan.so.4
#9 0x565fd4d7 in strcpy (dest=0xf4a02121 "", src=0xf5c00895 "k") at string/lib_strcpy.c:64
#10 0x565e4eb2 in nxtask_setup_stackargs (tcb=0xf5c00810, argv=0x0) at task/task_setup.c:570
#11 0x565e50ff in nxtask_setup_arguments (tcb=0xf5c00810, name=0x5679e580 "hpwork", argv=0x0) at task/task_setup.c:714
#12 0x565e414e in nxthread_create (name=0x5679e580 "hpwork", ttype=2 '\002', priority=224, stack=0x0, stack_size=8192, entry=0x565e54e1 <work_hpthread>, argv=0x0) at task/task_create.c:143
#13 0x565e42e3 in kthread_create (name=0x5679e580 "hpwork", priority=224, stack_size=8192, entry=0x565e54e1 <work_hpthread>, argv=0x0) at task/task_create.c:297
#14 0x565e5557 in work_start_highpri () at wqueue/kwork_hpthread.c:149
#15 0x565e3e32 in nx_workqueues () at init/nx_bringup.c:181
#16 0x565e3ec7 in nx_bringup () at init/nx_bringup.c:436
#17 0x565e3d96 in nx_start () at init/nx_start.c:809
#18 0x565e3195 in main (argc=1, argv=0xffe6b954, envp=0xffe6b95c) at sim/up_head.c:95
Change-Id: I096f7952aae67d055daa737e967242eb217ef8ac
Signed-off-by: chao.an <anchao@xiaomi.com>
like other related macro(e.g. INTMAX_MIN, INTMAX_MAX...)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8863599960b1a9b1c22ae9c35735a379a4c745b0
utilize the call inside nxtask_exit instead, also move
nxsched_suspend_scheduler to nxtask_exit for symmetry
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I219fc15faf0026e452b0db3906aa40b40ac677f3
-Move task_init() and task_activate() prototypes from include/sched.h to include/nuttx/sched.h. These are internal OS functions and should not be exposed to the user.
-Remove references to task_init() and task_activate() from the User Manual.
-Rename task_init() to nxtask_init() since since it is an OS internal function
-Rename task_activate() to nxtask_activate since it is an OS internal function
remove the TLS alignment check
Regression by:
--------------------------------------------------------
commit a6da3c2cb6
Author: Ouss4 <abdelatif.guettouche@gmail.com>
Date: Thu May 7 18:50:07 2020 +0100
arch/*/*_checkstack.c: Get aligned address only when
CONFIG_TLS_ALIGNED is enabled.
--------------------------------------------------------
commit c2244a2382
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Thu May 7 09:46:47 2020 -0600
Remove CONFIG_TLS
A first step in implementing the user-space error is
force TLS to be enabled at all times. It is no longer optional
Signed-off-by: chao.an <anchao@xiaomi.com>
All complaints fixed except for those that were not possible to fix:
- Used of Mixed case identifier in ESP32 files. These are references to Expressif ROM functions which are outside of the scope of NuttX.
- Remove per-thread errno from the TCB structure (pterrno)
- Remove get_errno() and set_errno() as functions. The macros are still available as stubs and will be needed in the future if we need to access the errno from a different address environment (KERNEL mode).
- Add errno value to the tls_info_s structure definitions
- Move sched/errno to libs/libc/errno. Replace old TCB access to the errno with TLS access to the errno.
So call 'make EXTRAFLAGS=-Wno-cpp' could suppress the warnings with pre-processor
directive #warning in GCC.
Change-Id: Iaa618238924c9969bf91db22117b39e6d2fc9bb6
Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
Necessary for dlfcn etc on ESP32, which has separate memory regions
for instruction and data.
known issues/todo
* consider something similar to dual heaps for PROTOECTED
* consider to adapt binfmt as well
The remaining errors:
Operator/assignment must be preceded with whitespace
I didn't fix them because they are in assembly code, which
nxstyle doesn't understand.
The remaining errors:
Mixed case identifier found
I didn't fix them because they were on ROM symbols,
which are not supposed to obey NuttX's coding style.
I skipped the following files because they were not simple.
I'll create separate PRs.
arch/xtensa/src/esp32/esp32_cpustart.c
arch/xtensa/src/common/xtensa_abi.h
boards/xtensa/esp32/esp32-core/include/board.h
Also, I skipped the following files and directories because
they looked too huge and/or foreign.
arch/xtensa/include/esp32/tie.h
arch/xtensa/include/xtensa/xtensa_corebits.h
arch/xtensa/src/esp32/hardware/
arch/xtensa/include/esp32/tie-asm.h
arch/xtensa/include/esp32/core-isa.h
arch/xtensa/include/xtensa/core.h
I also fixed a few "is is" style typos when unwrapping long lines.
