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14168 Commits

Author SHA1 Message Date
raiden00pl
5b9b3814f8 stm32: add CAN error support 2022-01-05 18:33:06 +08:00
Petro Karashchenko
4b190fbce1 arch/arm/samv7: correct number on interrupts 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:22 +08:00
Petro Karashchenko
6c2b40f98a typos: fix typos in many files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:07 +08:00
Petro Karashchenko
c7d3a674fd drivers/sensors/as5048b: fix lower half init issue 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 11:38:44 +08:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-02 20:50:30 +01:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-30 16:57:40 +08:00
Xiang Xiao
b92c90ee81 arch/arm: Fix rebase error in arm_backtrace_thumb.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 20:42:05 +08:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation 
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 12:09:54 +08:00
chao.an
cf2dfa8985 arch/arm/assert: move the arm_assert to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 05:09:30 -06:00
chao.an
579738c8fa arch/arm: move the backtrace implement to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 03:02:01 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:31:27 -06:00
chao.an
8eb999ff03 arch/arm: select ARM_THUMB by default for Cortex-M 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:30:53 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-27 21:01:19 -06:00
chao.an
6069433d2d arch/arm/cortex-a/r: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-23 06:54:32 -06:00
David Sidrane
74e692b3c1 stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite 
For FAT the same buffer is used for read and writes, there
  is a possibility a cache line is dirty. But the fs is
  not dirty and will not write the sector to disk. This can
  be seen  https://github.com/PX4/NuttX/pull/175

  When the system is busy that cache line can be evicted after the
  RX DMA has completed and overwrite the data in memory. The solution
  is to invalidate before the DMA to prevent an evection causing an
  overwite, and after the DMA it to insure coherency.
 2021-12-22 20:44:04 -06:00
chao.an
a0b61bbf6f arm/cortex-a/r: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
chao.an
2737701996 cortex-m/hardfault: add secure-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-21 07:08:13 -06:00
Juha Niskanen
422ceec99b Fix typos in comments and Kconfig files 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-21 03:26:16 -06:00
Simon Filgis
6cc48ff6ff arch/arm/samv7: initial support for LIN bus communication 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 18:23:05 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
David Sidrane
e269b5fa28 Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working." 
This reverts commit 0aecfe8691.
 2021-12-19 01:40:35 -06:00
raiden00pl
87a8b1bed9 nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832 2021-12-18 12:27:59 -06:00
raiden00pl
f3fdd5a019 arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice 2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4 arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected 2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79 arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes 2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support 2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0 arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device 2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines 2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018 arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex 2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6 arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset 2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13 arch/arm/src/nrf52/Kconfig: fix typos 2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2 arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types 2021-12-17 12:35:17 -06:00
raiden00pl
07d295b8db add 5-Clause Nordic License barrier for Nordic SoftDevice Controller 2021-12-17 11:22:39 -06:00
Gerson Fernando Budke
2dd5578d50 arch/arm/src/samv7/Kconfig: Define mem sizes 
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691 stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. 
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
 2021-12-16 01:28:05 -06:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump 
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-12 21:40:29 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040 
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
 2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B 
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
 2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support 
Signed-off-by: Huang Qi <no1wudi@qq.com>
 2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c 
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-12-07 23:28:54 -06:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh 
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
 2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation 
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config 
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver 
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors 
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 08:47:08 -06:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate 
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion 
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
 2021-11-24 20:38:23 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:48:00 -06:00
chao.an
4c76c356ef arch/arm: add more arch elf define 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:34:56 +09:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-11-18 19:27:07 -06:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX 
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-17 08:59:14 -03:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support 
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
 2021-11-16 14:45:03 -03:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache 
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code 
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-15 00:04:12 +01:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug. 
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver 
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
David Sidrane
c077361a8a imxrt:usb Fix EP type allocation 2021-11-04 13:23:25 -05:00
David Sidrane
95f7f4b9e6 imxrt:usb DMA cache aligned Buffers for Endpoints 2021-11-04 13:23:25 -05:00
David Sidrane
bd2bc1e351 imxrt:usbdev Clean up cache maintainence 2021-11-04 13:23:25 -05:00
David Sidrane
c3d10ad0aa imxrt:usbdev formatting cleanup 2021-11-04 13:23:25 -05:00
David Sidrane
532635129c imxrt:usdhc add proper support for dcache (wb) 2021-11-04 13:23:25 -05:00
David Sidrane
5022244339 imxrt mpuinit:Set Data and Code Type to Normal 
Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
 2021-11-04 13:23:25 -05:00
David Sidrane
34c3efcb91 imxrt mpuinit:Remove duplicate entry for ITCM (0x0) 2021-11-04 13:23:25 -05:00
David Sidrane
08d0434bad imxrt:mpu init handle dcache setting in MPU config 
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
   are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   is on then buffering operations are no-ops.

   This change enables MPU_RASR_C and MPU_RASR_B if
   CONFIG_ARMV7M_DCACHE is only set.

   if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
   MPU_RASR_C is enabled.

   N.B When caching is disalbed unaligned access may cause hard faults
   so add -mno-unaligned-access

   It is always safe to enable Buffering in FLASH to achive unaligned
   access leniency, as it is not written to.
 2021-11-04 13:23:25 -05:00
Alexander Lunev
60de445ab3 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because 
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
 2021-11-03 22:50:14 -05:00
ligd
2f4662c513 arch/arm: Remove -mcpu for fix warning 
warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8-m.main' switch

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-11-01 21:28:10 -05:00
ligd
8417b4726b Revert "arch/armv8-m: use -mfpu=auto based on -mcpu=cortex-m55" 
This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d.

Revert "arch/arm: Remove -march and -mtune"

This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.
 2021-11-01 21:28:10 -05:00