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114 Commits

Author SHA1 Message Date
Masayuki Ishikawa
5e7d48f4b0 arch: k210: Fix k210 timer on QEMU 6.1 or later 
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
  though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
  However, this fix works as a tentative solution.

Impact:
- K210 on QEMU only

Tested
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2023-04-06 00:54:08 -07:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-02-26 13:24:24 -08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
Petro Karashchenko
f952b8456c assert: switch from ASSERT(0/false) to PANIC 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-01-26 10:15:34 +08:00
Masayuki Ishikawa
df6bf3e614 arch: risc-v: Introduce RISCV_IPI macro for SMP 
Summary:
- This commit introduces RISCV_IPI macro for SMP
- Also, replace RISCV_IRQ_MSOFT with RISCV_IRQ_SOFT
- Remove duplicate irq_attach() from qemu_rv_irq.c

Impact:
- None

Testing:
- Tested with rv-virt:smp64 and maix-bit:smp on QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-10-07 14:49:29 +08:00
Xiang Xiao
bdeaea3742 Remove the unnessary empty line after label 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-09-30 17:54:56 +02:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t * 
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-09-24 21:26:56 +02:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place 
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-09-21 22:23:11 +02:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal 
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
 2022-06-28 14:41:56 +03:00
Masayuki Ishikawa
a0ff6f9fa6 arch: k210: Add a workaround for clock stabilization 
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue

Impact:
- k210 only

Testing:
- Tested with maix-bit

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-06-13 11:42:59 +08:00
Huang Qi
9d9d591b93 arch/risc-v: Unify common source include 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-05-31 07:59:33 +03:00
chao.an
3f65b562bb arch: inline up_interrupt_context() 
inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-05-26 04:36:07 +08:00
Petro Karashchenko
0fee5a2b84 nuttx: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-05-14 23:45:52 +08:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210 
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 21:47:29 +03:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t 
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-07 11:25:12 +03:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception 
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-06 22:48:46 +08:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-25 10:26:15 -03:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common 
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 17:38:18 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx 
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-17 15:43:30 +08:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-03 19:55:54 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-18 13:25:01 +08:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine 
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-15 11:40:34 +09:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-14 11:32:34 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-13 14:37:57 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs 
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-12 21:07:35 +09:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-10 13:09:32 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit" 
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-09 21:21:43 +08:00
Huang Qi
71d3ff1045 arch/risc-v: Remove g_serial_ok 
`WFI` is enough to wait the ready signal from master core,
so we can remove it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-23 18:28:37 +08:00
Huang Qi
422e005183 arch/risc-v: Move xxx_cpustart.c to common 
It's a common solution for MSIP and IPI based risc-v smp soc,
also works on qemu-rv smp (WIP).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-23 18:28:37 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-21 00:44:43 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case 
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Huang Qi
e97ba17451 arch/risc-v: Refine riscv_cpupause.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-16 23:11:32 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
Huang Qi
3200c936cc arch/risc-v: Refine riscv_cpuindex.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 21:54:05 +08:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00