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518 Commits

Author SHA1 Message Date
Gregory Nutt
2430049e3b arch/arm/include/xmc4: More support for Infineon XMC4xxx arch. Still incomplete. 2017-03-14 13:04:09 -06:00
ahb
67c86e5aa9 add LPC4337FET256 2017-03-09 10:30:28 +01:00
Gregory Nutt
ac6e552ff7 Fixes for coding standard: '*' needs to 'snuggle' with following variable name 2017-02-28 18:37:44 -06:00
Gregory Nutt
2e0ffc0ea3 Update some comments. 2017-02-26 09:15:57 -06:00
raiden00pl
3175b74428 Add basic support for the STM32F334 2017-02-26 12:39:44 +01:00
David Sidrane
61b10c5e58 Kinetis:Add LPUART to K66 chip 
Add KINETIS_NLPUART setting it to 1 and adjust KINETIS_NUART
  to removed UART5 as the K66 dioes not have UART5
 2017-02-25 07:02:56 -10:00
David Sidrane
1ba6eadcec Kinetis:Include the PMC features 2017-02-22 10:42:52 -10:00
David Sidrane
8525c266a1 Created a kinetis PMC versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
     K series family of parts.

     This added versioning and configuration features for the
     Kinetis PMC IP block.

     It is envisioned that in the long term as a chip is added.
     The author of the new chip definitions will either find
     the exact configuration in an existing chip define and
     add the new chip to it Or add the PMC fature configuration
     #defines to the chip ifdef list in
     arch/arm/include/kinetis/kinetis_pmc.h  In either case the
     author should mark it as "Verified to Document Number:"
     taken from the reference manual.

     The version KINETIS_PMC_VERSION_UKN has been applied to
     most all the SoCs in the kinetis arch prior to this commit.

     The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
     CONFIG_ARCH_CHIP_MK20DXxxxVLH7 All K64 and K66 have ben
     Verified PMC configurations.
 2017-02-22 10:42:52 -10:00
David Sidrane
5b550a37eb Kinetis:Include the SIM features 2017-02-22 10:42:52 -10:00
David Sidrane
d74f16ecb9 Kinetis:Created a kinetis SIM versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
   K series family of parts.

   This added versioning and configuration features for the
   Kinetis SIM IP block.

   It is envisioned that in the long term as a chip is added.
   The author of the new chip definitions will either find
   the exact configuration in an existing chip define and
   add the new chip to it Or add the SIM feature configuration
   #defines to the chip ifdef list in
   arch/arm/include/kinetis/kinetis_sim.h  In either case the
   author should mark it as "Verified to Document Number:"
   taken from the reference manual.

   The version KINETIS_SIM_VERSION_UKN has been applied to
   most all the SoCs in the kinetis arch prior to this commit.

   The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
   All K64 and K66 which not have Verified SIM configurations.
 2017-02-22 10:42:52 -10:00
David Sidrane
14bdf3af22 Kinetis:Fixed Typo in kinetis_mcg header 2017-02-22 10:42:52 -10:00
Gregory Nutt
e803e2c3f4 Costmetic changes from review of last PR. 2017-02-07 17:16:56 -06:00
David Sidrane
ff056cf9bd arch/arm/include/kinetis/kinetis_mcg.h 2017-02-07 12:38:28 -10:00
David Sidrane
2216ed52a9 Kinetis chip Adding K66 and inlcuding MCG versioning 
This includes arch/arm/include/kinetis/kinetis_mcg.h
  to bring in the MCG versioning and defines the KINETIS_K66
  family for the added SoCs:

   --------------- ------- --- ------- ------- ------ ------ ------ -----
   PART NUMBER     CPU     PIN PACKAGE  TOTAL  PROGRAM EEPROM SRAM  GPIO
                   FREQ    CNT          FLASH  FLASH
   --------------- ------- --- ------- ------- ------ ------ ------ -----
   MK66FN2M0VMD18  180 MHz 144 MAPBGA   2   MB    —    — KB  260 KB 100
   MK66FX1M0VMD18  180 MHz 144 MAPBGA  1.25 MB  1 MB   4 KB  256 KB 100
   MK66FN2M0VLQ18  180 MHz 144 LQFP     2   MB    —    — KB  260 KB 100
   MK66FX1M0VLQ18  180 MHz 144 LQFP    1.25 MB  1 MB   4 KB  256 KB 100
 2017-02-07 12:38:28 -10:00
David Sidrane
ec567371b6 Created a kinetis MCG versioning scheme pulled in by Kinetis chip.h 
The motvations is to version the IP blocks of the Kinetis
   K series family of parts.

   This added versioning and configuration features for the
   Kinetis MCG IP block.

   It is envisioned that in the long term as a chip is added.
   The author of the new chip definitions will either find
   the exact configuration in an existing  chip define and
   add the new chip to it Or add the MCG feature configuration
   #defines to the chip ifdef list in
   arch/arm/include/kinetis/kinetis_mcg.h  In either case the
   author should mark it as "Verified to Document Number:"
   taken from the reference manual.

   The version KINETIS_MCG_VERSION_UKN has been applied to
   most all the SoCs in the kinetis arch prior to this commit.

   The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
   All K64 and K66 which not have Verified MCG configurations.
 2017-02-07 12:38:28 -10:00
Gregory Nutt
9395704192 Kinetis, not Kinetics. 2017-02-07 08:20:52 -06:00
Wolfgang Reißnegger
a22dc9b1a8 SAM3/4: Add support for ATSAM4S4C. 2017-01-18 11:56:51 -08:00
Maciej Skrzypek
902c41462d Kinetis: New K60 has no Flex memory 2017-01-13 08:20:48 -06:00
Maciej Skrzypek
4becebe59f Kinetis: Fixed wrong MCG VDIV calculation on new NXP K60 2017-01-13 08:13:21 -06:00
Maciej Skrzypek
bc1826da63 Kinetis: Added CHIP_MK60FN1M0VLQ12 chip 2017-01-13 08:10:03 -06:00
Gregory Nutt
12148f0e33 Merged in paulpatience/nuttx/stm32 (pull request #180) 
STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
 2016-12-24 20:20:39 -06:00
Gregory Nutt
f063e4c5ac Remove Calypso architecture support and support for Calypso SERCOMM driver. 2016-12-13 18:35:52 -06:00
Gregory Nutt
26560cb9e1 i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. 2016-12-13 16:59:50 -06:00
Paul A. Patience
30bbeb6c1f STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs 2016-12-08 16:31:39 -05:00
Sebastien Lorquet
db24f237d7 STM32L4: Correct USART1/2 definitions. Use default mbed UART4 settings 2016-12-01 09:00:59 -06:00
Gregory Nutt
3353d9280f i.MX6: Disable non-cached region support. Add SCU register definitions. 2016-11-26 17:03:57 -06:00
Gregory Nutt
6ff6da083f Fix a few compile related issues from the last commit 2016-11-26 12:23:09 -06:00
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Gregory Nutt
f53e48199f Simplify and document some macros 2016-11-21 13:12:43 -06:00
Gregory Nutt
558784d06f Spinlocks: Added capability to provide architecture-specific memory barriers. This was for i.MX6 but does not help with the SMP problems. It is still a good feature. 2016-11-21 11:55:59 -06:00
Paul A. Patience
912fe06a86 Add architecture-specific inttypes.h 2016-10-27 16:01:38 -04:00
Marc Rechte
483f012600 Initial implemention of the STM32 F37xx SDADC module. There are also changes to ADC, DAC modules. SDADC has only been tested in DMA mode and does not support external TIMER triggers. This is a work in progress. 2016-10-25 14:14:10 -06:00
Gregory Nutt
48fb97e7b5 More of the same cloned typo 2016-10-19 10:11:45 -06:00
David Sidrane
bce382da52 Kinetis Support ARMV7 Common Vector and FPU 2016-10-18 12:00:01 -10:00
Gregory Nutt
56f2454c86 Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
Gregory Nutt
e6137ff129 Rename SAMD/L version of CONFIG_GPIO_IRQ to CONFIG_SAMDL_GPIOIRQ 2016-07-22 14:38:33 -06:00
Gregory Nutt
360efe03c1 Rename LP17xx version of CONFIG_GPIO_IRQ to CONFIG_LPC17_GPIOIRQ 2016-07-22 14:18:30 -06:00
Gregory Nutt
7a7998e4f9 Add support for the NXP Freedom-K64F board. This is primarily the work of Jordan Macintyre. I leveraged this code from https://github.com/jmacintyre/nuttx-k64f 2016-07-01 15:42:21 -06:00
Gregory Nutt
91dd3306c8 arch/arm/src/kinetis: Add basic support for the K64 family. Still moving register definition files to the kinetis/chip subdirectory. 2016-07-01 11:24:41 -06:00
David Sidrane
2de4ec2a47 Added as an author 2016-06-17 12:38:17 -10:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Konstantin Berezenko
b9e7b4ed70 Correct the can2 rx irq number for stm32f10xx chips 2016-06-10 10:52:58 -07:00
David Sidrane
d8ea955d69 Added STM32FF76xxx and STM32FF7xx families 2016-06-08 08:26:26 -06:00
Konstantin Berezenko
3fc7b6f0e5 Add stm32f105r support 2016-06-06 12:52:41 -07:00
Paul A. Patience
56b018d5db STM32: Fix typo 2016-06-06 12:02:11 -04:00
Gregory Nutt
f06a06952f LPC43xx: 1KB is 1024, not 1025. Noted by phreakuencies. 2016-05-31 06:22:10 -06:00
Konstantin Berezenko
5c6cd17d46 Add support for SPI 4 and 5 on stm32f411 chips 2016-05-27 11:08:18 -07:00
Gregory Nutt
4a63a7760a STM32: Hook 1-Wire driver into the build system 2016-05-25 12:31:32 -06:00
Alexander Vasiljev
ad6f37edfa Adds definitions for the LPC4337jet100 chip. 2016-05-24 07:03:50 -06:00
Konstantin Berezenko
a2253cdd3e Add basic configuration for stm32f411e-disco board with STM32F411VE chip 2016-05-20 16:38:25 -07:00
Aleksandr Vyhovanec
472115eda9 ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
Gregory Nutt
e0249bd025 STM32L4: Fix incorrect and conflicting definitions for STM32L4_NGPIOS and STM32L4_NGPIO_PORTS. Now there is only STM32L4_NPORTS. 2016-03-20 14:12:07 -06:00
Gregory Nutt
4e07680554 TLS: Forgot to add a file before last commit 2016-03-11 12:30:04 -06:00
Sebastien Lorquet
f4f03e6f02 Add port to the stm32L4 2016-03-10 09:59:16 -06:00
Gregory Nutt
5c75f83b55 ARMv7-A GIC: Add definitions for shared interrupt IDs 2016-03-10 07:13:40 -06:00
Gregory Nutt
400aead74a i.MX6: Add definitions for private processor interrupt IDs 2016-03-09 18:11:28 -06:00
Gregory Nutt
5c881e6d2e i.MX6: minor updates to last commit 2016-03-04 18:44:30 -06:00
Gregory Nutt
5100e7a623 i.MX6: Add some preliminary definitions to handle other family members 2016-03-04 18:43:16 -06:00
Gregory Nutt
bed5aa8731 Add IMX_NCPUS to i.MX6 chip.h file 2016-03-02 10:28:09 -06:00
Gregory Nutt
b466f18daf i.MX6: Some fixes for early compile issues 2016-03-01 14:15:43 -06:00
Gregory Nutt
52d777fa8d Merged in paulpatience/nuttx-arch/stm32f469 (pull request #56) 
STM32: Add support for STM32F46xxx
 2016-03-01 11:53:07 -06:00
Paul A. Patience
099990f3da STM32: Add support for STM32F46xxx 2016-03-01 12:18:07 -05:00
Gregory Nutt
fe7331900c i.MX6 add dummy chip.h header files 2016-02-29 14:08:16 -06:00
Gregory Nutt
0a9920a87a i.MX6: Add IRQ header file 2016-02-28 14:07:53 -06:00
Gregory Nutt
74e5336b39 Rename the imx/ directories to imx1/ to make room in the namespace for other members of the i.MX family 2016-02-27 10:29:24 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
5d449e9991 Add spinlock support for ARMv7-A architectures 2016-02-09 12:53:10 -06:00
Gregory Nutt
8f1b9886a9 Backport the new LPC17xx I2C driver to the LPC11xx in order to get the I2C_TRANSFER method 2016-01-30 12:17:01 -06:00
Gregory Nutt
f4115ab45c Correct LPC11xx priority definitions + fix some typos in comments 2016-01-25 07:36:26 -06:00
Lok Tep
1f4ce9e7f9 LPC43xx: Fix some NVIC priority definitions 2016-01-25 07:23:28 -06:00
Andrew Webster
43303a5786 Kinetis: add MK60N512VLL100 support 2016-01-21 19:07:18 -06:00
Gregory Nutt
c58393cb4d TMS570: Add GIO drivrs and GIO interrupt support 2015-12-25 13:44:49 -06:00
Gregory Nutt
ccc6913383 TMS570: Add definitions to support GIO second level interrupts 2015-12-25 11:43:38 -06:00
Gregory Nutt
ea1fa2e938 TMS570: SCI serial driver is now included in the build and compiles without error 2015-12-24 13:37:42 -06:00
Gregory Nutt
fa36531fee TMS570: Add default VIM channel assignments 2015-12-23 09:45:32 -06:00
Gregory Nutt
5794675247 TMS570: Memory map applies only to LS04x and LS03x. Peripheral numbering seems to start with 1, not 0 2015-12-16 14:10:45 -06:00
Gregory Nutt
bacf7cf07e ARMv7-R: fix some issues to get a clean compilation; TMS570: Add enough logic to support a minimum build. Not much there on the initial commit 2015-12-16 09:03:14 -06:00
Gregory Nutt
8cabb844ab TMS570: Hook into build/configuration system 2015-12-15 17:15:37 -06:00
Gregory Nutt
a6e035baeb TMS570: Add arch/arm/include/tms570 header files 2015-12-15 13:41:12 -06:00
Gregory Nutt
6a9876f960 SAMV7: Add an untested RSWDT driver 2015-12-06 09:56:45 -06:00
Gregory Nutt
a6d6c430d9 Changes to last merge from review for compliance to coding standards 2015-11-17 21:10:17 -06:00
Marwan Ragab
4999c14085 Added implementation to get 96-bit stm32 unique id 2015-11-17 21:34:41 -05:00
Gregory Nutt
0add2b8910 arch/arm/include/samv7: Add support for the SAME70 family 2015-11-14 11:36:21 -06:00
Lok Tep
3b4c71ef8d more revert 2015-11-09 14:51:00 +01:00
Lok Tep
a8416d2a26 revert 2015-11-09 14:41:08 +01:00
Lok Tep
7d386866af Merged nuttx/arch into master 2015-11-09 14:24:41 +01:00
v01d
79fad2843a lpc4337: WIP 2015-10-30 20:15:18 -03:00
Gregory Nutt
2b078150e8 Merged in marten_svanfeldt/nuttx-arch-public/for_upstream/stm32f429n (pull request #20) 
Add support for STM32F429N (TFBGA) chip
 2015-10-22 18:19:52 +08:00
Marten Svanfeldt
4d879a33ee Add support for STM32F429N (TFBGA) chip 
Signed-off-by: Marten Svanfeldt <marten@intuitiveaerial.com>
 2015-10-21 10:30:57 +08:00
Lok Tep
5983019a45 merge from nuttx 2015-10-08 22:57:34 +02:00
Gregory Nutt
9caf33e13b Standardize the width of all comment boxes in C header files 2015-10-03 07:28:30 -06:00
Gregory Nutt
cae0c9a2e3 Standardize the width of all comment boxes in header files 2015-10-02 17:47:23 -06:00
Gregory Nutt
36726b1bc4 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
Gregory Nutt
3a07b09b9a LPC43xx: Tweaks to pkolesnikov's LPC4370 changes to get a clean compilation 2015-10-01 10:00:25 -06:00
petekol
0eb1afcdef usb reset right 2015-09-30 17:13:32 +02:00
petekol
585fdf70d8 CONFIG_ARCH_CHIP_LPC4370FET100 2015-09-29 17:23:17 +02:00
Gregory Nutt
cbdafb96d5 Remove unused function setipsr. Cortex-M IPSR register is not writable 2015-09-23 08:38:32 -06:00
Gregory Nutt
139a31b875 stm32f74xx75xx_irq.h: STM32_IRQ_SAI2 is not defined but STM32_IRQ_SAI1 is defined twice. Noted by Vlad Chiorean 2015-09-22 07:45:59 -06:00
Gregory Nutt
a27e673967 SAMA5D2: Finish implementtion of the PIO driver 2015-09-12 11:36:06 -06:00