Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
allocation; use the previous calculation directly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
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That field is never used and, in most cases, is never initialized correctly.
This should have no impact to anything with the possible exception of free-running drivers.
Verified using CI builds only.
The comments at the top of the file say this:
```
This will be automatically registered
* - AXI SRAM is a 512kb memory area. This will be automatically registered
* with the system heap in up_allocate_heap, all the other memory
* regions will be registered in arm_addregion().
```
but the implementation was using SRAM123 instead. Furthermore, arm_addregion then re-adds SRAM123 again.
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This change makes it so that the timeout is set as part of the SDIO_WAITENABLE call instead of the SDIO_EVENTWAIT call. By doing so, you eliminate all opportunity for a race condition.
stm32h7:sdmmc Check if busy ended early
1.To support the different MCU in series(e.g. cortex-m0+)
2.It's redundant since we already specify in compliler option
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Several licenses were missed in the initial work
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Normally, statically allocated data goes in .bss, followed by the
initial stack, followed by HEAP. However, any data that is statically
allocated in SRAM4 with __attribute__ ((section (".sram4"))) will
clobber, and be clobbered by, the HEAP.
On STM32H7, BDMA can only access SRAM4. Therefore any BDMA buffers (or
any other data) placed in SRAM4 will expose this problem. In one case,
this manifested as a failure of NSH to start, because the SPI6 BDMA
buffers clobbered the /dev/console inode structs, which the OS
allocated earlier.
This PR ensures that only the rest of SRAM4, after any static data, is
added to the heap. This PR also allows SRAM4 to be completely excluded
from the heap by a new Kconfig, CONFIG_STM32H7_SRAM4EXCLUDE, similar
to what CONFIG_STM32H7_DTCMEXCLUDE does for the DTCM region.
Change required in linker scripts:
Every STM32H7 linker script must replace this:
.sram4 :
{
} > sram4
with this:
.sram4_reserve (NOLOAD) :
{
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
or link will fail with: undefined reference to '_sram4_heap_start'.
The Release Notes should document this for users with out-of-tree
boards.
arch/arm/src/stm32h7/Kconfig:
* Add config STM32H7_SRAM4EXCLUDE to allow excluding all of SRAM4
from the HEAP.
arch/arm/src/stm32h7/stm32_allocateheap.c:
* Only when including SRAM4 in the heap, define HAVE_SRAM4,
SRAM4_START, SRAM4_END, and SRAM4_HEAP_START.
* Add "Private Data" section.
* Add extern for_sram4_heap_start, which must be defined in the
board's linker script.
* arm_addregion(): Only add SRAM4 to the heap when configured to
do so, i.e., unless CONFIG_STM32H7_SRAM4EXCLUDE is defined, and
only add the portion of SRAM4 that is past any static data.
boards/arm/stm32h7/nucleo-h743zi/scripts/flash.ld:
boards/arm/stm32h7/nucleo-h743zi/scripts/kernel.space.ld:
boards/arm/stm32h7/nucleo-h743zi2/scripts/flash.ld:
boards/arm/stm32h7/stm32h747i-disco/scripts/flash.ld:
boards/arm/stm32h7/stm32h747i-disco/scripts/kernel.space.ld:
* Update all in-tree STM32H7 board linker scripts as described in
"Change required in linker scripts" above.
Testing:
* Successfully built all of the following configurations:
nucleo-h743zi2:jumbo
nucleo-h743zi2:nsh
nucleo-h743zi:nxlines_oled
nucleo-h743zi:elf
nucleo-h743zi:otg_fs_host
nucleo-h743zi:nsh
nucleo-h743zi:netnsh
nucleo-h743zi:pwm
stm32h747i-disco:nsh
* Tested with custom board.
* nxstyle.
References:
[1] See the dev@nuttx.a.o mailing list discussion started 2021/03/25:
"How to ensure HEAP will not overlap static DMA buffer?"
https://lists.apache.org/thread.html/recf2bb9043f8c9f53c10917e2adb2ec64fe35dc5e6f9a695a7ac6ecc%40%3Cdev.nuttx.apache.org%3E
[2] See arm_addregion() in arch/arm/src/stm32h7/stm32_allocateheap.c
Thanks to Gregory Nutt and David Sidrane for suggestions and reviews.
The maximum number of samples which can be handled without overrun depends on various factors.
This is the user's responsibility to correctly select this value.
Since the interfece to update the sampling time is available for all supported devices,
the user can change the default vaules in the board initialization logic and avoid ADC overrun.
arch/arm/src/stm32h7/stm32_dma.c:
* Include <inttypes.h> explicitly for format specifiers.
* In functions stm32_mdma_capable(), stm32_mdma_dump(),
stm32_sdma_setup(), stm32_sdma_capable(), stm32_sdma_dump(),
stm32_bdma_setup(), stm32_bdma_capable(), stm32_bdma_dump(),
stm32_dmamux_dump(), stm32_dmachannel(), stm32_dmafree(), and
stm32_dmadump():
Where appropriate, use format specifiers from <inttypes.h> in
calls to dmainfo(). This removes numerous compiler warnings
like:
warning: format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'uint32_t {aka long unsigned int}'
[-Wformat=]
* In function stm32_mdma_disable():
Remove wrong redefinition of 'dmachan' parameter as a local
variable. This fixes the following compiler error that occurs
when building with CONFIG_STM32H7_MDMA:
chip/stm32_dma.c:930:17: error: 'dmachan' redeclared as
different kind of symbol
DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
^~~~~~~
chip/stm32_dma.c:928:44: note: previous definition of 'dmachan'
was here
static void stm32_mdma_disable(DMA_CHANNEL dmachan)
^~~~~~~
chip/stm32_dma.c:930:43: error: 'handle' undeclared (first use
in this function); did you mean 'random'?
DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
^~~~~~
random
For example Windows RNDIS driver issues SETUP requests that are 76 bytes
long. Previously NuttX would read them all, but only if they arrive at
the same time. If host transfer scheduling causes a pause between the
two DATA packets, stm32_ep0out_receive() would proceed with an incomplete
transfer. The rest of the data could either be skipped by the error handler
branch, or be left in NAK state forever, stopping any further communication
on the endpoint.
This commit changes it so that the whole transfer has to be received before
SETUP handler is called. Depending on CONFIG_USBDEV_SETUP_MAXDATASIZE any
excess bytes will be discarded, but doing this in a controlled way ensures
deterministic behavior. In the specific case of RNDIS, the trailing bytes
are unused padding bytes and can be safely discarded.
arch/arm/src/stm32/Kconfig:
* configs ARCH_CHIP_STM32G431K, ARCH_CHIP_STM32G431C,
ARCH_CHIP_STM32G431R, ARCH_CHIP_STM32G431M, and
ARCH_CHIP_STM32G431V: Fix copy/paste of incorrect
names shown in the Kconfig menu.
nxstyle is complaining that the headers are defines outside
Included Files section and we have to duplicate the definitions
to the imported files to avoid build errors.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
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Since the original stm32l4 version of this code already has an ASF
license header do that for stm32l5, too.
Apply latest changes to stm32l4_spi.c to stm32l5_spi.c as well.
Update stm32l5/Kconfig to allow selection of SPI1/2/3.
Signed-off-by: Michael Jung <mijung@gmx.net>
The LSE crystal oscillator driving strength can only be decreased to the
lower drive capability (LSEDRV = 00b) once the LSE is running, but not
to any other drive capability. Instead of letting the user select a
value between 0 and 3 and then failing the build if the selected value
was not 0, make it a boolean option.
Signed-off-by: Michael Jung <mijung@gmx.net>
Ported from stm32f7/h7: If configured this way, ramp-up the LSE crystal
oscillator driving strength until the LSE starts up.
Signed-off-by: Michael Jung <mijung@gmx.net>
Because a thread of gnss receiver is created by pthread in the
AppBringUp task, the thread would be killed when AppBringUp
task exits.
Change to use kthread_create instead of pthread_create to prevent
this issue.
cxd56_gnss.c uses file descriptor operation from next change.
0536953 Kernel module should prefer functions with nx/kmm prefix
But this change need to add fcntl.h in include header.
So, add missing header.
As proposed by David Sidrane. Required drive strength is board specific
and should be defined in the respective board.h file.
Signed-off-by: Michael Jung <mijung@gmx.net>
Architecture support for STMicroelectronics STM32L552xx and STM32L562xx
MCUs. This is based on corresponding code for STM32L4, but has been
considerably adjusted. Tested with Nucleo-L552ZE-Q and STM32L562E-DK
boards with simple NSH configurations.
Signed-off-by: Michael Jung <mijung@gmx.net>
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Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
stm32f7:sdmmc WRITE COMPLETE prevent false triggers
stm32h7:sdmmc WRITE COMPLETE prevent false triggers
While testing PR #2989 on the H7 I noticed that the cards
were staying in 1-bit mode. The root cause was that the
scr read path was using DMA without an invlidate.
This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT,
but the sdmmc driver, did not use the delayed invalidate
nor would it work on 8 bytes.
The driver fully supported dcache mgt on runt buffers, but
the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it.
Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
it may have been valid at the time. But after the dcache operations
we fixed. It is not necessary and offers no benefit.
Summary:
- This commit fixes an error message in imx_enet.c
Impact:
- None
Testing:
- Build only
Suggested-by: David Sidrane <David.Sidrane@NscDg.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds CPU activity LED feature to cxd56_idle.c and cx56_irq.c
- An LED for the current CPU will turn off before calling WFI
- An LED for the current CPU will turn on when an interrupt happens
Impact:
- CONFIG_ARCH_LEDS_CPU_ACTIVITY=y only
Testing:
- defconfigs will be commited later.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The original commit was added to avoid hardfault but the
root cause was the stack corruption which has been fixed by
the previous commit. So let me revert the original commit.
Impact:
- SMP only
Testing:
- spresense:rndis_smp with nxplayer + telnet
This reverts commit 197187d826.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes hardfault when running nxplayer with rndis_smp
Impact:
- SMP only
Testing:
- Tested with rndis_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
In scenarios where there is suspicion that someone might be touching your data when you don't expect, you can setup a watchpoint, and then guard accesses that you know are valid. If the debugger halts due to the watchpoint, you'll see where the unexpected access is coming from.
Implement si_send/sendto/recvfrom with si_sendmsg/recvmsg, instead of
the other way round.
Change-Id: I7b858556996e0862df22807a6edf6d7cfe6518fc
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
Bug description:
CONFIG_SMP=y
Suppose we have 2 cores in SMP, here is the ps return:
PID GROUP CPU PRI POLICY TYPE NPX STATE STACK USED FILLED COMMAND
0 0 0 0 FIFO Kthread N-- Assigned 004076 000748 18.3% CPU0 IDLE
1 0 1 0 FIFO Kthread N-- Running 004096 000540 13.1% CPU1 IDLE
nsh> kill -4 0
or:
nsh> kill -4 1
system blocked.
Reason:
In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.
Fix:
Add condition to cover saved_irqcount == 0.
Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
