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12768 Commits

Author SHA1 Message Date
Aleksandr Vyhovanec
bf528f2071 packed_struct replaced by begin_packed_struct and end_packed_struct 2017-01-09 14:17:49 +03:00
Gregory Nutt
1f33654f2d Update some comments 2017-01-06 17:15:01 -06:00
Gregory Nutt
905a1ce10f SAMV7 Ethernet: Fix a compiler error introduced with commit 7467329a98 2017-01-06 16:49:18 -06:00
Gregory Nutt
13d00344c9 Add configuration to prevent selection of Windows native toolchains when using Ubuntu under Windows 10 2017-01-02 07:16:47 -06:00
Gregory Nutt
3a0413c048 Back out most of 34be3e7c3c and update README again. Windows native tools cannot be used with Ubuntu under Windows 10 now. For Cygwin, that support depends on the 'cygpath -w' tool to convert POSIX paths to Windows paths. There is no corresponding tool for Ubuntu under Windows 10. 2017-01-01 16:29:03 -06:00
Gregory Nutt
34be3e7c3c Add configuration support for builds with Ubuntu under Windows 10 2017-01-01 15:34:23 -06:00
Gregory Nutt
b9e2bd4f37 Merge branch 'master' of bitbucket.org:nuttx/nuttx 2016-12-31 12:25:20 -06:00
Gregory Nutt
17cbec16dc STM32 SDIO: Remove warning about unused variable in STM32 F4 builds. 2016-12-31 12:24:02 -06:00
Aleksandr Vyhovanec
a0814ece13 Fix typos 2016-12-30 09:49:31 +03:00
Masayuki Ishikawa
3a0ae405b2 i.MX6: Fix clearing GPT status register 2016-12-28 10:19:18 -06:00
Gregory Nutt
c9b15ebb6a Xtensa ESP32: Remove call to sched_lock()/unock() from inter-cpu interrupt logic. Results in recursive call to sched_mergepending(). 2016-12-25 09:26:20 -06:00
Gregory Nutt
b87fc91466 Revert "Xtensa SMP: Avoid a nasty situation in SMP by assuring that up_release_pending() is not re-entered." 
This reverts commit 733a57b4df.
 2016-12-25 07:12:46 -06:00
Gregory Nutt
49fae0ac6b Revert "All CMP platforms: Apply same fix verified on other platforms found on Xtensa." 
This reverts commit fb146abee0.
 2016-12-25 07:08:44 -06:00
Gregory Nutt
ea7b673174 Merged in david_s5/nuttx/upstream_sdio_1bit_dma (pull request #188) 
Allow dma in 1 bit mode in STM32F4xxx
 2016-12-24 20:21:03 -06:00
Gregory Nutt
12148f0e33 Merged in paulpatience/nuttx/stm32 (pull request #180) 
STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
 2016-12-24 20:20:39 -06:00
Gregory Nutt
efb86382c3 SMP: Back out deferred IRQ locking. This was accidentally merged into master and it looks like it is going to be more work than I thought to get it working again. Changes will go to the irqlock branch. 2016-12-24 19:53:37 -06:00
David Sidrane
df9ae3c13f Revert "STM32 serial: Make input hardware flow-control work with RX DMA. From Jussi Kivilinna" 
This reverts commit 265af48120.

Conflicts:
	arch/arm/src/stm32/stm32_serial.c
 2016-12-23 14:12:57 -10:00
Gregory Nutt
1b790a61cd Xtensa ESP32: Add stack checking logic. 2016-12-23 15:51:33 -06:00
Gregory Nutt
b262c6be91 Merge remote-tracking branch 'origin/master' into irqlock 2016-12-23 13:09:11 -06:00
Gregory Nutt
f3d755c16f Some trivial, cosmetic changes for irqlock branch 2016-12-23 13:04:33 -06:00
Gregory Nutt
c7f5435637 Implement deferred IRQ locking. The rest of the support for Xtensa. Untested. 2016-12-23 11:56:45 -06:00
Frank Benkert
29cf2eb342 AMV7: CAN: Make delete_filter functions more robust 2016-12-23 11:45:21 -06:00
Gregory Nutt
cb1cc66d81 Implement deferred IRQ locking. Adds partial support for Xtensa. More is needed. 2016-12-23 11:39:44 -06:00
Gregory Nutt
9f7ba21f8a Implement deferred IRQ locking. Adds support for simulator. 2016-12-23 11:28:43 -06:00
Gregory Nutt
729ee7c099 ARMv7-A: Small improvement to some register handling in context restoration. 2016-12-23 11:13:18 -06:00
Gregory Nutt
d9ef0e86fb Fix a couple of errors in the last commit 2016-12-23 10:45:13 -06:00
Gregory Nutt
c00a1870d7 Implement deferred IRQ locking. Adds support for ARMv7-A. 2016-12-23 10:17:36 -06:00
Gregory Nutt
e6fff09ef8 Implement deferred IRQ locking. So far only form ARMv7-M. 2016-12-23 07:55:41 -06:00
David Sidrane
76ceb37553 Allow dma in 1 bit mode in STM32F4xxx 2016-12-22 09:19:37 -10:00
Gregory Nutt
5f9caad078 Xtensa ESP32: Correct copyright info; update some comments 2016-12-22 12:34:55 -06:00
Gregory Nutt
714e6f80ca Xtensa ESP32: Corrects a problem with dispatching to signal handlers: Cannot vector directly to the signal handling function as in other ABIs under the Xtensa Window ABI. In that case, we need to go through a tiny hook when performs the correct window call (call4) otherwise registers will be scrambled in the signal handler 2016-12-22 11:19:38 -06:00
Gregory Nutt
d9a64b9ca9 Xtensa ESP32: Some fixes from integration of ostest configuration. Almost works: There are some assertions in xtensa_sigdeliver() 2016-12-22 09:34:39 -06:00
Gregory Nutt
fb146abee0 All CMP platforms: Apply same fix verified on other platforms found on Xtensa. 2016-12-21 14:04:09 -06:00
Gregory Nutt
733a57b4df Xtensa SMP: Avoid a nasty situation in SMP by assuring that up_release_pending() is not re-entered. 2016-12-21 13:34:01 -06:00
Gregory Nutt
588d2b506f Xtensa ESP32: Oddly, an rsync barrier when writing to co-processor register corrects problem. 2016-12-21 08:04:48 -06:00
Gregory Nutt
1b7162a0db Eliminate a warning 2016-12-21 08:04:48 -06:00
Gregory Nutt
81697f2285 Xtensa ESP32: Fix APP CPU startup... Can't use semaphores on the IDLE thread. 2016-12-20 11:26:37 -06:00
Gregory Nutt
6d5a718b98 Xtensa ESP32: A few fixes for APP CPU start-up 2016-12-20 10:38:27 -06:00
Gregory Nutt
4e9a0ffea5 Xtensa ESP32: Update APP CPU startup logic to match current Expressif example code. 2016-12-20 09:00:04 -06:00
Gregory Nutt
3b681586c0 Xtensa ESP32: Missing prologue/epilogue macros on C callable function 2016-12-20 08:31:36 -06:00
Gregory Nutt
5666bf30a7 Review of last PR 2016-12-20 07:08:46 -06:00
Young
07b70fcc20 Improve the PWM logs 2016-12-20 17:05:51 +08:00
Young
9d355e12d5 Support indefinite number of pulses generation in PULSECOUNT mode 2016-12-20 14:08:31 +08:00
Young
e35406f7d6 Support PWM_PULSECOUNT feature for TI tiva 2016-12-20 13:20:04 +08:00
Gregory Nutt
e5182acbe3 Xtensa ESP32: Make sure that SMP configuratin still builds without errors. 2016-12-19 14:12:19 -06:00
Gregory Nutt
e61549d8b9 Xtensa ESP32: Clean-up and fixes from last commits 2016-12-19 13:57:37 -06:00
Gregory Nutt
097f09cb02 Xtensa ESP32: Corrects timer initialization and timer input frequency. 2016-12-19 11:50:28 -06:00
Gregory Nutt
a9a39800a4 Xtensa ESP32: Fixes some double faults and user errors, but I do not fully understand why. 2016-12-19 11:14:08 -06:00
Gregory Nutt
886ce88b4f Xtensa ESP32: Automatically mount /proc at start-up. 2016-12-19 09:43:16 -06:00
Gregory Nutt
2b0b698d72 ESP32 Serial: Add logic to prevent infinite loops in interrupt handler. 2016-12-18 16:04:25 -06:00
Gregory Nutt
71bb79a6c7 ESP32 Serial: Fix some register bit definitions. 2016-12-18 15:11:34 -06:00
Gregory Nutt
4bd530d026 Xtensa ESP32: Last change should be conditioned on the window ABI. 2016-12-18 13:17:31 -06:00
Gregory Nutt
665c1647b5 Xtensa ESP32: Need to spill registers to memory as the last dying action before switching to a new thread. 2016-12-18 12:54:47 -06:00
Gregory Nutt
586f0aab50 Fix context save logic when called in window ABI configuration. Add an IDLE stack. Don't depend on the mystery stack received from the bootloader. 2016-12-18 10:08:08 -06:00
Gregory Nutt
93e6d16f75 Xtensa ESP32: wsr, not rsr. 2016-12-17 11:23:10 -06:00
Gregory Nutt
a88c50d366 Xtensa ESP32: Need to clone some logic for syncrhonous context switch. Window spill logic in the conmon restores logic is inappropriate in this context 2016-12-17 11:00:12 -06:00
Gregory Nutt
6b80e5f15f Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore 2016-12-17 11:00:12 -06:00
Gregory Nutt
8de1127899 Xtensa ESP32: Using wrong register to disable interrupts. 2016-12-17 11:00:12 -06:00
David Sidrane
ec85425041 STM32: Fix some STM32F7 copy paste errors 2016-12-17 08:31:12 -06:00
Gregory Nutt
38ebe6c13f Xtensa ESP32: Change that should have been included in a previous commit was not. 2016-12-17 08:11:32 -06:00
Gregory Nutt
05e798488b One register getting clobber on context save 2016-12-17 08:10:10 -06:00
Gregory Nutt
adbacfc42c Xtensa ESP32: Fix a duplicate in Kconfig files. Level 1 should return via RFE. 2016-12-17 07:07:33 -06:00
Gregory Nutt
6599feb310 Xtensa ESP32: Fixes a few issue with restoring registers on interrupt return, but there is still a problem 2016-12-16 17:56:22 -06:00
Gregory Nutt
cdd8dc72a5 Xtensa ESP32: Basically a redesign of the interrupt dispatch logic. 2016-12-16 15:36:52 -06:00
Gregory Nutt
d4ad5f04d3 Xtensa ESP32: Minor rearchitecting of how CPU interrupts are enabled. MOre to come. 2016-12-16 14:13:09 -06:00
Gregory Nutt
cd3d414ba2 Xtensa: Fix some missing SMP logic 2016-12-16 13:37:28 -06:00
Gregory Nutt
34a994b0f6 Correct a logic problem the prevented dumping the IDLE thread's stack on an assertion 2016-12-16 13:21:01 -06:00
Gregory Nutt
6337fadd8c Missing escape character on CR of CR-LF expansion. 2016-12-16 10:49:42 -06:00
Gregory Nutt
935e49f5bb Update some comments 2016-12-16 09:38:08 -06:00
Gregory Nutt
f1a5b91cd8 Use r6, not r2 when passing paramters with call4 2016-12-16 09:21:44 -06:00
Gregory Nutt
41cf32a20e Fix windowspill register handling + Use r6, not r2 when passing paramters with call4 2016-12-16 09:20:36 -06:00
Gregory Nutt
aa5a8b0ca2 Xtensa: Make sure that all C callable assembly functions includes ENTRY prologue and RET epilogue. 2016-12-15 14:02:19 -06:00
Gregory Nutt
c56268b416 Fix missing CALL0 ABI condition. 2016-12-15 11:06:41 -06:00
Gregory Nutt
ea9e6c48e4 Cosmetic update to comments. 2016-12-15 10:43:34 -06:00
Gregory Nutt
10b9a10d2f Xtensa ESP32: Fix several build-related issues associated with vector section 2016-12-15 10:08:26 -06:00
Gregory Nutt
4795d58e03 Back out most of 46dbbe837e. The order is correct -- or, rather, the order is the same as the order that response data is provided. Change the order will break all other drivers. 2016-12-15 07:16:24 -06:00
Gregory Nutt
b5e979d58f ESP32: Fix a couple of bugs associated with handling of CPU interrupts. 2016-12-14 13:31:44 -06:00
Gregory Nutt
4052ec2d90 Add missing ENTRY() and RET() macros in C callable assembly language. At one time I though the that the ESP32 support the CALL0 ABI. I was mistaken so there may be a few more like this. 2016-12-14 12:14:51 -06:00
Gregory Nutt
730ca4ce41 Fix missing semicolons in DEBUGASSERT statements 2016-12-14 09:06:09 -06:00
Angus Gratton
dd5e47a418 ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...) 2016-12-14 08:15:03 -06:00
Gregory Nutt
f063e4c5ac Remove Calypso architecture support and support for Calypso SERCOMM driver. 2016-12-13 18:35:52 -06:00
Gregory Nutt
c83da3c48f Remove minnsh configurations and support logic: up_getc() and lowinstream. 
This was an interesting exercise to see just how small you could get NuttX, but otherwise it was not useful:  (1) the NSH code violated the OS interface layer by callup up_getc and up_putc directly, and (2) while waiting for character input, NSH would call up_getc() which would hog all of the CPU.  NOt a reasonably solution other than as a proof of concept.
 2016-12-13 18:01:23 -06:00
Gregory Nutt
26560cb9e1 i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. 2016-12-13 16:59:50 -06:00
Frank Benkert
a36ed28790 SAMV7: MCAN: Prevent Interrupt-Flooding of ACKE when not connected to CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node acknowledges the message sent. This will also occur if the device is not connected to the can-bus. The CAN-Standard declares, that the Chip has to retry a given message as long as it is not sent successfully (or it is not cancelled by the application). Every time the chip tries to resend the message an Acknowledge-Error-Interrupt is generated. At high baud rates this can lead in extremely high CPU load just for handling the interrupts (and possibly the error handling in the application). To prevent this Interrupt-Flooding we disable the ACKE once it is seen as long we didn't transfer at least one message successfully. 2016-12-13 11:22:54 -06:00
Gregory Nutt
edeee90c66 i.MX6 interrupt handling: Additional logic needed to handle nested interrupts when an interrupt stack is used 2016-12-13 10:04:38 -06:00
Gregory Nutt
113d8bdcca Fix some SMP-related compilation errors 2016-12-09 17:10:59 -06:00
Gregory Nutt
70de0ee39f Merge remote-tracking branch 'origin/master' into cancelpt 2016-12-09 14:42:48 -06:00
Gregory Nutt
8b81cf5c7e Merged in david_s5/nuttx-3/david_s5/typo-in-stm32f76xx77xx_pinmaph-edited-on-1481298811328 (pull request #182) 
Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket
 2016-12-09 10:54:39 -06:00
Alan Carvalho de Assis
35023e4c6d LPC43xx SD card: Correct pin configuration options needed for SD card pins. 2016-12-09 10:54:17 -06:00
David Sidrane
64ae731c99 stm32_allocateheap.c edited online with Bitbucket 2016-12-09 16:35:35 +00:00
Gregory Nutt
018db84567 Flesh out more cancellation point logic. 2016-12-09 10:31:40 -06:00
David Sidrane
e7597d1754 Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket 2016-12-09 15:53:58 +00:00
David Sidrane
df9c5b33a0 Added STM32F469 RAM size and deliberated STM32F446 size 2016-12-09 05:02:31 -10:00
Paul A. Patience
30bbeb6c1f STM32: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs 2016-12-08 16:31:39 -05:00
David Sidrane
dd309ad9e8 I was wrong - the original commit was correct. Assume a write op on the last word: address of 0xxxxxfe and count of 2. It is a valid operation and address+count is == STM32_FLASH_SIZE - so that is OK 2016-12-08 21:14:31 +00:00
David Sidrane
c77bda47d7 BUGFIX:STM32F427 was rebooting. Over reached family. 2016-12-08 20:31:56 +00:00
Gregory Nutt
ab43681f15 Update TODO and some comments. 2016-12-08 10:24:40 -06:00
Pierre-noel Bouteville
017773eda3 EFM32: Fix a compilation error 2016-12-07 09:13:13 -06:00
Gregory Nutt
a7b688e87b sched notes: Add additional note to see if/when CPU is started in SMP mode. 2016-12-07 09:08:20 -06:00
Gregory Nutt
dc79e35d65 For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem. 2016-12-07 09:06:41 -06:00
Gregory Nutt
b9be0279b1 Coding standard requires a blank line after every comment. 2016-12-07 06:52:15 -06:00
Gregory Nutt
cae56b825b Merged in david_s5/nuttx/upstream_to_greg_SDIO_fix (pull request #177) 
Allow a config to override the SDIO clock edge setting
 2016-12-07 12:48:11 +00:00
David Sidrane
cbf863b1ca STM32F7: Allow the config to override the clock edge setting 2016-12-06 13:43:57 -10:00
David Sidrane
7cc0a06f44 STM32: Allow the config to override the clock edge setting 2016-12-06 13:30:07 -10:00
Gregory Nutt
e190e1ee5b stm32fxxxxx_otgfs.h edited online with Bitbucket 2016-12-06 15:58:05 +00:00
Gregory Nutt
8e447453e1 Add a missing bit field definitions that was lost when stm32_otgfs.h was deleted. 2016-12-06 09:22:03 -06:00
Gregory Nutt
d6437407b1 Fix broken build. Previous commit removed a file that was being used. 2016-12-06 09:03:00 -06:00
Gregory Nutt
b6a21edb42 Merged in david_s5/nuttx/upstream_to_greg (pull request #176) 
Upstream to greg
 2016-12-06 12:22:42 +00:00
David Sidrane
885b718552 Expanded otgfs support to stm32F469 and stm32f446 
Added missing bits definitions
   Used stm32F469 and stm32f446 bit definitions
   Removed unsed header file
 2016-12-05 18:07:57 -10:00
David Sidrane
50f36f8967 Added support for stmf469 SAI and I2S PLL configuration and STM446 fixes 2016-12-05 14:21:46 -10:00
David Sidrane
8b31eda4d8 Added Timers 2-5 and control of SAI and I2S PLLs 2016-12-05 14:19:56 -10:00
Gregory Nutt
9ed0387379 Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount /proc on startup. 2016-12-05 08:52:40 -06:00
Gregory Nutt
6cff0a7012 SAMA5 PWM: Minor improvement to a loop 2016-12-04 15:48:13 -06:00
Gregory Nutt
39c4ecbcd0 SAMA5 PWM: Costmetic 2016-12-04 15:39:53 -06:00
Gregory Nutt
ff76ebfd31 SAMA5 does not build when executing from SDRAM before board frequencies are not constant. Rather, the bootloader configures the clocking and we must derive the clocking from the MCK left by the bootloader. This means lots more computations. This is untested on initial commit because I don't have a good PWM test setup right now. 2016-12-04 15:25:43 -06:00
Masayuki Ishikawa
d92a7886a4 SAM3/4: Add SMP support for the dual-core SAM4CM 2016-12-04 07:23:31 -06:00
Masayuki Ishikawa
84900298b7 ARMv7-M SMP: Applied the latest changes for ARMv7A-SMP 2016-12-04 06:49:49 -06:00
Gregory Nutt
9c65b0321d Eliminate some warnings 2016-12-04 06:24:24 -06:00
Gregory Nutt
920a9592d1 Fix a naming collision introduced in last big commit 2016-12-03 18:19:08 -06:00
Gregory Nutt
7467329a98 Eliminate CONFIG_NO_NOINTS. Lots of files changed -> lots of testing needed. 2016-12-03 16:28:19 -06:00
Gregory Nutt
ad3897531f C5471 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 12:17:55 -06:00
Gregory Nutt
43459fe75e DM09x0 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 11:42:15 -06:00
Gregory Nutt
41e35c88bf eZ80 Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 10:43:35 -06:00
Gregory Nutt
eba1e076ec PIC32MX/Z Ethernet: Now supports CONFIG_NET_NOINT 2016-12-03 09:50:14 -06:00
Gregory Nutt
bfa1da14e2 LM3S Ethernet now supports CONFIG_NET_NOINTS 2016-12-03 08:32:49 -06:00
Gregory Nutt
1851e9e837 SAMA5D3: Add support for CONFIG_NET_NOINTS to EMACA and GMAC driver. 2016-12-02 16:36:27 -06:00
Gregory Nutt
b95e1f656b i.MX6: Add an untested SPI driver taken directly from the i.MX1 port. 2016-12-02 13:51:07 -06:00
Gregory Nutt
c0cbea2550 Remove RGMP and RGMP drivers. 2016-12-02 09:49:33 -06:00
Alan Carvalho de Assis
cd119ad544 GPDMA driver for the LPC43xx. The GPDMA block is basically the same as the LPC17xx. Only the clock configuration is different and LPC43xx has four different DMA request sources, where LPC17xx has only two. 2016-12-01 18:01:04 -06:00
Sebastien Lorquet
db24f237d7 STM32L4: Correct USART1/2 definitions. Use default mbed UART4 settings 2016-12-01 09:00:59 -06:00
Alan Carvalho de Assis
8b3a6d1eca LPC43 SD/MMC: Correct some git definitions on SMMC control register in lpc43_sdmmc.h 2016-11-30 14:50:32 -06:00
Janne Rosberg
a03d26e88d stm32_otghshost: if STM32F446 increase number of channels to 16 2016-11-30 12:17:12 -06:00
Gregory Nutt
44668c00a0 LPC17 Ethernet: Tiny, trivial, cosmetic spacing change 2016-11-30 12:16:21 -06:00
Gregory Nutt
b29b77532f Update some comments 2016-11-29 18:17:37 -06:00
Gregory Nutt
934aded293 arch/: Adapt all Ethernet drivers to work as though CONFIG_NET_MULTIBUFFER were set. Remove all references to CONFIG_NET_MULTIBUFFER 2016-11-29 16:06:48 -06:00
Gregory Nutt
f06d521c10 Minor extensions to some comments 2016-11-29 10:01:38 -06:00
Ramtin Amin
137586f50a Misoc LM32: Add logic to flush/invalidate caches 2016-11-29 09:09:28 -06:00
Gregory Nutt
79bb895073 i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set. 2016-11-29 08:34:22 -06:00
Gregory Nutt
a8b69c3efe Back out a debug change that was included in commit 2016-11-29 07:51:49 -06:00
Marc Rechté
3f91bd6056 STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, up to three interfaces. 2016-11-29 07:03:54 -06:00
Gregory Nutt
1f9e3ae5f1 Misoc LM32: Make naming consistent, lm32_sigdeliver vs. up_sigdeliver. 2016-11-28 11:18:07 -06:00
Ramtin Amin
b568bfa813 Misoc LM3: Add Misoc Ethernet driver. Integrate network support into configs/misoc/hello. Remove configs/misoc/include/generated directory. I suppose the the intent now is that this is a symbolic link? DANGER! This means that you cannot compile this code with first generating these files a providing a symbolic link to this location! 2016-11-28 11:08:29 -06:00
Gregory Nutt
d65be718c2 sched_note: Extend OS instrumentation to include some SMP events. 2016-11-27 17:14:57 -06:00
Gregory Nutt
cbf98ae0a0 ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary. 2016-11-27 13:18:34 -06:00
Gregory Nutt
21e42d18c1 ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0 2016-11-27 11:28:24 -06:00
Gregory Nutt
cd54c71dc1 ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however. 2016-11-27 10:21:46 -06:00
Gregory Nutt
278d8330d6 arm_scu.c edited online with Bitbucket. Fux some typos. 2016-11-27 02:59:42 +00:00
Gregory Nutt
3f6eadc238 ARMv7-A: Fix some SCU SMP logic 2016-11-26 18:41:48 -06:00
Gregory Nutt
546e352830 i.MX6: Add some controls to enable SMP cache coherency in SMP mode 2016-11-26 17:46:20 -06:00
Gregory Nutt
3353d9280f i.MX6: Disable non-cached region support. Add SCU register definitions. 2016-11-26 17:03:57 -06:00