Summary:
- This commit adds MMU support for qemu-rv
- Please note that mtimer is disabled for S-mode because
the mtimer needs to be accessed in M-mode
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 (will be pushed later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides an example of Asymmetric Multiprocessing (AMP). The
master from Linux sends pings that this NuttX echoes back. The system
uses RPMsg from OpenAMP.
The Inter-Hart Communication module is present in the vendor's software
stack with the tag "2021.11". The software is present on github at the
polarfire-soc project. The following conditions must be met:
1. FPGA programmed with 2021.11 software
2. HSS (Vendor bootloader) with 2021.11 software
3. U-boot and Linux kernel from 2011.11 software
Currently the IHC works as a slave only on the hart number 4.
On the NuttX side, this patch uses rptun that incorporates rpmsg and
virtio. If it used only rpmsg and virtio, the future maintenance would
likely be much heavier. Using rptun also simplifies many things.
Upon success, the master side from Linux may issue an example test:
root@icicle-kit-es-amp:/opt/microchip/amp/rpmsg-pingpong# ./rpmsg-pingpong
However, the rpmsg-pingpong.c (compiled on target with gcc), may need to
be modified as seen below to match the device id:
- char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.0";
+ char *rpmsg_dev="virtio0.rpmsg-amp-demo-channel.-1.1024";
This work uses a separate linker script. Due to a bug yet unknown to date,
a small NuttX, when loaded by the vendor HSS bootloader, will cause the
Linux kernel to hang at boot. Thus, the binary size is increased with
a section 'filler_area' whose only purpose is to increase the image size
so that the Linux kernel will boot up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Implement a generic access rights modification procedure instead
of the procedures that only do one thing (enable/disable write)
to one section (text).
Summary:
- Because a context switch issue still exists with FPU,
it should be enabled only if EXPERIMENTAL=y
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When the .elf file is loaded from disk, the kernel must be given write
access to the allocated .text section in the task's address environment.
The access is removed after the elf is loaded and relocations are done.
NOTE:
The reason this works for the ARM implementation, is that the ARM MMU
can be configured to give write access for the privileged mode, but
revoke write access for the user mode.
Regardless, it would be smart to revoke write access even for the
kernel, when the kernel does not need it. This framework allows doing
that, if someone wishes to take up the task.
Summary:
- This commit adds support for semihosting and hostfs
Impact:
- None
Testing:
- Tested with nsh and nsh64 (defconfig will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Mappings are done with vaddr=paddr.
- I/O space mapped with two gigapages
- Kernel space mapped to statically allocated page tables. 2MB of kernel
memory is supported.
- Page pool is mapped to the kernel space, to allow virtual memory access
for the kernel e.g. to initialize the page memory when it is allocated.
by renaming riscv_dispatch_syscall to sys_callx, so the caller
don't need the immediate step(syscallx->riscv_dispatch_syscall)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Using the Kconfig macro does not work for RISC-V target, as there the
user heap follows .data/.bss and does not obey any Kconfig provided
boundary.
Added stubs for ARM and Z80 also.
Copy the kernel mappings to the new (user) address environment. The
copyuing is done exactly once. This relies on the fact that the kernel
L1/L2 mappings will never change, as all of the kernel memory is mapped
upon boot.
This implements initial support for kernel build (address environments,
page allocator) for RISC-V.
This is done a bit differently compared to the ARMV7 implementation:
- Support implemented for Sv39 MMU, however the implementation should be
extensible for other MMU types also.
- Instead of preserving and moving the L1 references around, a canonical
approach is used instead, where the page table base address register
is switched upon context switch.
- To preserve a bit of memory, only a single L1/L2 table is supported,
this gives access to 1GiB of virtual memory for each process, which
should be more than enough.
Some things worth noting:
- Assumes page pool is mapped with vaddr=paddr mappings
- The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are
ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used
for ARCH_DATA_RESERVE
- ARCH_DATA_RESERVE is placed at the beginning of the userspace task's
address environment
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
if FPU is disabled.
- This commit fixes this issue.
Impact:
- K210 with QEMU only
Testing:
- Tested with qemu-5.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.
Signed-off-by: chao.an <anchao@xiaomi.com>
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".
Signed-off-by: chao.an <anchao@xiaomi.com>
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group. Accessing the group from dumponexit will crash.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
filelist = tcb->group->tg_filelist;"
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.
SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.
Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
DEBUGASSERT(lower);
^~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: chao.an <anchao@xiaomi.com>
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.
Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.
The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.
In this patch, we handle the misaligned access by software to make
system run continue.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start
NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
