Stm32 rtc small patches
* RTC: canceling an alarm marks it as inactive
* STM32L4, STM32F4, STM32F7 RTC: fix reading alarm value that is more than 24h in future
* STM32F0 RTC: fix backup register count in stm32_rtcc.h
All other STM32: SHIFTR_SUBFS_MASK was correct in STM32F0 only
* STM32L1: use correct EXTI line definitions
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Initial ADC support for the STM32F33XX
* stm32_adc.h: add JEXTSEL definitions and hrtim trigger configuration
* stm32_adc.c: move STM32F33 ADC logic to a separate file
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L4 small fixes to RTC
* STM32L4 RTC: init mode was never exited because nested locking in rtc_synchwait() disabled backup domain access
* STM32L4 RTC: use backup register magic value instead of INITS bit
The INITS (bit 4) of RTC_ISR register cannot be used to reliably
detect backup domain reset. This is because we can operate our
device without ever initializing the year field in the RTC calendar
if our application does not care about correct date being set.
Hardware also clears the bit when RTC date is set back to year 2000:
nsh> date -s "Jan 01 00:00:00 2001"
rtc_dumptime: Setting time:
rtc_dumptime: tm: 2001-01-01 00:00:00
rtc_dumpregs: New time setting:
rtc_dumpregs: TR: 00000000
rtc_dumpregs: DR: 00012101
rtc_dumpregs: CR: 00000000
rtc_dumpregs: ISR: 00000037
...
nsh> date -s "Jan 01 00:00:00 2000"
rtc_dumptime: Setting time:
rtc_dumptime: tm: 2000-01-01 00:00:00
rtc_dumpregs: New time setting:
rtc_dumpregs: TR: 00000000
rtc_dumpregs: DR: 0000c101
rtc_dumpregs: CR: 00000000
rtc_dumpregs: ISR: 00000027 <--- Bit 4 went missing!
...
This patch allows us to do:
stm32l4_pmstop(true);
/* Stop mode disables HSE/HSI/PLL and wake happens with default system
* clock. So reconfigure clocks early on Stop mode return.
*/
stm32l4_clockconfig();
without stm32l4_clockconfig() doing spurious and harmful backup domain
reset in rcc_resetbkp().
* STM32L4 RTC: put back the SSR race condition workaround
ST has confirmed that the issue has not been fixed, and that it applies
to STM32L4 too (was not in errata sheets due to documentation bug)
See discussion:
https://community.st.com/thread/43710-issue-with-rtc-maximum-time-resolution
* STM32F4, STM32L4, STM32F7 RTC: add more CONFIG_RTC_NALARMS > 1 to reduce code size
* STM32L4: rename stm32l4_rtcc.c to stm32l4_rtc.c to better match STM32F7
Cosmetic changes to comments
* STM32, STM32L4, STM32F7 RTC: stray comment and typos in chip/stm32_rtcc.h
* STM32L4 RTC: change maximum alarm time from 24h to one month
Approved-by: Gregory Nutt <gnutt@nuttx.org>
BCM2708: Add enough infrastructrue (more stubs) to get a clean compilation of the Pi Zero configuration (with many undefined things at link time).
BCM2708: Add basic interrupt handling logic
BCM2708: Add interrupt register definitions.
BCM2708: Add irq.h header file
BCM2708/Pi zero: bcm_boot.c and bcm_memorymap.h now compile. Added pizero linker script.
BCM2708/Pi Zero: Add Make.defs needed to build.
arch/arm/include/bcm2708, arch/arm/src/bcm2708, configs/pizero: Add some basic build and configuration logic.
configs/pizero: Add some basic structure of the Rasperry Pi Zero port.
Created directory configs/pizero. Nothing there now but a README.txt file.
Add initial boot.c and memorymap.c files
Author: Alan Carvalho de Assis <acassis@gmail.com>
Add AUX/UART/SPI registers definition
Author: Alan Carvalho de Assis <acassis@gmail.com>
Pizero GPIO registers
* Initial commit to add GPIO definitions
* Add remaining GPIO registers definition
Alan Carvalho de Assis <acassis@gmail.com>
BCM2708 memory map: Add VBASE defintions; fix VCSDRAM address per Alan; move all virtual address to the bottom of the file to avoid confusion -- top is all physical address; bottom is all veritural address.
Add initial memory map to BCM2708/BCM2835
Alan Carvalho de Assis <acassis@gmail.com>
Stm32, stm32l4 serial patches
* stm32: serial: add interface to get uart_dev_t by USART number, stm32_serial_get_uart
* stm32: serial: do not stop processing input in SW flow-control mode
* stm32l4: serial: do not stop processing input in SW flow-control mode
* stm32l4: serial: suspend serial for Stop mode
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
Change all calls to usleep() in the OS proper to calls to nxsig_usleep()
sched/signal: Add a new OS internal function nxsig_usleep() that is functionally equivalent to usleep() but does not cause a cancellaption point and does not modify the errno variable.
sched/signal: Add a new OS internal function nxsig_sleep() that is functionally equivalent to sleep() but does not cause a cancellaption point.
This commit backs out most of commit b4747286b1. That change was added because sem_wait() would sometimes cause cancellation points inappropriated. But with these recent changes, nxsem_wait() is used instead and it is not a cancellation point.
In the OS, all calls to sem_wait() changed to nxsem_wait(). nxsem_wait() does not return errors via errno so each place where nxsem_wait() is now called must not examine the errno variable.
In all OS functions (not libraries), change sem_wait() to nxsem_wait(). This will prevent the OS from creating bogus cancellation points and from modifying the per-task errno variable.
sched/semaphore: Add the function nxsem_wait(). This is a new internal OS interface. It is functionally equivalent to sem_wait() except that (1) it is not a cancellation point, and (2) it does not set the per-thread errno value on return.
sched/semaphore: Add nxsem_post() which is identical to sem_post() except that it never modifies the errno variable. Changed all references to sem_post in the OS to nxsem_post().
sched/semaphore: Add nxsem_destroy() which is identical to sem_destroy() except that it never modifies the errno variable. Changed all references to sem_destroy() in the OS to nxsem_destroy().
libc/semaphore and sched/semaphore: Add nxsem_getprotocol() and nxsem_setprotocola which are identical to sem_getprotocol() and set_setprotocol() except that they never modifies the errno variable. Changed all references to sem_setprotocol in the OS to nxsem_setprotocol(). sem_getprotocol() was not used in the OS
libc/semaphore: Add nxsem_getvalue() which is identical to sem_getvalue() except that it never modifies the errno variable. Changed all references to sem_getvalue in the OS to nxsem_getvalue().
sched/semaphore: Rename all internal private functions from sem_xyz to nxsem_xyz. The sem_ prefix is (will be) reserved only for the application semaphore interfaces.
libc/semaphore: Add nxsem_init() which is identical to sem_init() except that it never modifies the errno variable. Changed all references to sem_init in the OS to nxsem_init().
sched/semaphore: Rename sem_tickwait() to nxsem_tickwait() so that it is clear this is an internal OS function.
sched/semaphoate: Rename sem_reset() to nxsem_reset() so that it is clear this is an internal OS function.
STM32L4 RTC, PM: small fixes to subseconds handling, ADC power-management hooks
* STM32L4 ADC: add PM hooks from Motorola MDK
* STM32L4 RTC: add up_rtc_getdatetime_with_subseconds
* STM32 RTC: workaround for potential subseconds race condition
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
However many old chips have in their errata this silicon bug (at least F401xB/C,
F42xx, F43xx, L15xxE, L15xVD and likely others):
"When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after reading the RTC_SSR register. This happens
if the read operation is initiated one APB clock period before the shadow
registers are updated. This can result in a non-consistency of the three
registers. Similarly, RTC_DR register can be updated after reading the RTC_TR
register instead of being locked."
* STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
Change the register read ordering to match this and don't keep a workaround
for a hypothetical race condition (not in any L4 errata, lets for once assume
ST's silicon works as it is documented...)
* STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32, STM32 F7: LTDC and DMA2D drivers are not permitted to set the errno.
SIM LPC31xx: Serial and console drivers are not permitted to set the errno.
SAMv7, STM32, STM32 L4: DAC and ADC drivers are not permitted to set the errno.
STM32L4 FLASH, DFSDM: option bytes, JEXTSEL bits, ADC1 output to DFSDM chips change
* STM32L4 FLASH: add function for modifying device option bytes
* STM32L4 DFSDM: add JEXTSEL bits, ADC1 output to DFSDM chips change
ST's documentation hints that ADC output can be routed to DFSDM
on some STM32L4X3 chips, but I got confirmation from tech support
that this is just a documentation error so remove this from Kconfig.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32:stm32f40xxx I2C ensure proper isr handling
Injecting data errors that causes a STOP to be perceived by the
driver, will continually re-enter the isr with SB not set and BTF
and RxNE set. This changes allows the interrupts to
be cleared and propagates a I2C_SR1_TIMEOUT to the waiting task.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L4 DFSDM: add peripheral, DAC, TIM: small changes
* STM32L4 DAC: do not configure output pin if it is not used
* STM32L4 TIM: fix compilation of timers with complementary outputs when not PWM_MULTICHAN
* STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs
Initial version. Timer trigger support is not completed and there is
some issue with DMA.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
STM32L4: ADC, Kconfig small changes
* STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK
* STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates
Approved-by: Gregory Nutt <gnutt@nuttx.org>
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.
Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Actually write something to the DAC DMA buffer.
Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
On a very memory constrained device with a single task. The
sem_wait and sem_post operations can be disabled, to save space.
The default is blocking enabled.
In the where CONFIG_SDIO_PREFLIGHT is not used and
dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
boundaries.
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
