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17464 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
984e0f0ec9 xtensa/esp32: Add missing option for I2C reset 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
79ea96a1d0 xtensa/esp32: Fix ESP32_I2C option bringing the char driver 2021-03-04 16:31:51 +00:00
David Sidrane
8b73e30185 arch/arm/src/stm32h7/Kconfig 
stm32h7:lse fix Kconfig help text
 2021-03-04 07:10:18 -08:00
David Sidrane
296d94b5cb stm32f7:lse Use Kconfig values directly 2021-03-04 00:16:10 -08:00
ligd
d009074ed5 sim/up_uart.c: fix losting uart data when user paste long cmd 
N/A

Change-Id: I66c01c0789fc83ae8f6db522d61ff8ab63cd9211
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 19:05:22 -08:00
Fotis Panagiotopoulos
f423403dfa stm32_wwdg debug log formatting 2021-03-03 19:02:04 -08:00
Gustavo Henrique Nihei
5e9e2bec32 xtensa/esp32: Change I2C SCL default pin to a valid one 
Current default pin for I2C SCL is not available for mapping with IOMUX
peripheral.
 2021-03-03 19:00:15 -08:00
Nathan Hartman
3ac61053ce arch/stm32, arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32/hardware/stm32_dma2d.h,
arch/arm/src/stm32/hardware/stm32_ltdc.h,
arch/arm/src/stm32/stm32_dma2d.c,
arch/arm/src/stm32/stm32_ltdc.c,
arch/arm/src/stm32f7/hardware/stm32_dma2d.h,
arch/arm/src/stm32f7/hardware/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_dma2d.c, and
arch/arm/src/stm32f7/stm32_ltdc.c:

    * Fix nxstyle "mixed case identifier" errors for the
      following identifiers:

      DMA2D_xGPFCCR_ALPHA         -> DMA2D_XGPFCCR_ALPHA
      DMA2D_xGPFCCR_AM            -> DMA2D_XGPFCCR_AM
      DMA2D_xGPFCCR_CCM           -> DMA2D_XGPFCCR_CCM
      DMA2D_xGPFCCR_CM            -> DMA2D_XGPFCCR_CM
      DMA2D_xGPFCCR_CS            -> DMA2D_XGPFCCR_CS
      DMA2D_xGPFCCR_START         -> DMA2D_XGPFCCR_START
      LTDC_LxBFCR_BF1             -> LTDC_LXBFCR_BF1
      LTDC_LxBFCR_BF2             -> LTDC_LXBFCR_BF2
      LTDC_LxCFBLR_CFBLL          -> LTDC_LXCFBLR_CFBLL
      LTDC_LxCFBLR_CFBP           -> LTDC_LXCFBLR_CFBP
      LTDC_LxCR_CLUTEN            -> LTDC_LXCR_CLUTEN
      LTDC_LxCR_COLKEN            -> LTDC_LXCR_COLKEN
      LTDC_LxCR_LEN               -> LTDC_LXCR_LEN
      LTDC_LxWHPCR_WHSPPOS        -> LTDC_LXWHPCR_WHSPPOS
      LTDC_LxWHPCR_WHSTPOS        -> LTDC_LXWHPCR_WHSTPOS
      LTDC_LxWVPCR_WVSPPOS        -> LTDC_LXWVPCR_WVSPPOS
      LTDC_LxWVPCR_WVSTPOS        -> LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_LxWHPCR_WHSTPOS  -> STM32_LTDC_LXWHPCR_WHSTPOS
      STM32_LTDC_LxWVPCR_WVSTPOS  -> STM32_LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_Lx_BYPP          -> STM32_LTDC_LX_BYPP
      DMA2D_xGCOLR_BLUE           -> DMA2D_XGCOLR_BLUE
      DMA2D_xGCOLR_BLUE_MASK      -> DMA2D_XGCOLR_BLUE_MASK
      DMA2D_xGCOLR_BLUE_SHIFT     -> DMA2D_XGCOLR_BLUE_SHIFT
      DMA2D_xGCOLR_GREEN          -> DMA2D_XGCOLR_GREEN
      DMA2D_xGCOLR_GREEN_MASK     -> DMA2D_XGCOLR_GREEN_MASK
      DMA2D_xGCOLR_GREEN_SHIFT    -> DMA2D_XGCOLR_GREEN_SHIFT
      DMA2D_xGCOLR_RED            -> DMA2D_XGCOLR_RED
      DMA2D_xGCOLR_RED_MASK       -> DMA2D_XGCOLR_RED_MASK
      DMA2D_xGCOLR_RED_SHIFT      -> DMA2D_XGCOLR_RED_SHIFT
      DMA2D_xGOR                  -> DMA2D_XGOR
      DMA2D_xGOR_MASK             -> DMA2D_XGOR_MASK
      DMA2D_xGOR_SHIFT            -> DMA2D_XGOR_SHIFT
      DMA2D_xGPFCCR_ALPHA_MASK    -> DMA2D_XGPFCCR_ALPHA_MASK
      DMA2D_xGPFCCR_ALPHA_SHIFT   -> DMA2D_XGPFCCR_ALPHA_SHIFT
      DMA2D_xGPFCCR_AM_MASK       -> DMA2D_XGPFCCR_AM_MASK
      DMA2D_xGPFCCR_AM_SHIFT      -> DMA2D_XGPFCCR_AM_SHIFT
      DMA2D_xGPFCCR_CM_MASK       -> DMA2D_XGPFCCR_CM_MASK
      DMA2D_xGPFCCR_CM_SHIFT      -> DMA2D_XGPFCCR_CM_SHIFT
      DMA2D_xGPFCCR_CS_MASK       -> DMA2D_XGPFCCR_CS_MASK
      DMA2D_xGPFCCR_CS_SHIFT      -> DMA2D_XGPFCCR_CS_SHIFT
      LTDC_LxBFCR_BF1_MASK        -> LTDC_LXBFCR_BF1_MASK
      LTDC_LxBFCR_BF1_SHIFT       -> LTDC_LXBFCR_BF1_SHIFT
      LTDC_LxBFCR_BF2_MASK        -> LTDC_LXBFCR_BF2_MASK
      LTDC_LxBFCR_BF2_SHIFT       -> LTDC_LXBFCR_BF2_SHIFT
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA_MASK     -> LTDC_LXCACR_CONSTA_MASK
      LTDC_LxCACR_CONSTA_SHIFT    -> LTDC_LXCACR_CONSTA_SHIFT
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN_MASK       -> LTDC_LXCFBLNR_LN_MASK
      LTDC_LxCFBLNR_LN_SHIFT      -> LTDC_LXCFBLNR_LN_SHIFT
      LTDC_LxCFBLR_CFBLL_MASK     -> LTDC_LXCFBLR_CFBLL_MASK
      LTDC_LxCFBLR_CFBLL_SHIFT    -> LTDC_LXCFBLR_CFBLL_SHIFT
      LTDC_LxCFBLR_CFBP_MASK      -> LTDC_LXCFBLR_CFBP_MASK
      LTDC_LxCFBLR_CFBP_SHIFT     -> LTDC_LXCFBLR_CFBP_SHIFT
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE_MASK     -> LTDC_LXCKCR_CKBLUE_MASK
      LTDC_LxCKCR_CKBLUE_SHIFT    -> LTDC_LXCKCR_CKBLUE_SHIFT
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN_MASK    -> LTDC_LXCKCR_CKGREEN_MASK
      LTDC_LxCKCR_CKGREEN_SHIFT   -> LTDC_LXCKCR_CKGREEN_SHIFT
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED_MASK      -> LTDC_LXCKCR_CKRED_MASK
      LTDC_LxCKCR_CKRED_SHIFT     -> LTDC_LXCKCR_CKRED_SHIFT
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE_MASK     -> LTDC_LXCLUTWR_BLUE_MASK
      LTDC_LxCLUTWR_BLUE_SHIFT    -> LTDC_LXCLUTWR_BLUE_SHIFT
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD_MASK  -> LTDC_LXCLUTWR_CLUTADD_MASK
      LTDC_LxCLUTWR_CLUTADD_SHIFT -> LTDC_LXCLUTWR_CLUTADD_SHIFT
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN_MASK    -> LTDC_LXCLUTWR_GREEN_MASK
      LTDC_LxCLUTWR_GREEN_SHIFT   -> LTDC_LXCLUTWR_GREEN_SHIFT
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED_MASK      -> LTDC_LXCLUTWR_RED_MASK
      LTDC_LxCLUTWR_RED_SHIFT     -> LTDC_LXCLUTWR_RED_SHIFT
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA_MASK    -> LTDC_LXDCCR_DCALPHA_MASK
      LTDC_LxDCCR_DCALPHA_SHIFT   -> LTDC_LXDCCR_DCALPHA_SHIFT
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE_MASK     -> LTDC_LXDCCR_DCBLUE_MASK
      LTDC_LxDCCR_DCBLUE_SHIFT    -> LTDC_LXDCCR_DCBLUE_SHIFT
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN_MASK    -> LTDC_LXDCCR_DCGREEN_MASK
      LTDC_LxDCCR_DCGREEN_SHIFT   -> LTDC_LXDCCR_DCGREEN_SHIFT
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED_MASK      -> LTDC_LXDCCR_DCRED_MASK
      LTDC_LxDCCR_DCRED_SHIFT     -> LTDC_LXDCCR_DCRED_SHIFT
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF_MASK         -> LTDC_LXPFCR_PF_MASK
      LTDC_LxPFCR_PF_SHIFT        -> LTDC_LXPFCR_PF_SHIFT
      LTDC_LxWHPCR_WHSPPOS_MASK   -> LTDC_LXWHPCR_WHSPPOS_MASK
      LTDC_LxWHPCR_WHSPPOS_SHIFT  -> LTDC_LXWHPCR_WHSPPOS_SHIFT
      LTDC_LxWHPCR_WHSTPOS_MASK   -> LTDC_LXWHPCR_WHSTPOS_MASK
      LTDC_LxWHPCR_WHSTPOS_SHIFT  -> LTDC_LXWHPCR_WHSTPOS_SHIFT
      LTDC_LxWVPCR_WVSPPOS_MASK   -> LTDC_LXWVPCR_WVSPPOS_MASK
      LTDC_LxWVPCR_WVSPPOS_SHIFT  -> LTDC_LXWVPCR_WVSPPOS_SHIFT
      LTDC_LxWVPCR_WVSTPOS_MASK   -> LTDC_LXWVPCR_WVSTPOS_MASK
      LTDC_LxWVPCR_WVSTPOS_SHIFT  -> LTDC_LXWVPCR_WVSTPOS_SHIFT

    * Fix all other nxstyle errors in the affected files.
 2021-03-03 18:49:20 -08:00
Gustavo Henrique Nihei
b1b4190802 risc-v/esp32c3: Fix default GPIO function when no option is provided 2021-03-03 18:46:43 -08:00
Gustavo Henrique Nihei
bc335009d9 risc-v/esp32c3: Allow pin to be configured as Input and Output simultaneously 2021-03-03 18:46:43 -08:00
Abdelatif Guettouche
85620c3c1a risc-v/esp32c3: Add more flash options to esptool. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-03 18:28:18 -08:00
Abdelatif Guettouche
77302f9d3a xtensa/esp32: Add more flash options to esptool. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-03 18:28:18 -08:00
Xiang Xiao
c8d4a4c76a mtd/progmem: Add up_progmem_read callback guarded by ARCH_HAVE_PROGMEM_READ 
since sometime platform code need do some special action during memcpy

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id108ef4232376feab3e37e9b3aee9a7927a03bd4
 2021-03-03 13:47:59 -08:00
ligd
f9d20ea4d2 sigdeliver: fix system block when kill signal to idle in SMP 
Bug description:

CONFIG_SMP=y

Suppose we have 2 cores in SMP, here is the ps return:

PID GROUP CPU PRI POLICY TYPE    NPX STATE     STACK   USED  FILLED COMMAND
  0     0   0   0 FIFO   Kthread N-- Assigned 004076 000748  18.3%  CPU0 IDLE
  1     0   1   0 FIFO   Kthread N-- Running  004096 000540  13.1%  CPU1 IDLE

nsh> kill -4 0
or:
nsh> kill -4 1

system blocked.

Reason:

In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.

Fix:

Add condition to cover saved_irqcount == 0.

Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 15:03:32 +00:00
Yuichi Nakamura
9d0b3594f6 arm/rp2040: Add RP2040 I2C device support 2021-03-03 09:35:45 -03:00
Yuichi Nakamura
60b18467f3 arm/rp2040: Add rp2040_gpio_set_pulls() 2021-03-03 09:35:45 -03:00
David Sidrane
ab5f46d46c stm32h7:Add DBGMCU 2021-03-02 18:28:19 -08:00
chenwen
19627095e4 esp32/esp32_allocateheap.c: Support the maximum available internal heap configuration 2021-03-02 18:27:20 -08:00
chenwen
516c553b97 esp32/esp32_wifi_adapter.c: Fix the issue of WiFi internal malloc from PSRAM 2021-03-02 18:27:20 -08:00
Nathan Hartman
a3f0923ad0 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_tim.h:

    * Fix nxstyle errors.
 2021-03-02 21:34:33 +00:00
David Sidrane
1e5754232a stm32f7:Add option to auto select LSE CAPABILITY 
This Knob will cycle through the values from
   low to high. To avoid damaging the crystal.
   We want to use the lowest setting that gets
   the OSC running. See app note AN2867
 2021-03-02 14:34:56 -03:00
David Sidrane
9fbd7f9dc5 stm32h7:Add option to auto select LSE CAPABILITY 
This Knob will cycle through the correct*
   values from low to high. To avoid damaging
   the crystal. We want to use the lowest setting
   that gets the OSC running. See app note AN2867

    *It will take into account the rev of the silicon
    and use the correct code points to achive the drive
    strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator
    driving capability selection bits are swapped.
 2021-03-02 14:34:56 -03:00
Michael Jung
fbfddda28b armv8-m: Fix EXC_RETURN for non-secure usage 
With TrustZone support in armv8-m the bit-fields in EXC_RETURN have been
extended.  Bit 6 ('S') now specifies whether the interrupted program was
running in the Non-Secure (S=0) or Secure (S=1) security state.
Furthermore, Bit 0 ('ES' - Exception Secure) specifies the
security state athe exception is taken to (0: Non-Secure, 1: Secure).

When NuttX is run together with TrustedFirmware-M as the application in
the non-secure world both the S and the ES bits have to be set to '0'.
For armv8-m those are also the correct values if TrustZone is not
implemented on the respective MCU or if it is disabled.

Signed-off-by: Michael Jung <mijung@gmx.net>
 2021-03-02 07:28:42 -03:00
YAMAMOTO Takashi
c230edea29 esp32_ummap: write back spiram cache before calling Cache_Flush 
This seems to fix esp32_readdata_encrypted() with spiram "buffer".

Note: I'm not sure if this is the right fix or not.
I couldn't find any documentation about Cache_Flush.
 2021-03-02 08:37:50 +00:00
Nathan Hartman
75eb3e8ec2 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_lowputc.c:

    * Fix nxstyle errors.
 2021-03-01 18:13:06 +00:00
Xiang Xiao
3d24288a66 arm/cxd56xx: Beautify the coding style in cxd56_gnss.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-03-01 10:00:13 -05:00
Xiang Xiao
9473434587 Ensure the kernel component don't call userspace API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-03-01 09:23:09 +09:00
Masayuki Ishikawa
ef1826e133 arch: armv6-m: Apply armv7-m signal handling logic 
Summary:
- This commit applies armv7-m signal handling logic

Impact:
- armv6-m signal handling

Testing:
- Tested with ostest with the following configs
- raspberrypi-pico:nsh, raspberrypi-pico:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-26 22:23:03 -06:00
Fotis Panagiotopoulos
40fdf388bd Fixed __stack_overflow_trap declaration typo. 2021-02-26 12:08:16 -08:00
Nathan Hartman
9d48beb2c8 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_pm.h,
arch/arm/src/stm32f7/stm32_pmsleep.c,
arch/arm/src/stm32f7/stm32_pmstandby.c,
arch/arm/src/stm32f7/stm32_pmstop.c,
arch/arm/src/stm32f7/stm32_pwm.h:

    * Fix nxstyle errors.
 2021-02-26 17:13:05 +00:00
Peter van der Perk
4842868be2 [FlexCAN] Fix TX drop #2792 and correctly set CAN timings to non-zeroed registers 2021-02-26 06:14:33 -08:00
Byron Ellacott
1105cf0669 ez80: fix several bugs in emac driver 
IRQs cannot be individually disabled on the eZ80, so using
`up_disable_irq()` had no effect. This left the IRQ handler being
constantly triggered without the lower half handler running.

The macro for EMAC stats was incompatible with Clang. The simplified
form gives identical results under ZDS-II.

The MII clock speed must be set before trying to read MII registers.
It's now done before resetting the PHY using the Mode Control Register.

MII initialization waited on the auto-neogotiate restart bit being set
but PHY hardware is frequently fast enough to have cleared the bit
before the first read of it. It now instead just waits on auto-negotiate
completing. The MII poll loop now uses `up_mdelay` because it was far
too fast at 50MHz using a busy loop, giving time for a link to be
established.

Bad packets are now processed enough to release their buffers back to
the EMAC hardware.

A few typos, unused variables, and other miscellaneous issues were also
fixed.
 2021-02-26 03:25:58 -06:00
Michal Lenc
04fc5e314d arch/arm/src/imxrt: updated flexcan driver to support classical and FD frames at once 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-02-25 22:31:04 -08:00
Abdelatif Guettouche
39016f6d68 risc-v/esp32c3: Configure clock and call board initialize at startup. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-25 22:13:26 -08:00
hotislandn
651b905b99 arch:rv64:add API up_copyfullstate for later FPU support. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-02-25 11:26:27 -08:00
Yuichi Nakamura
a556bbf3a4 arm/rp2040: Fix LDFLAGS for boot stage2 2021-02-25 11:25:27 -08:00
Gustavo Henrique Nihei
7fe096c65e risc-v: Fix typos reported by codespell 2021-02-25 16:25:47 +00:00
Gustavo Henrique Nihei
ed0a1b724b xtensa/esp32: Fix typos reported by codespell 2021-02-25 15:02:15 +00:00
hotislandn
30cb7d3983 arch:rv32:up_sigdeliver missing fpu contexts. 
Signed-off-by: hotislandn <hotislandn@hotmail.com>
 2021-02-24 23:42:18 -08:00
Masayuki Ishikawa
8085010ae8 arch: arm: Add 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040 
Summary:
- This commit adds 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040
- Now NuttX spinlock uses WFE/SEV to reduce power consumption
- Also, modify a comment on rp2040

Impact:
- rp2040 only

Testing:
- Tested with raspberrypi-pico:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-24 19:12:22 -08:00
Nathan Hartman
7c5174a53b arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_config.h,
arch/arm/src/stm32f7/stm32_dma.h,
arch/arm/src/stm32f7/stm32_dma2d.h,
arch/arm/src/stm32f7/stm32_dtcm.h,
arch/arm/src/stm32f7/stm32_dumpgpio.c,
arch/arm/src/stm32f7/stm32_ethernet.h,
arch/arm/src/stm32f7/stm32_gpio.c,
arch/arm/src/stm32f7/stm32_gpio.h:

    * Fix nxstyle errors.
 2021-02-24 22:39:49 +00:00
Yuichi Nakamura
01699e00e0 arm/rp2040: Raspberry Pi Pico SMP support 2021-02-25 07:20:59 +09:00
Gustavo Henrique Nihei
6edeb9ebd9 risc-v/esp32c3: Free CPU interrupt if irq_attach fails 2021-02-24 15:56:26 +00:00
Gustavo Henrique Nihei
5c24c98880 risc-v/esp32c3: Invalidate CPU interrupt number after free 2021-02-24 15:56:26 +00:00
YAMAMOTO Takashi
ee8cea1f4b esp32: xtensa_user: Implement a few more instructions 
You can find them used in the ROM version of memcpy.
While it might be controversial if it's a good idea to use the ROM version
of these functions, it's nicer to support more instructions here anyway.
 2021-02-24 10:34:55 +00:00
Abdelatif Guettouche
fb68a4b777 esp32c3: Add system reset. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-23 18:13:02 -08:00
Gustavo Henrique Nihei
48ff647fe9 risc-v/esp32c3: Fix erroneous references to ESP32-C3 2021-02-23 18:12:16 -08:00
David Sidrane
62321fa5db s32k1xx:Support ramfunc 2021-02-23 18:11:41 -08:00
Nathan Hartman
c90fffcc09 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_pwr.c,
arch/arm/src/stm32f7/stm32_pwr.h,
arch/arm/src/stm32f7/stm32_usbhost.h:

    * Fix nxstyle errors.
 2021-02-22 18:18:58 -08:00
Gustavo Henrique Nihei
af8e71d9e9 risc-v/esp32c3: Fix inconsistent guard comment 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
628e2288aa risc-v/esp32c3: Add missing header guard for lowputc 2021-02-22 09:24:14 -08:00
Gustavo Henrique Nihei
ca30c1db69 risc-v/esp32c3: Build serial driver only when selected 2021-02-22 09:24:14 -08:00
Abdelatif Guettouche
491a4c1ed2 risc-v/esp32c3: Don't reserve any vectors for any special use. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-22 09:21:24 -08:00
Gustavo Henrique Nihei
291a5755cc risc-v/esp32c3: Add support for MWDT0 and MWDT1 2021-02-22 17:18:01 +00:00
Yuichi Nakamura
7b8c72ec1b boards: raspberrypi-pico: Add nshsram defconfig for SRAM build 2021-02-22 09:11:09 -08:00
Brennan Ashton
f23f2a8557 Fix context switch bug for pic32mx 2021-02-21 22:24:12 -08:00
Masayuki Ishikawa
cf72133d3c rp2040: Continue to build even if PICO_SDK_PATH is not set 
Summary:
- In the previous implementation, the build system stops if
  PICO_SDK_PATH is not set.
- However, this behavior is not good for CI. Because the path
  is only used to generate a flash image.
- This commit fixes this issue

Impact:
- rp2040 only

Testing:
- Tested with and without PICO_SDK_PATH
 2021-02-21 20:30:58 -08:00
Brennan Ashton
7a9e9b770f pic32mz does not have ANSELJ register on port K 2021-02-21 18:27:56 -08:00
Alexander Vasiljev
8bb50b578b arch/stm32h7: add definitions for DAC 2021-02-21 07:39:05 -08:00
Abdelatif Guettouche
067da56d0c esp32c3: Some cosmetics and style fixes. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-21 10:29:43 -03:00
Abdelatif Guettouche
10822799fb esp32c3: Add GPIO IRQ support. 
The GPIO example was also extended to include testing an interrupt pin.

Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
 2021-02-21 10:29:43 -03:00
Alan Carvalho
4a42998f36 esp32-c3: Add the GPIO driver. 
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix.  It
also includes necessary board logic to run the GPIO example with 2
outputs.

Co-authored-by: Alan Carvalho <alan.carvalho@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-21 10:29:43 -03:00
Yuichi Nakamura
96a473d39d arch/arm: Add support for boot stage2 from Raspberry Pi Pico SDK 2021-02-20 03:45:24 -08:00
Yuichi Nakamura
ed1da60f52 arch/arm: Add RP2040 (Raspberry Pi Pico's SoC) support 2021-02-20 03:45:24 -08:00
Yuichi Nakamura
d0002b24c7 arm: ARMv6-M vector table offset register support 2021-02-19 19:24:09 -08:00
Byron Ellacott
9a1b726bae fs: change geometry types from size_t to blkcnt_t and blksize_t 
This change reflects that the geometry isn't related to the largest
allocatable unit on the platform.

Calls to read and write block devices are also affected and have
been updated.
 2021-02-18 20:38:22 -08:00
Masayuki Ishikawa
e87d14721e arch: xtensa: Fix stack coloring 
Summary:
- Call up_stack_color() correctly in the up_create_stack()
- Fix nwords calculation in up_stack_color()
- Also, refactor up_stack_color()
- Fix do_stackcheck() to consider stack alignment

Impact:
- Only for CONFIG_STACK_COLORATION=y

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-18 19:05:07 -08:00
Gustavo Henrique Nihei
7750de72bb stdint.h: Use conversion macros for the definition of MIN and MAX constants 2021-02-18 18:35:35 -08:00
Gustavo Henrique Nihei
9fcca55ad6 z80/inttypes.h: Add INT24_C and UINT24_C function macros 2021-02-18 18:35:35 -08:00
Augusto Fraga Giachero
43a98662f3 lpc17xx_40xx/lpc17_40_i2c.c: Propagate I2C I/O errors 
Check if all messages were transferred, if not, return -ENXIO.

This is particularly useful when the slave returns an unexpected NAK,
the application code should catch the error to avoid failing silently.
 2021-02-18 18:33:05 -08:00
Abdelatif Guettouche
4c3412faaa risc-v/esp32c3: Add clock configuration 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-18 01:21:53 -08:00
Sara Souza
998f7e5d4c risc-v/esp32c3: Add basic UART support for console 2021-02-18 01:21:53 -08:00
Dong Heng
b11a5ca8b2 risc-v/esp32c3: Add ESP32-C3 basic support 
Co-authored-by: Dong Heng <dongheng@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-18 01:21:53 -08:00
Masayuki Ishikawa
3ddfab239f arch: xtensa: Fix a compile warning in xtensa_dumpstate.c 
Summary:
- This commit fixes a compile warning if CONFIG_ARCH_INTERRUPTSTACK is set

Impact:
- None

Testing:
- Built with esp32-devkitc:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-18 09:11:27 +00:00
Byron Ellacott
458e021c86 eZ80: remove private function prototype from header 2021-02-17 02:32:12 -08:00
Byron Ellacott
bf7bd51a62 eZ80: fix typos in emac driver 2021-02-17 02:32:12 -08:00
Byron Ellacott
256c5c266a eZ80: fix name of SP register in stack frame 2021-02-17 02:32:12 -08:00
Byron Ellacott
e50b5bef8b eZ80: ensure DECL_SAVESTATE() is done when needed 2021-02-17 02:32:12 -08:00
Byron Ellacott
f0ccce3212 eZ80: include inttypes from inttypes 2021-02-17 02:32:12 -08:00
Byron Ellacott
ed83ee2675 eZ80: update register offsets 2021-02-17 02:32:12 -08:00
Masayuki Ishikawa
102adaf026 arch: esp32: Fix a memory leak when discarding a large packet. 
Summary:
- Recently I noticed that ESP32-DevKitC-32D suddenly stops
  during receiving ping packets from PC after 10-20mins
- Actually, sometimes memory leak happened when some device
  sent a big broadcast packet periodically on the network
- This commit fixes this issue by calling esp_wifi_free_eb()
  in the case that the packet exceeds WLAN_BUF_SIZE.
- Also, this commit applies the same logic in the case that
  the Wi-Fi interface is down

Impact:
- None

Testing:
- Tested with esp32-devkitc:wapi

Suggested-by: YAMAMOTO Takashi <yamamoto@midokura.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-17 12:55:08 +09:00
Brennan Ashton
9f1017feb3 board/freedom-k64f: Add usbdev support with cdcacm example 2021-02-14 19:51:34 -08:00
David Jablonski
41bddc8461 litex: fix mtime and mtimecmp register address 2021-02-13 15:24:28 -08:00
David Jablonski
11167857c3 litex: nsh working 2021-02-13 15:24:28 -08:00
jpeng
af42079cc7 fix spi bug 2021-02-13 10:31:25 -08:00
liang
5914af84c7 arch/risc-v/bl602: spi_master support. 2021-02-13 10:31:25 -08:00
Nathan Hartman
01248cae8d arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_qencoder.c,
arch/arm/src/stm32f7/stm32_rng.c,
arch/arm/src/stm32f7/stm32_rtc.c,
arch/arm/src/stm32f7/stm32_rtc.h,
arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c,
arch/arm/src/stm32f7/stm32_sai.h,
arch/arm/src/stm32f7/stm32_sdmmc.h,
arch/arm/src/stm32f7/stm32_spi.h,
arch/arm/src/stm32f7/stm32_tim_lowerhalf.c,
arch/arm/src/stm32f7/stm32_uid.c,
arch/arm/src/stm32f7/stm32_userspace.c,
arch/arm/src/stm32f7/stm32_userspace.h,
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c,
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c:

    * Fix nxstyle errors.
 2021-02-12 10:27:13 -08:00
YAMAMOTO Takashi
aed24f1255 esp32: Retire XTENSA_IMEM_PROCFS 
Now /proc/meminfo has the equivalent.
 2021-02-12 03:16:03 -08:00
YAMAMOTO Takashi
7bb849535c esp32_modtext.c: Report the usage with procfs_register_meminfo 2021-02-12 03:16:03 -08:00
YAMAMOTO Takashi
c51e2a0cb3 esp32_imm.c: Report the usage with procfs_register_meminfo 2021-02-12 03:16:03 -08:00
Alan C. Assis
f56ff40101 Add esp32_gpio_matrix_in/out to replace ROM functions 2021-02-11 20:39:51 +00:00
Masayuki Ishikawa
c024b414f8 arch: cxd56xx: Introduce driver-specific spinlock in cxd56_serial.c 
Summary:
- This commit introduces driver-specific spinlock in cxd56_serial.c
  to improve performance

Impact:
- SMP only

Testing:
- Tested with spresense:wifi and spresense:wifi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-09 11:29:18 -08:00
chenwen
dcec04f5b2 xtensa/esp32: Writeback PSRAM data when mapping SPI Flash address to ESP32's address bus 2021-02-09 08:26:45 -03:00
YAMAMOTO Takashi
2220827463 esp32_allocateheap.c: Add a sanity check 2021-02-09 07:51:12 +00:00
YAMAMOTO Takashi
63c08a79be esp32_allocateheap.c: Add a comment 2021-02-09 07:51:12 +00:00
Gustavo Henrique Nihei
a8cf8abfaa esp32: Create chip selection config to improve capabilities refinement 2021-02-08 21:17:22 +00:00
hotislandn
84daebf2cc arch:risc-v:bl602: enable FPU for this target. 2021-02-08 00:29:34 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs. 
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-07 21:28:56 -08:00
Abdelatif Guettouche
6547c3df55 arch/riscv: Fix file names in headers that were still using the old 'up_' prefix. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-05 21:19:20 -03:00
Gustavo Henrique Nihei
29b9cf652e xtensa/esp32: Add extern modifier to ROM function declaration 2021-02-05 14:05:44 -03:00
Abdelatif Guettouche
685c2ce506 esp32_spiflash.c: Fix preprocessor condition. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-05 12:16:55 -03:00
Masayuki Ishikawa
96d4bc11c0 arch: s32k1xx: Fix style warnings in s32k1xx_edma.c 
Summary:
- This commit fixes style warnings in s32k1xx_edma.c

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-04 21:49:16 -08:00
Masayuki Ishikawa
9f414cf6db arch: max32660: Fix style warnings and compile errors 
Summary:
- This commit fixes style warnings under max32660
- Also fix compile errors in max32660_gpio.c with CONFIG_DEBUG_GPIO_INFO=y

Impact:
- None

Testing:
- Built with max32660-evsys:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-04 21:49:16 -08:00
Masayuki Ishikawa
dabd835bb7 arch: imxrt: Fix style warnings in imxrt_edma.[c,h] 
Summary:
- This commit fixes style warnings in imxrt_edna.[c,y]

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-04 21:49:16 -08:00
Alan C. Assis
c4f87977dc xtensa/esp32: Fix cache issue detected by DEBUG_ASSERTION 2021-02-04 21:22:01 +00:00
Masayuki Ishikawa
12a515ebb6 arch: imxrt: Introduce CONFIG_NET_GUARDSIZE to imxrt_enet.c 
Summary:
- In the previous imxrt_enet.c, imxrt_enet.c assumed that
  CONFIG_NET_ETH_PKTSIZE includes the ethernet CRC (4bytes)
- However, most of the driver implementation explicitly
  add CONFIG_NET_GUARDSIZE for the CRC to the internal buffer
- This commit conforms to such rules

Imapct:
- No impact

Testing:
- Tested with iperf with imxrt1060-evk
- NOTE: need to add the following configs
  +CONFIG_EXAMPLES_IPERF=y
  +CONFIG_EXAMPLES_IPERFTEST_DEVNAME="eth0"
  +CONFIG_IOB_NBUFFERS=128
  +CONFIG_NET_ETH_PKTSIZE=1514
  +CONFIG_NET_GUARDSIZE=4
  +CONFIG_RR_INTERVAL=200

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-02-04 00:29:07 -08:00
Huang Qi
aabb870d6b stm32f7/stm32_qspi.c: Fix warning of format strings 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-02-03 08:49:46 +00:00
David Sidrane
18ce105e8b stm32f412:Corrected Pin count 
Port C was not working because the GPIO pin count was
   wrong. The 48 pin packages has 34 GPIO (Not counting PH0 & PH1)
   It is GPIOA GPIO B (sans PB11) and GPIOC PC13-PC15
 2021-02-02 18:41:39 -08:00
Matias N
45b392be7e nRF52: add support for building SoftDevice BLE controller 2021-02-02 14:40:26 -08:00
Matias N
74e7e2b5b2 nRF52 tickless RTC: fix timer not firing on edge case 
The calls via RTC API weren't fast enough for the edge case
of minimum counter value, resulting in the timer never
expiring as the counter had already passed the compare value.
This now uses direct register access functions and also
gets the latest counter value in edge case.
 2021-02-02 14:37:22 -08:00
Matias N
27ac9a6948 nRF52 SPI: fix for RX transfers when !SPI_EXCHANGE 2021-02-02 14:37:22 -08:00
Matias N
e9a45ea183 nRF52 SPI: use PPI API instead of direct register access 2021-02-02 14:37:22 -08:00
Peter van der Perk
22437698f1 [imxrt] Fix FlexCAN tx dropping frames 2021-02-02 17:51:29 -03:00
Abdelatif Guettouche
5447f28742 riscv: Remove the nx_start prototype from riscv_internal.h 
This function is already declared in include/nuttx/init.h include this
file instead.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-02 17:48:40 -03:00
Abdelatif Guettouche
db2a8f0dc5 arch/risc-v: Remove incorrect ARM references. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-02 17:48:06 -03:00
Abdelatif Guettouche
37b93bd498 arch/risc-v: Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1. 
Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1, so we won't
have to provide a dummy stub for every chip.
Also rename the function from up_addregion to riscv_addregion since it's
not exported outside the arch directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-02-01 18:45:25 -08:00
Pavel Pisa
56be7c54ea arch/arm/src/samv7/sam_mcan.c: fix some mismatches caused by renaming. 
The MCAN driver private structure has been renamed to struct sam_mcan_s,
but some functions reference sam_can_s. There are missing defines
of return variable in some functions.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
 2021-02-01 18:28:35 -08:00
Nathan Hartman
d82cc3ccc6 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/chip.h,
arch/arm/src/stm32f7/stm32_adc.h,
arch/arm/src/stm32f7/stm32_allocateheap.c,
arch/arm/src/stm32f7/stm32_bbsram.h,
arch/arm/src/stm32f7/stm32_can.h,
arch/arm/src/stm32f7/stm32_capture.c,
arch/arm/src/stm32f7/stm32_capture.h:

    * Fix nxstyle errors.
 2021-01-31 19:55:34 +00:00
Alan C. Assis
b0d611d3dc Replace ARM_LWL_CONSOLE with generic LWL_CONSOLE 2021-01-31 06:14:50 -08:00
Abdelatif Guettouche
52b4c73a61 arch/riscv: Remove references to MIPS. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-30 15:46:38 -08:00
Xiang Xiao
418a87af4c arch/sim: Fix typo error(HCITTY->BTUART) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-30 15:43:03 -08:00
Masayuki Ishikawa
5bcdeb0851 arch: imx6: Fix a compile error with CONFIG_DEBUG_ASSERTIONS=y 
Summary:
- This commit fixes a compile error in imx_enet.c
  with CONFIG_DEBUG_ASSERTIONS=y

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-29 12:09:47 -03:00
Masayuki Ishikawa
585884fde9 arch: imx6: Add CONFIG_IMX_ENET_NTXBUFFERS check in imx_enet.c 
Summary:
- This commit checks CONFIG_IMX_ENET_NTXBUFFERS without
  CONFIG_NET_TCP_WRITE_BUFFERS

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-29 00:05:01 -08:00
Masayuki Ishikawa
6140969f16 arch: imx6: Fix imx_enet.c if CONFIG_IMX_ENET_NTXBUFFERS=1 
Summary:
- This commit fixes imx_enet.c if CONFIG_IMX_ENET_NTXBUFFERS=1
- Also adds some ninfo() debug messages

Impact:
- imx_enet.c only

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-28 18:41:34 -08:00
Alan C. Assis
bf384a7e33 esp32/psram: Fix missing configs 2021-01-28 05:14:36 -08:00
Masayuki Ishikawa
977367ce04 arch: imx6: Apply the latest imxrt/imxrt_enet.c to imx6/imx_enet.c 
Summary:
- Since imx_enet.c is based on imxrt_enet.c and still under debugging,
  the differences should be minimum to keep tracking the changes

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-27 22:58:29 -08:00
Abdelatif Guettouche
0f2b774dec arch/risc-v: Remove unused and undefined file section "Public Variables" 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-27 18:40:10 -08:00
Abdelatif Guettouche
82aae4deb6 esp32/esp32_wifi_adapter.c: Print debug output only when DEBUG_WIRLESS* 
are enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-28 07:51:31 +09:00
Abdelatif Guettouche
6bc070024d arch/xtensa/Kconfig: Reduce the default value of the internal memory. 
The static memory is now divided at almost the middle to not override
the ROM data.  The old 0x28000 will take all of what's left for heap
region1.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-27 09:49:58 -08:00
Matias N
e5200d4af9 nrf52: add stackcheck support 2021-01-27 09:49:16 -08:00
Masayuki Ishikawa
b9d4bd0854 arch: esp32: Fix compile errors with CONFIG_SMP=y 
Summary:
- This commit fixes compile errors in esp32_spiflash.c and
  esp32_wifi_adapter.c with CONFIG_SMP=y

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi
- NOTE: the following configs need to be added.
  +CONFIG_SMP=y
  +CONFIG_SMP_IDLETHREAD_STACKSIZE=3072
  +CONFIG_SMP_NCPUS=2
  +CONFIG_SPINLOCK_IRQ=y

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-27 04:47:05 -08:00
Alan C. Assis
6a87b85285 xtensa/esp32: Add efuse driver 2021-01-26 18:23:43 -08:00
Abdelatif Guettouche
6bf826acca arch/xtensa/src/esp32/esp32_spiflash.c: Fix the value of the page start 
address.
It was incorrectly taken from the size.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-26 15:27:16 -03:00
baggio63446333
7723ce46ce arch: cxd56xx: Add I2C bitbang lower driver 
Add I2C bitbang lower driver for cxd56xx.
 2021-01-26 13:59:30 -03:00
Xiang Xiao
39f96361a3 arch/sim: Rename bthcitty driver to btuart driver 
align with other soc naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-25 08:23:23 -08:00
Xiang Xiao
503780497a board/sim: Support NuttX BLE stack through uart shim driver 
and add new btuart config to test it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-24 19:04:37 -08:00
Matias N
d2f9544556 nRF52 GPIO: tiny optimization, do not decode PORT when no PORT1 2021-01-24 19:03:56 -08:00
Matias N
28caf27229 nRF52: add I2C bitbang implementation 2021-01-24 19:03:56 -08:00
Alin Jerpelea
56ef94086f arch: arm: cxd56xx: update license to Apache 2.0 
This is a license change to Apache 2.0 license.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-01-25 09:09:30 +09:00
Xiang Xiao
7f2317e90a Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-22 08:34:07 +01:00
Xiang Xiao
94da3e4c3a arch: Remove critical section inside up_schedule_sigaction 
since nxsig_tcbdispatch already hold it for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I2fe6ad840bdca3ec0eaa76a9af3b6929c7d5a721
 2021-01-22 08:34:07 +01:00
Alan C. Assis
394cfba1d8 Fix himem debug assert error 2021-01-22 00:00:04 +01:00
Dong Heng
4bbc17454c xtensa/esp32: Add AES hardware accelerator driver 2021-01-21 15:06:35 -03:00
David Sidrane
a2f82542ef stm32f412:Replaced Kludged pinmap with one for SoC. 
The stm32f412 was not a clean port. This is one step to fix
   it. The shortcuts taken has caused more wasted hours finding
   bad pin mappings then doing the job correctlry to begin with.

   stm32:Kconfig Add CAN2 on STM32F412
 2021-01-21 06:56:33 -08:00
Abdelatif Guettouche
c87e5965b7 xtensa/esp_allocateheap.c: Correct ROM memory boundries. 
SMP was broken because the ROM memory wasn't set correctly.  Some
regions were shared with the ROM code.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-21 11:13:19 -03:00
YAMAMOTO Takashi
a4a2d5ff7d esp32_dma_init: Fix a dubious assertion 
Requiring the size to be a multiple of 3 is a very strange restriction.
It doesn't even work with the default value of SPI_SLAVE_BUFSIZE.
I guess it was a typo.
 2021-01-21 10:51:46 +01:00
YAMAMOTO Takashi
8c02b366f8 esp32_free_cpuint: Fix an assertion 
The original assertion was wrong because:

* cpuint numbers for edge interrupts are not dense
  (while ESP32_CPUINT_NEDGEPERIPHS is 4, EPS32_CPUINT_EDGESET is not 0xf.)

* This function is used for level interrupts too
 2021-01-21 10:37:03 +01:00
Matias N
ed5e494298 nRF52: FIX wrong bitmask for DRIVE setting 
This bug made certain values of DRIVE setting
to be wrongly applied (which can be dangerous
under certain situations since for example H0D1
was mapped to H0H1).
 2021-01-21 00:36:56 -08:00
Jiuzhu Dong
f6cfd1c87b vfork: support sim vfork 
N/A

Change-Id: I15920bcbacfc5ea519cfe12c39cb64dfe6365838
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-01-20 08:39:17 -08:00
chao.an
a32856f965 sim/hcitty: remove the poll lock to avoid invalid wait 
it it unnecessary to protect pollnotify() since the wakeup
source comes from idle thread

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-01-19 03:38:15 -08:00
Matias N
5fc34a6e8c nRF52: support stack coloration 2021-01-18 17:29:36 -03:00
Nathan Hartman
3620728db2 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_dtcm.c:
arch/arm/src/stm32h7/stm32_lowputc.c:

    * Fix nxstyle issues.
 2021-01-18 17:28:05 -03:00
Xiang Xiao
34a300b647 arch/sim: Fix up_hcitty.c:366:20: warning: ‘eventset’ may be used uninitialized 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-18 11:20:06 -03:00
Xiang Xiao
aa37399c89 arch/sim: Extend hcitty_register to accept device name 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-18 11:20:06 -03:00
Xiang Xiao
8c8c30b9d7 arch/sim: Rename g_hcitty_ops to g_bthcitty_ops 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-18 11:20:06 -03:00
Xiang Xiao
db0b661f37 arch/sim: Don't potect recvsem in bthcitty_pollnotify 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-18 11:20:06 -03:00
Dong Heng
eb2937003b xtensa/esp32: Fix ESP32 SPI driver issues 
1. reset SPI hardware when deinitializing
2. reset SPI priavte configuration data when deinitializing
3. free interrupt when deinitializing
 2021-01-18 12:54:12 +01:00
Brennan Ashton
b6fbcb649c nrf52: Add a static copy buffer for i2c 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2021-01-18 00:45:59 -08:00
Dong Heng
4693857b2c xtensa/esp32: Fix ESP32 I2C driver issues 
1. when sending a message in a group fails, exit immediately
2. when catch I2C error interrupt, close interrupt
3. clear clock configuration when deinit I2C
4. free I2C interrupt when deinit I2C
 2021-01-18 09:23:47 +01:00
Brennan Ashton
3a64783273 nrf52: Add simple i2c test configuration 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2021-01-17 23:46:01 -08:00
raiden00pl
0f1c026a16 nrf52_i2c: add support for I2C_M_NOSTART flags 2021-01-17 13:39:28 -08:00
Nathan Hartman
df8139c59b arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_rtc.c:
arch/arm/src/stm32h7/stm32_rtc.h:

    * Fix nxstyle issues.
 2021-01-17 09:52:17 -08:00
chao.an
328b7c06bc sim/hcitty: add hcitty adapter 
add support to attach the devices via HCI TTY to Bluetooth Host

Reference:

drivers/wireless/bluetooth/bt_uart_shim.c

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-01-16 21:32:10 -08:00
Matias N
93ef2e7174 nrf52 GPIO: set GPIO drive setting and missing input buffer configuration 2021-01-16 21:04:44 -08:00
Matias N
2fcfd63f8e nrf52: fix build without serial 2021-01-16 21:04:44 -08:00
Matias N
6f3f1c07fb nrf52 i2c: disable peripheral while configuring 2021-01-16 21:04:44 -08:00
Matias N
e1b3374bce nrf52 spi: build fixes and a missing register setting (polarity) 2021-01-16 21:04:44 -08:00
Matias N
ebe596bcd1 nrf52: enable and fix build for SPI BITORDER 2021-01-16 21:04:44 -08:00
Matias N
5d4463121f nrf52: fix SPI3 irq macro naming 2021-01-16 21:04:44 -08:00
Matias N
c526f01ba7 nrf52: fix build for PWM without multichan enabled 2021-01-16 21:04:44 -08:00
Masayuki Ishikawa
497e2f9e0c arch: tiva: Fix lm3s_ethernet.c with DEBUGASSERT 
Summary:
- This commit fixes DEBUGASSERT in lm3s_ethernet.c

Impact:
- lm3s_ethernet.c only

Testing:
- Tested with lm3s6965-ek:discover with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-16 10:40:17 +01:00
Nathan Hartman
75d3ae959f arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_sdmmc.h:

    * Fix nxstyle issues.
 2021-01-15 23:23:08 +01:00
Nathan Hartman
fda9f63bd8 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_tim.c:

    * Fix nxstyle issues.
 2021-01-15 23:23:08 +01:00
Nathan Hartman
c76fd28b83 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_uid.c:

    * Fix nxstyle issues.
 2021-01-15 23:23:08 +01:00
Nathan Hartman
07b1014ef0 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_usbhost.h:

    * Fix nxstyle issues.
 2021-01-15 23:23:08 +01:00
Nathan Hartman
938db2fa9e arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_userspace.c:
arch/arm/src/stm32h7/stm32_userspace.h:

    * Fix nxstyle issues.
 2021-01-15 23:23:08 +01:00
Abdelatif Guettouche
c00141c41a arch/xtensa/Kconfig: The ESP32 has a different numbers for vectors and 
IRQs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-15 09:47:33 +01:00
Masayuki Ishikawa
5f0e334974 arch: cxd56xx: Fix a compile warning with CONFIG_DEBUG_ERROR=y 
Summary:
- This commit fixes a compile warning in cxd56_sdhci.c

Impact:
- None

Testing:
- Built with spresense:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-01-14 20:48:25 -06:00
liang
caf2d1430e arch/risc-v/bl602: add gpioirq and i2c(master) driver 2021-01-14 08:55:03 -08:00
Abdelatif Guettouche
8e4397968c net/ & esp32/wlan: Fix some typos and nxstyle issues. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-01-14 07:57:27 -06:00
YAMAMOTO Takashi
27a49331fc sim: Link libc++abi for LIBCXX + macOS 2021-01-14 04:26:12 -06:00
David Sidrane
657088318a stm32412: Fixes pinmap CAN1 2021-01-13 11:01:44 -06:00
Nathan Hartman
095d99717b arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_rcc.c:
arch/arm/src/stm32h7/stm32_rcc.h:

    * Fix nxstyle issues.
 2021-01-13 11:01:03 -06:00
YAMAMOTO Takashi
ca0932f842 esp32_i2c.c: Remove useless casts 2021-01-13 11:04:59 +01:00
Xiang Xiao
0dc6990166 Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-13 08:57:58 +01:00
Xiang Xiao
0536953ded Kernel module should prefer functions with nx/kmm prefix 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-13 08:57:58 +01:00
Nathan Hartman
15480e51cf arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_qencoder.c:

    * Fix nxstyle issues.
 2021-01-12 19:06:44 +01:00
liang
32708ab849 arch/risc-v/bl602 : add spiflash(hardware sf controller) 2021-01-11 17:59:00 -08:00
Dong Heng
7a953bb154 xtensa/esp32: Fix ESP32 SPI3 slave ops data error 2021-01-11 09:10:18 +01:00
Xiang Xiao
fbc68912b9 arch/sim: Simplify SYMBOL macro definition 
Change-Id: I1772b65b9bbe29917885e432056f84921b562eb0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-01-10 11:10:09 +01:00
liang
2889315c20 arch/risc-v/bl602 : add pwm onshot watchdog driver. 2021-01-06 23:40:37 -08:00
Nathan Hartman
2cfbfa8213 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_pwr.c:

    * Fix nxstyle issues.
 2021-01-07 01:11:43 +01:00
Nathan Hartman
f30097d0ab arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_pmstop.c:

    * Fix nxstyle issues.
 2021-01-07 01:11:43 +01:00
Nathan Hartman
4c82459851 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_dma.h:

    * Fix nxstyle issues.
 2021-01-07 01:11:43 +01:00
Nathan Hartman
8cc9308da7 arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/chip.h:

    * Fix nxstyle issues.
 2021-01-07 01:11:43 +01:00
ligd
f63db66382 mqueue: add file_mq_xx for kernel use 
Change-Id: Ida12f5938388cca2f233a4cde90277a218033645
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-01-05 02:40:43 -06:00
Nathan Hartman
4ccaedf91f arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_adc.c:
arch/arm/src/stm32h7/stm32_adc.h:

    * Fix nxstyle issues.
 2021-01-04 13:04:51 -06:00
Dong Heng
fadae0bf39 xtensa/esp32: Fix ESP32 serial UART tx ready check error 2021-01-04 09:19:53 +01:00
Nathan Hartman
ec0b2f063c arch/stm32h7: Fix nxstyle errors 
arch/arm/src/stm32h7/stm32_bbsram.h:

    * Fix nxstyle issues.
 2021-01-03 20:30:45 -06:00
Brennan Ashton
dd26d9c9f9 BL602: Add support for system reboot modes 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2021-01-02 00:14:37 -06:00
Nathan Hartman
7592fc17d3 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_otghs.h:

    * Fix nxstyle issues.
 2021-01-01 18:17:03 +01:00
Nathan Hartman
588227ed7b arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_otgfs.h:

    * Fix nxstyle issues.
 2020-12-31 20:32:13 +01:00
Xiang Xiao
c647faa117 Fix nxstyle warning 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-31 09:37:29 +01:00
Xiang Xiao
0defe43282 OS internal function should indicate the error by return negative value 
instead to change errno value by calling set_errno

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-31 09:37:29 +01:00
Brennan Ashton
c8db3293bb BL602: Use sig mask instead of number for AHB swrst 2020-12-30 23:27:42 -06:00
Brennan Ashton
e062bd08ce bl602: Update register defines and drivers 2020-12-30 23:27:42 -06:00
Nathan Hartman
81224cc596 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_spi.h:

    * Fix nxstyle issues.
 2020-12-30 10:20:15 -06:00
chao.an
961532a5da arch/sim/hci: reuse the reserved fields of hci buffer 
Reuse the reserved fields of hci buffer to avoid redundant packet type splitting

Change-Id: I79d70ae939111bb909a6e0981c50e401734590f2
Signed-off-by: chao.an <anchao@xiaomi.com>
 2020-12-29 18:10:04 -08:00
chao.an
2ca99ed1be sim/host/hcisocket: add avail/close interface 
Change-Id: I3d96f62c4c3c7d703bfec74952953bee4aef9c7c
Signed-off-by: chao.an <anchao@xiaomi.com>
 2020-12-29 18:10:04 -08:00
Nathan Hartman
763aae8155 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_rtc.h:

    * Fix nxstyle issues.
 2020-12-29 08:36:31 -06:00
Virus.V
5f71e2be79 fix ci build failed 2020-12-29 01:52:09 -08:00
Virus.V
3e0a84182e check bl602 license 2020-12-29 01:52:09 -08:00
yangyue
d354a2f19f fix some code style 2020-12-29 01:52:09 -08:00
Virus.V
12258d72d2 Fix the BL602 mtimer frequency error. 2020-12-29 01:52:09 -08:00
Virus.V
2b8e0945a9 Fix BL602 CI Build failed. 
Modify the default configuration in KConfig.
Sync latest commit from mainline.

Remove unused demo configuration

fixup bl602 nsh defconfig cause CICD failed

Rebase from mainline code
 2020-12-29 01:52:09 -08:00
Virus.V
7e84874cb1 Reconstruct bl602 readme; move up_irq_save/restore declaration to common place 2020-12-29 01:52:09 -08:00
Virus.V
ce40edbd11 Solve the problems pointed out in the comments 2020-12-29 01:52:09 -08:00
Virus.V
417d0d4ccd fix checkpatch warning 2020-12-29 01:52:09 -08:00
Lei Chen
58bd873729 Add Basic support for BL602(UART timer CLIC) 2020-12-29 01:52:09 -08:00
Peter van der Perk
673a4b5b39 arch: S32K/Kinetis: Fix RTC settime prescaler 2020-12-28 23:32:33 +01:00
Sara Souza
65f39fc0c7 xtensa/esp32: Added driver api to reload counter instantly 2020-12-28 12:08:27 +01:00
Masayuki Ishikawa
b784fd6c3c arch: cxd56xx: Replace license header with Apache License 2.0 
Summary:
- This commit replaces SHES related headers under cxd56xx

Impact:
- No impact

Testing:
- Build check only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-28 08:43:35 +01:00
dongjiuzhu
b83ae99456 rpmsg_uart: fix compile break when enable rptun 
nuttx.rel: In function `rpmsg_serialinit':
nuttx/arch/sim/src/sim/up_rptun.c:257: undefined reference to `uart_rpmsg_init'
collect2: error: ld returned 1 exit status
Makefile:310: recipe for target 'nuttx' failed

Change-Id: I93a20941bc07f749165dc8f012da46ddb7b02b00
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
 2020-12-25 21:07:04 +01:00
YAMAMOTO Takashi
e1c53eaeb0 arch/sim/include/irq.h: Make 32-bit xcpt_reg_t unsigned 
* 64-bit version is already unsigned

* up_copyfullstate uses unsigned for 32-bit

 Error: sim/up_unblocktask.c:107:33: error: pointer targets in passing argument 1 of 'up_copyfullstate' differ in signedness [-Werror=pointer-sign]
  107 |           up_savestate(rtcb->xcp.regs);
      |                        ~~~~~~~~~^~~~~
      |                                 |
      |                                 xcpt_reg_t * {aka int *}
sim/up_internal.h:133:45: note: in definition of macro 'up_savestate'
  133 | #define up_savestate(regs) up_copyfullstate(regs, (xcpt_reg_t *)CURRENT_REGS)
      |                                             ^~~~
sim/up_internal.h:205:33: note: expected 'uint32_t *' {aka 'unsigned int *'} but argument is of type 'xcpt_reg_t *' {aka 'int *'}
  205 | void up_copyfullstate(uint32_t *dest, uint32_t *src);
      |                       ~~~~~~~~~~^~~~
 2020-12-24 21:57:39 -06:00
Nathan Hartman
080b2dfceb arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_exti.h:
arch/arm/src/stm32/stm32_flash.c:
arch/arm/src/stm32/stm32_fsmc.c:
arch/arm/src/stm32/stm32_fsmc.h:
arch/arm/src/stm32/stm32_hciuart.h:
arch/arm/src/stm32/stm32_mpuinit.h:
arch/arm/src/stm32/stm32_rtc.c:

    * Fix nxstyle issues.
 2020-12-24 23:21:16 +01:00
chao.an
08b22784c3 sim/names: add writev/readv into name list 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2020-12-24 11:09:59 -03:00
Nathan Hartman
dad32ccd47 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_dma.h:

    * Fix nxstyle issues.
 2020-12-23 20:35:42 -06:00
Masayuki Ishikawa
ace6e70f57 arch: imx6: Add imx_enet driver 
Summary:
- This commit adds imx_enet driver derived from imxrt_enet

Impact:
- imx6 only

Testing:
- Tested with sabre-6quad:netnsh
- NOTE: telnetd works with QEMU
 2020-12-23 16:56:25 -03:00
Masayuki Ishikawa
1725e50a13 arch: imx6: Fix peripheral IP offsets in AIPS-2 
Summary:
- This commit fixes peripheral IP offsets in AIPS-2

Impact:
- No impact because there is no drivers

Testing:
- Tested with sabre-6quad:nsh and sabre-6quad:smp
 2020-12-23 16:56:25 -03:00
Masayuki Ishikawa
4ce99f324e arch: imx6: Fix style warnings in imx_memorymap.h 2020-12-23 16:56:25 -03:00
Fotis Panagiotopoulos
e26daf9357 STM32 FLASH latency is calculated based on Vin. 2020-12-23 08:13:45 -08:00
Michal Lenc
52416888f7 fix nx style warnings and errors 
Signed-off-by: Michal Lenc <lencmich@fel.cvut.cz>
 2020-12-23 11:19:53 -03:00
liang
b074ebec9e fix redefined CSR_INSTRET 2020-12-23 01:34:14 -06:00
Sara Souza
6a6121378c xtensa/esp32: Fixed wdt typos 2020-12-22 20:32:38 +01:00
YAMAMOTO Takashi
0fbfc4c44c esp32_wifi_adapter.c: file mode for open doesn't make sense for O_RDONLY 2020-12-22 03:37:29 -06:00
Huang Qi
073912e232 Replace all wget with curl 
wget is missing from some system (like macOS and Windows native),
it's better to use curl to simplify build environment.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2020-12-22 03:36:10 -06:00
Brennan Ashton
c6947199b2 Bluetooth: Fix bt_buff lifecycle 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
 2020-12-21 23:36:57 -06:00
Masayuki Ishikawa
ec73a4e69c arch & sched: task: Fix up_exit() and nxtask_exit() for SMP 
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
  I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
  section too early before context switching which resulted in
  selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
  from nxtask_exit() to up_exit() and also removing
  spin_setbit() and spin_clrbit() from nxtask_exit()
  because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
  were done for all CPU architectures

Impact:
- This commit affects all CPU architectures regardless of SMP

Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-21 23:29:56 -06:00
Nathan Hartman
78f308ff2c arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_dac.h:

    * Fix nxstyle issues.
 2020-12-21 20:20:17 +01:00
Nathan Hartman
4cefc5ce7a stm32g4: Fix incorrect FLASH wait states 
When the architectural support for STM32G4 family was added, the
reference manual (RM0440) was at revision 2. Since then, it has
undergone several revisions. One significant change is in the
table of FLASH wait states: section 3.3.3 table 9. The outcome
of this change is that fewer FLASH wait states are needed for
most CPU clock (HCLK) frequencies. Notably, if running the CPU
clock at the maximum 170 MHz, only 4 FLASH wait states are
needed, rather than the previously programmed 8 wait states.
This gives a noticeable performance boost.

arch/arm/src/stm32/stm32g4xxxx_rcc.c:

    * FLASH_ACR_LATENCY_SETTING: Reimplement compile-time logic
      that selects the required wait state setting to use the new
      updated table.

    * Update all comments to indicate that RM0440 Rev 5 is used.

    * Update section numbers mentioned in comments in cases where
      they have changed due to added sections in the manual.
 2020-12-21 18:43:49 +01:00
Xiang Xiao
92cefb0a78 arch/risc-v: Move CSR register bit definition to csr.h 
to avoid the macro duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-20 20:27:13 -08:00
Xiang Xiao
41d576f62b arch/riscv: Reuse the common up_schedule_sigaction implementation 
to avoid the code duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-20 20:26:27 -08:00
Nathan Hartman
4facd82ae0 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_ltdc.h:
arch/arm/src/stm32/stm32_pmsleep.c:
arch/arm/src/stm32/stm32_pmstandby.c:

    * Fix nxstyle issues.
 2020-12-19 00:16:47 -06:00
Xiang Xiao
d42c5a0bf6 arch/risc-v: Move csr.h to common place 
since CSR definition is same for 32bit and 64bit arch

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-19 08:41:33 +09:00
Xiang Xiao
fe8122ee2b arch/risc-v: Remove duplicated declaration for up_irq_save and up_irq_restore 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-19 08:29:42 +09:00
Abdelatif Guettouche
81a9eb190d arch/xtensa/src/esp32/esp32_spiflash.c: Invalidate the cache and 
writeback PSRAM data if the flash address used has a cache mapping.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-18 16:43:52 -03:00
chao.an
4a559807a5 arch/netdev: try tcp timer in every txavail call 
In the current implementation, the first transmission of the new
connection handshake is depends entirely by tcp_timer(), which will
caused 0.5s - 1s delay each time in connect().

This patch is mainly to improve the performance of TCP handshake.

Original:

nsh> tcp_client
[    1.536100] TCP connect start.
[    2.000200] TCP connect end. DIFF: tick: 4641, 464ms.
[    3.000300] TCP connect start.
[    4.000400] TCP connect end. DIFF: tick: 10001, 1000ms.
[    5.000500] TCP connect start.
[    6.000600] TCP connect end. DIFF: tick: 10001, 1000ms.
[    7.000700] TCP connect start.
[    8.000800] TCP connect end. DIFF: tick: 10001, 1000ms.

Optimized:

nsh> tcp_client
[    3.263600] TCP connect start.
[    3.263700] TCP connect end. DIFF: tick: 1, 0ms.
[    4.263800] TCP connect start.
[    4.263800] TCP connect end. DIFF: tick: 0, 0ms.
[    5.263900] TCP connect start.
[    5.263900] TCP connect end. DIFF: tick: 0, 0ms.
[    6.264000] TCP connect start.
[    6.264000] TCP connect end. DIFF: tick: 0, 0ms.
[    7.264100] TCP connect start.
[    7.264100] TCP connect end. DIFF: tick: 0, 0ms.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2020-12-18 14:16:11 +09:00
YAMAMOTO Takashi
48ba0bb30a esp32_wifi_adapter.c: Fix a use-after-free bug 2020-12-17 03:24:15 -06:00
YAMAMOTO Takashi
75bc489e24 esp32: Fix phy_printf 
Fix the following error:

CC:  chip/esp32_wifi_adapter.c
In file included from /Users/yamamoto/git/nuttx/nuttx/include/nuttx/mm/shm.h:45,
                 from /Users/yamamoto/git/nuttx/nuttx/include/nuttx/sched.h:42,
                 from /Users/yamamoto/git/nuttx/nuttx/include/sched.h:35,
                 from /Users/yamamoto/git/nuttx/nuttx/include/stdio.h:48,
                 from chip/esp32_wifi_adapter.c:28:
chip/esp32_wifi_adapter.c: In function 'phy_printf':
chip/esp32_wifi_adapter.c:3952:10: error: expected ')' before 'format'
   wlinfo(format, arg);
          ^~~~~~
 2020-12-17 03:24:15 -06:00
Christian
abcc41d17d fix: arch/.../stm32h7x3xx_memorymap.h invalid address map for fdcan 2020-12-16 20:27:07 -06:00
Sara Souza
1acba417c4 xtensa/esp32: enables started flag if the wdt was turned on in bootloader 2020-12-16 16:35:55 -03:00
RICHNER Jonathan
6339fcfdd3 arch/arm/src/stm32h7/stm32_ethernet.c: Fix typo in multicast address hash 
table registers for STM32H7
 2020-12-16 10:01:25 -06:00
Sara Souza
71715aaee8 xtensa/esp32: fixes enable int function and gets apb clk frequency through function 2020-12-16 10:48:02 -03:00
Sara Souza
add46d0408 xtensa/esp32: Added support for RTC WDT 2020-12-16 14:37:39 +01:00
Sara Souza
be12c79c52 xtensa/esp32: Changes in rtc driver to support rtc wdt driver 2020-12-16 14:37:39 +01:00
Abdelatif Guettouche
ecede04263 arch/*/src/Makefile: Generate dependencies for head files. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-15 21:00:52 -06:00
Xiang Xiao
625eef20f0 arch: Remove the special check for idle thread in up_use_stack 
since the idle thread don't call up_use_stack anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-16 09:54:29 +09:00
Xiang Xiao
efee1c6ded arch: Initialize the idle thread stack info directly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-16 09:54:29 +09:00
Michal Lenc
e1596e80aa arch/arm/src/imxrt/imxrt_usdhc.c: fixed no DMA build error 
Signed-off-by: Michal Lenc <lencmich@fel.cvut.cz>
 2020-12-15 12:39:58 -08:00
Nathan Hartman
b960bee78b arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_tim.c:

    * Fix nxstyle errors.
 2020-12-15 19:10:30 +01:00
YAMAMOTO Takashi
cb71469f85 esp32: Fix a typo. ESP_SPIRAM_BOOT_INIT -> ESP32_SPIRAM_BOOT_INIT 2020-12-15 02:07:05 -06:00
Bernd Walter
2ccc37f2a8 Fix syntax for BOARD_GCLK*_RUN_IN_STANDBY and BOARD_GCLK*_OUTPUT_ENABLE 
with GCLK1-8
 2020-12-15 08:46:10 +01:00
Nathan Hartman
3adadbe5d7 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_usbhost.h:

    * Fix nxstyle errors.
 2020-12-15 06:47:20 +01:00
Nathan Hartman
705c64e5ff arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_wwdg.c:

    * Fix nxstyle errors.
 2020-12-13 22:54:03 +01:00
John Bampton
ba12c6c0cf Fix spelling 2020-12-12 19:18:08 +01:00
Nathan Hartman
2fda2451e3 arch/stm32: Add register definitions for STM32G4 ADC 
arch/arm/src/stm32/hardware/stm32_adc_v2g4.h:

    * New file.

arch/arm/src/stm32/hardware/stm32_adc.h:

    * Distinguish between the normal STM32 ADC IPv2 core and the
      modified IPv2 core used in the G4 family, and include either
      stm32_adc_v2.h or stm32_adc_v2g4.h as needed.
 2020-12-12 13:58:51 +01:00
Nathan Hartman
3864912dc8 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32l15xxx_rtcc.c:

    * Fix nxstyle errors.
 2020-12-11 15:04:13 -03:00
danguanghua
796217917a fix build break with CONFIG_AUDIO_MULTI_SESSION enabled 
N/A

Change-Id: Idfa87031e09f26bd4ca57b5c220ce0ca849f80c4
Signed-off-by: danguanghua <danguanghua@xiaomi.com>
 2020-12-11 08:04:30 -06:00
Xiang Xiao
73d4832c15 arch/arm/imxrt: replace clock_systimespec with clock_systime_timespec 
since clock_systimespec doesn't exist anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2020-12-11 04:20:40 -08:00
Masayuki Ishikawa
6158b6b77b spinlock: Introduce SP_WFE() and SP_SEV() 
Summary:
- This commit introduces SP_WFE() and SP_SEV() to be used for spinlock
- Also, use wfe/sev instructions for ARMV7-A to reduce power consumption

Impact:
- ARMV7-a SMP only

Testing:
- sabre-6quad:smp (QEMU, dev board)
- maix-bit:smp, esp32-devkitc:smp, spresense:smp sim:smp (compile only)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-11 05:58:35 -06:00
Sara Souza
6244924c3e Removed initconf from esp32_wtd_ops_s 2020-12-10 20:31:15 -06:00
Sara Souza
2a9dab2e5d xtensa/esp32: allows the rtc wdt to be configured in bootloader and used later 2020-12-10 20:31:15 -06:00
Masayuki Ishikawa
b599823f3b arch: armv7-a: Remove unnecessary #ifdef CONFIG_SMP in arm_unblocktask.c 
Summary:
- Because this_task() returns the current task of the current CPU

Impact:
- SMP only

Testing:
- Tested with sabre-6quad:smp (QEMU)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-10 20:27:59 -06:00
Abdelatif Guettouche
f7c5b467e1 arch/xtensa/src/esp32: Remove the EXPERIMENTAL config from the Wireless. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
56713e0304 arch/xtensa/src/esp32/Make.defs: Don't condition including the low level 
WDT driver with the upper layer driver.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-10 12:31:17 -06:00
Abdelatif Guettouche
3ba5018b37 boards/xtensa/esp32: A bit of re-organisation in the ESP32 boards. 
Move the common files into the common directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-10 12:31:17 -06:00
Nathan Hartman
648ec7bee4 arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32l15xxx_rcc.c:

    * Fix nxstyle errors.
 2020-12-10 18:30:24 +01:00
Masayuki Ishikawa
f3a81cb1b7 sim: Fix interrupt handling for SMP 
Summary
- This commit fixes interrupt handling for SMP
- The following are the changes
- Introduce up_copyfullstate.c
- Add enter_critical_section() to up_exit()
- Add a critical section to up_schedule_sigaction()
- Introduce pseudo timer thread to send periodic events
- UART and interval timer are now handled in the pause handler
- Apply the same SMP related code as other CPU architectures
- However, signal handling and context switching are not changed
- Also enable debug features and some tools in smp/defconfig

Imact
- SMP only

Testing
- Tested with sim:smp on ubuntu18.04 x86_64
- Tested with hello, taskset, smp, ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-10 08:33:42 +01:00
Masayuki Ishikawa
ad9f88f042 Revert "Revert "arch/sim: Make the SIGUSR1 host signal to use the NuttX irq logic"" 
This reverts commit 3098b61776.
 2020-12-10 08:33:42 +01:00
Masayuki Ishikawa
409c65ce0b arch, sched: Fix global IRQ control logics for SMP 
Summary:
- This commit fixes global IRQ control logic
- In previous implementation, g_cpu_irqset for a remote CPU was
  set in sched_add_readytorun(), sched_remove_readytorun() and
  up_schedule_sigaction()
- In this implementation, they are removed.
- Instead, in the pause handler, call enter_critical_setion()
  which will call up_cpu_paused() then acquire g_cpu_irqlock
- So if a new task with irqcount > 1 restarts on the remote CPU,
  the CPU will only hold a critical section. Thus, the issue such as
  'POSSIBLE FOR TWO CPUs TO HOLD A CRITICAL SECTION' could be resolved.
- Fix nxsched_resume_scheduler() so that it does not call spin_clrbit()
  if a CPU does not hold a g_cpu_irqset
- Fix nxtask_exit() so that it acquires g_cpu_irqlock
- Update TODO

Impact:
- All SMP implementations

Testing:
- Tested with smp, ostest with the following configurations
- Tested with spresense:wifi_smp (NCPUS=2,4)
- Tested with sabre-6quad:smp (QEMU, dev board)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2020-12-10 08:33:42 +01:00
Abdelatif Guettouche
5d7428a385 arch/xtensa: Fix alignement when coloring and checking the stacks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
Abdelatif Guettouche
7075c98978 arch/xtensa: Add a pseudo save area to be able to backtrace from 
interrupts

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
Abdelatif Guettouche
1f96f42f1e arch/xtensa/include/irq.h: Reserve some space for interptee's BSA. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
Abdelatif Guettouche
368d21a0b9 arch/xtensa/src/common/xtensa_context.S: Name A3 register the usual way. 
i.e. a3 instead of r3.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
Abdelatif Guettouche
5f9d9ba44c arch/xtensa/src/common/xtensa_context.S: Don't save CALL0 ABI 
callee-saved registers.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
Abdelatif Guettouche
716a29ebeb arch/xtensa/src/common/xtensa_backtrace.S: Update the comments to show 
the functions in play during the backtrace.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-12-09 09:44:04 -03:00
raiden00pl
0c05f2ea38 stm32: add stm32g43x support and nucleo-g431rb board 2020-12-09 09:43:25 -03:00
Nathan Hartman
c257c458ad arch/stm32: Fix nxstyle errors 
arch/arm/src/stm32/stm32_rng.c:

    * Fix nxstyle errors.
 2020-12-09 09:21:42 +01:00
Juha Niskanen
7bc7b611d6 arch/arm/src/lc823450: fully parenthesize MIN and MAX macros 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2020-12-08 12:58:40 -06:00
Nathan Hartman
c162069cd5 arch/stm32: Fix nxstyle errors (and one typo) 
arch/arm/src/stm32/stm32_dma2d.h
arch/arm/src/stm32/stm32_fmc.h
arch/arm/src/stm32/stm32_freerun.h
arch/arm/src/stm32/stm32_pm.h

    * Fix nxstyle errors.

arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h

    * Fix typo in comment.
 2020-12-07 22:22:02 +01:00
raiden00pl
979a5b7fd4 stm32: convert all STM32G47X specific code to generic STM32G4 series code. 
This is an initial step towards supporting other STM32G4 chips.
 2020-12-06 13:37:02 -05:00
YAMAMOTO Takashi
b18c2e6cc5 arch/arm/src/arm/arm_assert.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
c3791e7c23 arch/arm/src/armv7-m/arm_assert.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
330aa43f72 arch/arm/src/stm32/stm32_adc.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
44f88cd71a arch/arm/src/lpc17xx_40xx/lpc17_40_can.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
065d310cf2 arch/arm/src/stm32f0l0g0/stm32_adc.c: Don't assume debug macro expansion 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
d11bcef391 arch/x86_64/src/common/up_assert.c: Avoid assuming how _alert is expanded 2020-12-06 09:03:09 -06:00
YAMAMOTO Takashi
a600b2478d arch/arm/src/s32k1xx/s32k1xx_flexcan.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
1c7bdcea98 arch/arm/src/s32k1xx/s32k1xx_lpspi.c: Fix a syslog format 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
cba6e69ccf arch/arm/src/s32k1xx/s32k1xx_lpi2c.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
fbf7d7cdf9 arch/arm/src/sam34/sam_emac.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
2829ecd18a arch/arm/src/sam34/sam_spi.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
5461bb2462 arch/arm/src/sam34/sam4s_nand.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
fcca968c0b arch/arm/src/sam34/sam_wdt.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
f22982f7e6 arch/arm/src/sam34/sam_wdt.c: Appease nxstyle 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
8eb0712dec arch/arm/src/sam34/sam_hsmci.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
8af7af12b3 arch/arm/src/sama5/sam_emacb.c: Fix a syslog format 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
83b24f0382 arch/arm/src/armv7-a/arm_syscall.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
3152ee6c62 arch/arm/src/sama5/sam_emacb.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
c3bcf80a18 arch/arm/src/sama5/sam_xdmac.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
c8eb8ac9c1 arch/arm/src/sama5/sam_xdmac.c: Appease nxstyle 2020-12-06 07:41:37 -06:00
YAMAMOTO Takashi
59dc739895 arch/arm/src/sama5/sam_ssc.c: Fix syslog formats 2020-12-06 07:41:37 -06:00
Matias N
ec83dc2ad3 nxstyle fixes 2020-12-05 21:44:49 -06:00
Matias N
de9842ab60 LPC43 RIT: build fixes 2020-12-05 21:44:49 -06:00
YAMAMOTO Takashi
0a4ee70f39 arch/renesas/src/common/up_createstack.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
e7389c8ef2 arch/renesas/src/rx65n/rx65n_eth.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
0583789abe arch/renesas/src/rx65n/rx65n_dumpstate.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
d6e1ae5616 arch/mips/src/pic32mz/pic32mz_spi.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
efde691052 arch/mips/src/pic32mx/pic32mx_spi.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
326b217ef4 arch/mips/src/pic32mx/pic32mx_ethernet.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
7b66e23a6a arch/mips/src/pic32mx/pic32mx_ethernet.c: Remove non-ascii characters 
0x91 and 0x92. I don't know what they are.
 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
41306dbeae arch/mips/src/mips32/mips_dumpstate.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
bc2fe40f5b arch/mips/src/mips32/mips_vfork.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
4699e9dfde arch/mips/src/mips32/mips_swint0.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
7731de24e8 arch/mips/src/mips32/mips_sigdeliver.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
2d243f2c2d arch/mips/src/mips32/mips_schedulesigaction.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
58fdaa5c2d arch/xtensa/src/esp32/esp32_wifi_adapter.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
a927f98a23 arch/arm/src/imxrt/imxrt_flexcan.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
29400f0e38 arch/arm/src/sama5/sam_tsd.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
9510c968cd arch/arm/src/sama5/sam_hsmci.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
a88da8f7d7 arch/arm/src/sama5/sam_spi.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
1a71802a06 arch/arm/src/sama5/sam_dmac.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
cc9c652a58 arch/arm/src/sama5/sam_dmac.c: Appease nxstyle 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
260b1af52b arch/arm/src/sama5/sam_dmac.c: Remove non ascii characters 
0x91 and 0x92. I don't know what they are.
 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
2a94c70ec8 arch/arm/src/sama5/sam_twi.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
05bf54fdbc arch/arm/src/sama5/sam_lcd.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
4c3d8e7429 arch/arm/src/sama5/sam_lcd.c: Appease nxstyle 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
7cb69a652d arch/arm/src/samv7/sam_twihs.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
ec4b3d3e84 arch/arm/src/samd5e5/sam_eic.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
7eacf123ec arch/arm/src/samd5e5/sam_tc.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
113b2b899a arch/arm/src/samv7/sam_spi.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
df4c60c96d arch/sim/src/sim/up_touchscreen.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
17f8bcc574 arch/arm/src/sama5/sam_sdmmc.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
84fa0a9b6c arch/arm/src/sama5/sam_ehci.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
cf9e8bb03e arch/arm/src/sama5/sam_ohci.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
ad158866ed arch/arm/src/sama5/sam_ohci.c: Appease nxstyle 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
471e94c57b arch/arm/src/sama5/sam_gmac.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
9450e02f3a arch/arm/src/sama5/sam_emaca.c: Fix syslog formats 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
700eaaa6fe arch/arm/src/sama5/sam_udphs.c: Fix a syslog format 2020-12-05 08:13:32 -06:00
YAMAMOTO Takashi
e297ed9cfe arch/arm/src/sama5/sam_memories.c: Fix syslog formats 2020-12-05 08:13:32 -06:00