imxrt UART must be placed in 9 bit mode (M=1) with when 8 bit
data with parity is required. If left in 8 bit mode (M=0) with
parity then D7 of the TX/RX register becomes parity bit. Hence
what is called 9-bit or 8-bit Mode Select is a misnomer.
8 bit mode when parity is enabled is realy 7 bit with parity.
I left mixed case identifiers for another commit.
arch/arm/src/imxrt/imxrt_lcd.c:142:13: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:143:13: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:147:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:157:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:162:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:173:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:184:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:195:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:208:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:210:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:212:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:214:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:11: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:23: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:33: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:519:11: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:519:23: error: Mixed case identifier found
The following nxstyle errors are intentionally left.
They are constants definitions like TPM_CnSC_MSB.
arch/arm/src/kl/kl_pwm.c:438:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:438:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:445:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:445:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:452:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:452:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:459:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:459:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:466:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:466:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:473:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:473:59: error: Mixed case identifier found
The following errors are intentionally left.
(Hardware constants like DMA2D_xGPFCCR_CCM.)
arch/arm/src/stm32/stm32_dma2d.c:484:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:692:13: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:701:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:706:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:711:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:725:14: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:732:18: error: Mixed case identifier found
The following nxstyle errors are intentionally left.
They are "Lx" constants shared among multiple files.
arch/arm/src/stm32/stm32_ltdc.c:1774:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1775:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1779:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1780:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1784:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1785:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1804:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1805:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1806:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1845:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1849:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:34: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:35: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1987:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1991:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2027:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2031:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_oneshot.c:
arch/arm/src/stm32/stm32_oneshot.h:
arch/arm/src/stm32/stm32_oneshot_lowerhalf.c:
arch/arm/src/stm32/stm32_dbgmcu.h:
* Fix nxstyle errors.
arch/arm/src/stm32/stm32_lsi.c:
* Fix nxstyle errors.
* Also a minor grammar fix in a comment: add "in" to "setting the
LSION bit in the RCC CSR register."
stm32f7, stm32h7, stm32l4 and stm32f0l0g0 do it this way and there is no
reason for classic stm32 to differ. Also manipulation of priv->ie was not
atomic with respect to interrupts.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with esp32-core:smp (QEMU)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with maix-bit:smp (QEMU)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with lc823450-xgevk:rndis
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that sched_add_readytorun() runs on multiple CPUs simultaneously
- Finally, I found the root cause which was described in TODO
- Actually, the task newly scheduled on remote CPU did not acquire g_cpu_irqlock
- This commit fixes this issue by adding a critical section to the pause handler
- Which will acquire g_cpu_irqlock on the remote CPU explicitly
Impact:
- SMP only
Testing:
- Tested with spresense:wifi_smp (NCPUS=2 and 4)
- Run smp, ostest, nxplayer
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that Cortex-A SGI can be masked
- We thought the SGI is not maskable
- Although I can not remember how I tested it before
- It actually works as expected now
- Also, fixed the number of remaining bugs in TODO
Impact:
- No impact
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Add the following code in up_idle() before calling asm("WFI");
+ if (0 != up_cpu_index())
+ {
+ up_irq_save();
+ }
- Run the hello app, you can see "Hello, World!!"
- But nsh will freeze soon because arm_pause_handler is not called.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
64-bit size_t/intptr_t/ptrdiff_t are long, not long long,
for macOS and Linux.
Note: we don't care CONFIG_SIM_M32 on macOS.
macOS:
spacetanuki% uname -a
Darwin spacetanuki.lan 18.7.0 Darwin Kernel Version 18.7.0: Mon Aug 31 20:53:32 PDT 2020; root:xnu-4903.278.44~1/RELEASE_X86_64 x86_64
spacetanuki% cc --version
Apple clang version 11.0.0 (clang-1100.0.33.17)
Target: x86_64-apple-darwin18.7.0
Thread model: posix
InstalledDir: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin
spacetanuki% cc -dM -E - < /dev/null|grep __SIZE_TYPE__
#define __SIZE_TYPE__ long unsigned int
spacetanuki% cc -m32 -dM -E - < /dev/null|grep __SIZE_TYPE__
#define __SIZE_TYPE__ long unsigned int
spacetanuki%
Linux:
root@4c2e9e83ac82:/tools# uname -a
Linux 4c2e9e83ac82 5.4.39-linuxkit #1 SMP Fri May 8 23:03:06 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
root@4c2e9e83ac82:/tools# cc --version
cc (Ubuntu 9.3.0-10ubuntu2) 9.3.0
Copyright (C) 2019 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
root@4c2e9e83ac82:/tools# cc -dM -E - < /dev/null|grep __SIZE_TYPE__
#define __SIZE_TYPE__ long unsigned int
root@4c2e9e83ac82:/tools# cc -m32 -dM -E - < /dev/null|grep __SIZE_TYPE__
#define __SIZE_TYPE__ unsigned int
root@4c2e9e83ac82:/tools#
root@212cf3f52994:/tools# p32-gcc -mlong32 -dM -E - < /dev/null | grep "__INT.*_TYPE__"|sort
#define __INT16_TYPE__ short int
#define __INT32_TYPE__ long int
#define __INT64_TYPE__ long long int
#define __INT8_TYPE__ signed char
#define __INTMAX_TYPE__ long long int
#define __INTPTR_TYPE__ int
#define __INT_FAST16_TYPE__ int
#define __INT_FAST32_TYPE__ int
#define __INT_FAST64_TYPE__ long long int
#define __INT_FAST8_TYPE__ int
#define __INT_LEAST16_TYPE__ short int
#define __INT_LEAST32_TYPE__ long int
#define __INT_LEAST64_TYPE__ long long int
#define __INT_LEAST8_TYPE__ signed char
root@212cf3f52994:/tools#
root@212cf3f52994:/tools# rx-elf-gcc -dM -E - < /dev/null | grep "__INT.*_TYPE__"|sort
#define __INT16_TYPE__ short int
#define __INT32_TYPE__ long int
#define __INT64_TYPE__ long long int
#define __INT8_TYPE__ signed char
#define __INTMAX_TYPE__ long long int
#define __INTPTR_TYPE__ long int
#define __INT_FAST16_TYPE__ int
#define __INT_FAST32_TYPE__ int
#define __INT_FAST64_TYPE__ long long int
#define __INT_FAST8_TYPE__ int
#define __INT_LEAST16_TYPE__ short int
#define __INT_LEAST32_TYPE__ long int
#define __INT_LEAST64_TYPE__ long long int
#define __INT_LEAST8_TYPE__ signed char
root@212cf3f52994:/tools#
To make it match what the compiler expects.
on nuttx-ci-linux image:
root@fec5a6192c70:/tools# gcc -dM -E - < /dev/null | grep -E "UINT(32|64)_TYPE"
#define __UINT64_TYPE__ long unsigned int
#define __UINT32_TYPE__ unsigned int
root@fec5a6192c70:/tools#
on macOS:
spacetanuki% x86_64-elf-gcc -dM -E - < /dev/null | grep -E "UINT(32|64)_TYPE"
#define __UINT32_TYPE__ unsigned int
#define __UINT64_TYPE__ long unsigned int
spacetanuki%
So that it matches what the toolchain expects.
spacetanuki% riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (SiFive GCC 8.3.0-2019.08.0) 8.3.0
Copyright (C) 2018 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
spacetanuki% riscv64-unknown-elf-gcc -dM -E - < /dev/null | grep UINT64_TYPE
#define __UINT64_TYPE__ long unsigned int
spacetanuki%
It seems that part of the patch
stm32l4: correct build of stm32l4_can.c to respect L4 variant
has been lost on its way to mainline.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Summary:
- Remove unnecessary d-cache operation to make boot fast
Impact:
- armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:
* New files, based on STM32G474RE reference manual, RM0440 Rev 4.
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:
* Remove all mentions of DMAMUX12 from comments. This family has
at most DMAMUX1 only.
* Add missing defines DMAMUX_CCR_SPOL_NONE,
DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
DMAMUX_CCR_SPOL_BOTH.
* DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
but datasheet shows bits 24-28 (5 bits).
* DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
shows (5 bits) 0x1f.
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
datasheet shows only 2 bits (0x3).
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
but datasheet shows 5 bits (0x1f).
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_spi.h:
* Avoid numerous ifdef on STM32 part numbers and make the
different variations of SPI peripheral features more
self-documenting: based on STM32_HAVE_IP_SPI_V* defines
from chip.h, define some or all of HAVE_SPI_I2S,
HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
which registers and bitfields to define based on them.
* Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
currently used only for STM32G47XX family MCUs, including
SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
SPI_I2SCFGR_ASTRTEN.
* SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
(xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(0 << SPI_I2SCFGR_I2SSTD_SHIFT).
* SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
(0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(1 << SPI_I2SCFGR_I2SSTD_SHIFT).
* Fix nxstyle errors.
arch/arm/include/stm32/chip.h:
* Add new section "Peripheral IP versions" and specify version of
SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows only 2 bits.
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows 5 bits.
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.
Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).
This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.
This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event
There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
(gdb) b longjmp
Breakpoint 1 at 0x8270
(gdb) r
Starting program: /home/chao/code/m3/nuttx/nuttx
[ 0.000000] Assertion failed at file:task/task_onexit.c line: 99
Breakpoint 1, 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
(gdb)
(gdb) bt
|#0 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
|#1 0xf7f9c3dc in siglongjmp_alias () from /lib/i386-linux-gnu/libpthread.so.0
|#2 0x5655d668 in up_assert (filename=0x56641018 "task/task_onexit.c", line=99) at sim/up_head.c:132
|#3 0x56567413 in _assert (filename=0x56641018 "task/task_onexit.c", linenum=99) at assert/lib_assert.c:36
|#4 0x565f8cfd in on_exit (func=0x565f8c12 <exitfunc>, arg=0x565fd780 <simuart_restoremode>) at task/task_onexit.c:99
|#5 0x565f8c89 in atexit (func=0x565fd780 <simuart_restoremode>) at task/task_atexit.c:109
|#6 0x565fd819 in simuart_start () at sim/up_simuart.c:112
|#7 0x5656c844 in up_uartinit () at sim/up_uart.c:496
|#8 0x5656ba7a in up_initialize () at sim/up_initialize.c:234
|#9 0x5655da56 in nx_start () at init/nx_start.c:701
|#10 0x5655d5e9 in main (argc=1, argv=0xffffd6f4, envp=0xffffd6fc) at sim/up_head.c:96
Change-Id: Ifd7196b2de7bf9fc7cea764c19a5c0eacf08fdb6
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:
* Merge comments when they are section separators for
similar/related registers:
- TIVA_FLASH_FWPWRITE*
- TIVA_FLASH_FSM_SECTOR1*
- TIVA_FLASH_FSM_BSLE*
- TIVA_FLASH_FSM_BSLP*
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This adds the inital wiring for i2c bus support in the sim target
and for Linux host adds the lower half that uses the i2c chardev.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Squashed commit of the following:
sim audio: call alsa to playback/capture data
sim/audio: correct the format capability
sim/audio: add pause/resume support
sim/audio: add auto stop when meet AUDIO_APB_FINAL
sim/audio: fix abort when set small buffer_size
sim/audio: move sim_audio.c to sim_alsa.c
Change-Id: I8e00ece79159e844ca17fd4c363480b985ee0490
Signed-off-by: ligd <liguiding1@xiaomi.com>
1. function "stop" should really stop repeat timer
2. delete timer really in rt-timer task to avoid resource being broken
3. timer triggers when stopping/deleting it and skip it in ISR
When HAVE_HSI_CONTROL, adc_reset_hsi_disable() calls adc_reset()
followed by adc_shutdown() and this combination is called before
adc_setup() by upper level ADC driver. Without this patch,
priv->initialized wraps from 0 to 255 in this case.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
In the current compilation environment, the recursive assignment(=) for compile
flags will be delayed until every file is actually need to be compile.
For example:
--------------------------------------------------------------------------------
arch/arm/src/Makefile:
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
CPPFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CXXFLAGS += $(INCLUDES) $(EXTRAFLAGS)
AFLAGS += $(INCLUDES) $(EXTRAFLAGS)
--------------------------------------------------------------------------------
All compilation options will be included recursively,
which will be delayed until the compilation options are actually used:
tools/Config.mk:
--------------------------------------------------------------------------------
define COMPILE
@echo "CC: $1"
$(Q) $(CC) -c $(CFLAGS) $($(strip $1)_CFLAGS) $1 -o $2
endef
--------------------------------------------------------------------------------
All compile flags to be reexecuted $(INCDIR) as long as one file needs to be compiled,
but in fact, the compilation options have not changed in the current directory.
So the we recommand to change the syntax of assignment
From
Recursive (=)
To
Simple (:=)
In this way, we can ensure that all compilation options are expanded only once and reducing repeated works.
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h:
* Fix syntax error. The define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN
had an unintentional comment closing "*/" in the middle of its
name.
