1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/
RISC-V ISA updates
Compared to previous releases, starting from 12.x, the compiler implements the new RISC-V ISA, which introduces an incompatibility issue, and builds might throw error messages like unrecognized opcode csrr.
The reason is that csr read/write (csrr*/csrw*) instructions and fence.i instruction were separated from the I extension, becoming two standalone extensions: Zicsr and Zifencei.
The solution is to add _zicsr and/or _zifencei to the -march option, e.g. -march=rv32imac becomes -march=rv32imac_zicsr_zifencei.
Initialize ICACHE way with correct mask.
Initialize scratchpad with constant g_init_marker as it has been done in HSS
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Changes the executable type built against the `make export` target fully linked by default. This greatly improves performance when loading applications, as relocations no longer need to be processed.
In the default configuration, the Litex ethernet peripheral contains two RX and two TX buffers. The active buffer for the peripheral should be swapped as soon as possible, in order to reduce packet loss.
This modification acknowledges the receive buffer as soon as the pending data is copied into the NuttX device data buffer. Improving reliability under heavy load.
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.
Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
This adds support for the CoreMMC v3.1 FPGA driver as described
in Microchip Handbook HB0510. The driver doesn't support DMA.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.
Why?
1. Because the exception entry status (REG_INT_CTX) is needed by the
kernel, and this is now in user memory which requires that the correct
user mappings are active when it is accessed.
2. The user must currently account for the exception stack frame (which
is BIG) in its own stack allocation. Moving the exception context save
to the kernel stack offloads this responsibility from the user to the
kernel, which is IMO the correct behavior.
3. The kernel access to user memory is currently allowed without condition,
however this is not ideal either. The privileged mode status CSR allows
blocking access to user memory via the STATUS_SUM-bit, which should be
disabled by default and only enabled when access to user space is really
needed. This patch allows implementing such features.
This is preparation to use kernel stack for everything when the user
process enters the kernel. Now the user stack is in use when the user
process runs a system call, which might not be the safest option.
This is a minimalistic SBI implementation for NuttX.
Provides a single service for now:
- Access to machine timer
Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.
Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
so the call gate does this from M-mode
The only supported (tested) target for now is MPFS.
Remove unnecessary reading of the status register when loading / unloading
the FIFOs. Reading from the IP block is slow due to BUS synchronization and
this basically makes the SPI busy loop for no reason at all, destroying the
CPU usage.
The overall benefit of these changes is approx. 25%-points, which is a
MASSIVE improvement.
Adds a driver for an FPGA fabric / CoreSPI implementation.
Supports multiple instances, assuming they reside in some base address,
offsettable by a constant value.
External function to query vbus status. Reading from the block requires
the clock, but if no devices are open -> vbus detect does not work.
This creates a chicken / egg problem, if vbus detect is used to start
the usb device.
bmp388 works poorly as the system fires STOPs even in
a beginning of a transaction. Don't let unrelated STOPs
to distort the data flow.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds 2 more FPGA I2Cs. Also rework the indexing
so that it matches the earlier work without major changes.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This fixes the following issue:
- After sending the address, the driver writes an extra zero
Without this patch, the extra write causes an extra ACK that would
terminate the sequence prematurely. This is observed as data read
corruption.
With this fix, the condition is detected precisely. That being the
case, the sequence is continued with a repeated start, after which
the read continues normally.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This incorporates an fpga i2c driver into the existing i2c driver.
This fpga i2c works almost 100% as the MSS i2c, but the difference
is that the fpga driver terminates all transactions with a stop
sent -interrupt. That needs to be handled.
Fpga clock source is also different, act accordingly.
SEC2TICK(10) is an overkill to any app, use just one second instead.
modifyreg32s are simplified as well, no need to clear and set
as set is enough.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
I2C status register reset value (0xf8) was not handled properly causing unnecessary bus resets.
Added critical section to mpfs_i2c_reset() and removed unnecessary interrupt disabling elsewhere.
to avoid the infinite recusive dispatch:
*0 myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1 0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Move the mapping functionality from up_shmat/shmdt into two generic
mapping functions. This makes it possible to do other mappings besides
user shared memory area mappings.
During the serial reconfiguration from bootloader to the
NuttX a trash character "?" (Unicode replacement U+FFFD)
was printed in the screen.
This fix was discovered by Sylvio Alves from Espressif!
Instead of using Espressif's emulated NVS to save Wi-Fi data, use
`wapi`s wireless configure initialization mechanism for saving
Wi-Fi data. It 1) avoids creating a specific storage partition
just to save Wi-Fi data (ESP32-C3's storage partition is used
instead); 2) avoids initialization problems of the emulated NVS
when SMP is enabled (the Wi-Fi driver tries to initialize it before
the actual partition is initialized); and 3) enables reconnecting
using `wapi reconnect` command and connect the device automatically
on bringup if `CONFIG_NETUTILS_NETINIT` is selected.
- putreg32() is used the wrong way around (reg, val) instead of (val, reg)
- MPFS_SPI_FRAMESIZE is not a register, FSIZE is the name
- Clear all interrupts _before_ writing the FIFO, this prevents a race
condition where a short transmission completes before the interrupt is
enabled.
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization
Signed-off-by: hujun5 <hujun5@xiaomi.com>
1. Get the value of sp from dump regs when an exception occurs,
to avoid getting the value of fp from up_getsp and causing
incomplete stack printing.
2. Determine which stack the value belongs to based on the value
of SP to avoid false reports of stack overflow
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
- Fix DMA addressing issues within litex_sendsetup/litex_recvsetup
- Extend with handling specific to eMMC commands during init & use.
- Cleanup of 4-bit BUS handling for SD and eMMC
- For eMMC, Send CMD0 during init as per JEDEC v4.41 for pre-idle
Store the old environment in a local context so another temporary address
environment can be selected. This can happen especially when a process
is being loaded (the new process's mappings are temporarily instantiated)
and and interrupt occurs.
- Remove the temporary "saved" variable when temporarily changing MMU
mappings to access another process's memory. The fact that it has an
address environment is enough to make the choice
- Restore nxflat_addrenv_restore-macro. It was accidentally lost when
the address environment handling was re-factored.
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
perf interface related code.
- Support for pmu init under smp.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
However, this fix works as a tentative solution.
Impact:
- K210 on QEMU only
Tested
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This has been a long issue for me as it results in random crashes when
asynchronous events occur when the idle process is active.
The problem is that the kernel cannot access user memory, because the CPU
status prevents it.
Current Toolchain.defs set the compile flags directly, it's OK for
target specified gcc toolchain.
But some LLVM based toolchains (Rust/Zig etc) use single toolchain to handle all supported paltform.
In this patch, arch level Toolchain.defs export standard LLVM style arch flags, and let <Lang>.defs to map them into internal style,
This will simplify the intergration of non-c language.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
* Remove the 'COEXISTENCE' suffix from Wi-Fi's STA + SoftAP mode.
Coexistence usually refers to Wi-Fi + BLE, instead of Wi-Fi's
operation mode;
* Remove commented debug code;
* Remove outdate function descriptions;
Initially supporting ESP32-C3 chip, to be followed by other RISC-V-based
chips from Espressif.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
If transfer is restarted in irq handler the interrupts shall be
cleared before the start bit is set in control register. This is
to avoid ints being accidentally cleared before they are handled leading
to timeout error.
In spi_irq handler the data is written into txfifo and transfer
is started before the TXDONE interrupt is cleared. If the bus/memory
access is in some cases delayed, the spi transfer may have been
finished already before the interrupt register is cleaned for the
transfer. This leads the early arrived interrupt to be just removed
and never handled, which would cause a timeout error.
This patch moves the clearing of the interrupt to the place before
the tx is started, so the interrupt is not missed in above cases.
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.
Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
Detach the address environment handling from the group structure to the
tcb. This is preparation to fix rare cases where the system (MMU) is left
without a valid page directory, e.g. when a process exits.
NuttX kernel should not use the syscall functions, especially after
enabling CONFIG_SCHED_INSTRUMENTATION_SYSCALL, all system functions
will be traced to backend, which will impact system performance.
Signed-off-by: chao an <anchao@xiaomi.com>
PWM driver for multiple peripherals supplied in gateware.
Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.
Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
This is preparation for moving address environments out of the group
structure into the tcb.
Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
This is fixed by making a stack frame to the user stack and copying it
there.
- If the signal handler uses a system call, the kernel stack was completely
and unconditionally destroyed, resulting in a crash in the user application
There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.
The CPU register always points to the faulting instruction so print it
out in the exception handler.
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.
- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.
In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.
Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
which is made by:
commit 87a1f69a3c
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date: Fri Dec 16 15:23:39 2022 -0300
Modify the IRQ APIs to be compatible with ESP32/S2/S3
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
before the OS finishes hardware initialization.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Summary:
- I noticed that mtimer stops around 30min after boot.
- Finally, I found that nesc overflows in riscv_mtimer_current().
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with rv-virt:nsh on QEMU-7.1
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
add the task from the specified task list to reduce time consuming.
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
delete the task from the specified task list to reduce time consuming.
After commit b7d2b38, the system suffers from -Warray-bounds warning with -Wall:
chip/mpfs_opensbi.c: In function 'mpfs_hart_to_scratch':
chip/mpfs_opensbi.c:251:26: warning: array subscript hartid is outside array bounds of 'sbi_scratch_holder_t[0]' {aka 'struct sbi_scratch_holder_s[]'} [-Warray-bounds]
251 | return (unsigned long)(&g_scratches[hartid].scratch);
Fix it by reverting back to what is was earlier. g_scratches shouldn't be in the bss
region that would be zeroed out.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
After the commit b8b541f, the system would not start up properly
with certain coldboot conditions. For example, if the OpenSBI picked
hart4 as the coldboot hart in preference to hart3, the system would
get stuck due to stack corruption. OpenSBI uses a lottery mechanism
to pick the coldboot hart.
Also fix g_scratches area in such a manner than it will not get
initialized to zero. If several harts initialize the area to zero, there's
danger the stack pointer gets wiped out.
Now any coldboot hart works.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
In the past, header file paths were generated by the incdir command
Now they are generated by concatenating environment variables
In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Currently the IHC (Inter Hart Communication) depends on OpenAMP and
rptun. However, the bootloader portion of the IHC doesn't need
either of them. Now they are wasting a lot of bootloader space.
Reorganize the bootloader portion into a separate file 'mpfs_ihc_sbi.c'.
This file contains the OpenSBI vendor extensions, or the only required
functionalities for the bootloader. On the other hand, 'mpfs_ihc.c'
contains the non-bootloader code.
This patch also makes it possible to utilize 2 RPMSG channels. This
has been tested so that 2 separate NuttXs on harts 1 and 2 communicate
with Linux kernel that runs on harts 3 and 4.
New configuration files are added as well:
- rpmsg-ch1: sample config for RPMSG
- rpmsg-ch2: sample config for another RPMSG channel
- rpmsg-sbi: sample bootloader config for RPMSG/OpenSBI
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This reverts commit ea9144bda8.
The commit made Icicle MPFS DDR useless. Revert the change for now.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Reduce "SPI Flash configuration" menu dependency on SPI Flash driver
just to MTD-related configs.
- Move SPI Flash Mode and Frequency configs to SPI Flash configuration
menu.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
to avoid misunderstanding the name
Impact:
- None
Testing:
- Tested with rv-virt:ksmp64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OS timer sometimes proceeds fast when
a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds SMP support for BUILD_KERNEL
Impact:
- RISC-V: BUILD_KERNEL + SMP only
Testing:
- Tested with rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.
NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.
For other SvXX architectures the boundary requirement (might be) is
different.
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
in riscv_percpu.c instead of using the global spinlock.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This allows properly using 10/100Mbps also with 1G phy. Some gigabit PHYs
come out of reset with 1G advertisement enabled, causing other devices to
set up link with 1G. If, after this, the link is set to 10/100 on the mpfs,
the link won't work.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.
Impact:
- qemu-rv only
Testing:
- Tested with rv-virt:knsh64 on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.
Impact:
- None
Testing:
- tested with rv-virt:knsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that the OpenSBI library depends on the BSD license
- This commit fixes this issue
Impact:
- CONFIG_OPENSBI=y only
Testing:
- Build with icicle:opensbi (will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Because a context switch issue still exists with FPU
the configs should be removed until it works.
Impact:
- None
Testing:
- Tested with ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
undeclare TCGETS on esp32c3 when enable usbserial and termios
error:
chip/esp32c3_usbserial.c: In function 'esp32c3_ioctl':
chip/esp32c3_usbserial.c:411:10: error: 'TCGETS' undeclared (first use in this function)
Situation:
Assume we have 2 cpus, and busy run task0.
CPU0 CPU1
task0 -> task1 task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
4.1 remove task2 form runninglist
4.2 take task0 as new tcb
4.3 add task2 to blocklist
4.4 use svc ISR swith to task0
4.5 crash
5. use svc ISR swith to task1
Fix:
Move clear spinlock to the end of svc ISR
Signed-off-by: ligd <liguiding1@xiaomi.com>
Simplify the clock mode from the board.h -files. Also make the
SD clock definable as well.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Some related products, such as Aries m100pfs, don't support eMMC
speeds up to 200MHz. Thus, provide option to select slower clock.
This has only to do with the clocking, no CMD6 is sent to select
high speed modes.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
The L3 mapping function was just way too simplistic. Depending on memory
configuration it either works or not.
Noticed that with icicle:pnsh the software crashes due to instruction
page fault, reason is the map_region() implementation that does not
work for regions that are not aligned to 2MB (the L2 page size).
Implemented an extremely simplistic page table allocator for the L3
references, that should once and for all get rid of the L3 mapping issue.
NOTE: gran_alloc() cannot be used at this point, it is too early for it.
If the system starts up using the SD-card, and later wants
to switch to use the eMMC, it's not going to happen. SD-card
will be kept selected within the FPGA making the transition
fail.
It's been possible to switch from eMMC to SD, but now the
transition is possible for both directions.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Issuing the following commands doesn't succeed:
- conn
- disconn
- conn
This USB driver doesn't even disconnect without this patch.
If the USB driver has been started from another hart, closing it
will not disable the PLIC interrupt. This means it's possible many
harts get the USB interrupt and thus make the USB look very unstable.
Fix these problems by disconnecting the USB via the USB_POWER
register at shutdown and disabling the interrupt at shutdown. Also
clear the software internals via the mpfs_sw_setup() for the conn /
disconect loop to succeed.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
The underlying hardware supports 9 endpoints:
- EP0
- 4x IN EPs
- 4x OUT EPs
Currently the driver assumes every EP number is unique. This limits
the amount of EPs to 1 + 4 = 5. Utilize the EPs in such a manner
that all may be used.
Also fix a few error handling related bugs. Update the composite
driver to match the current situation as well.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
==2117790==ERROR: AddressSanitizer: global-buffer-overflow on address 0x64d9e3c0 at pc 0x59ac4e16 bp 0xcefe8058 sp 0xcefe8048
READ of size 1 at 0x64d9e3c0 thread T0
#0 0x59ac4e15 in up_nputs sim/up_nputs.c:54
#1 0x59a67e4c in syslog_default_write syslog/syslog_channel.c:220
#2 0x59a67823 in syslog_default_write syslog/syslog_write.c:101
#3 0x59a67f10 in syslog_write syslog/syslog_write.c:153
#4 0x59a651c3 in syslogstream_flush syslog/syslog_stream.c:60
#5 0x59a6564e in syslogstream_addchar syslog/syslog_stream.c:104
#6 0x59a6576f in syslogstream_putc syslog/syslog_stream.c:140
#7 0x5989fc4d in vsprintf_internal stdio/lib_libvsprintf.c:952
#8 0x598a1298 in lib_vsprintf stdio/lib_libvsprintf.c:1379
#9 0x59a64ea4 in nx_vsyslog syslog/vsyslog.c:223
#10 0x598a601a in vsyslog syslog/lib_syslog.c:68
#11 0x59b0e3dc in AIOTJS::logPrintf(int, char const*, ...) src/ajs_log.cpp:45
#12 0x59b03d56 in jse_dump_obj src/jse/quickjs/jse_quickjs.cpp:569
#13 0x59b03ea1 in jse_dump_error1(JSContext*, unsigned long long) src/jse/quickjs/jse_quickjs.cpp:602
#14 0x59b03dd9 in jse_dump_error(JSContext*) src/jse/quickjs/jse_quickjs.cpp:591
#15 0x59bed615 in ferry::DomComponent::callHook(char const*) src/framework/dom/component.cpp:65
#16 0x59bfe0ff in ferry::DomComponent::initialize() src/framework/dom/component.cpp:645
#17 0x59bb141d in dom_create_component(JSContext*, unsigned long long, unsigned long long, unsigned long long) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x365c41d)
#18 0x59b4c0d3 in AIOTJS::__createComponent(JSContext*, unsigned long long, int, unsigned long long*) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x35f70d3)
#19 0x5a56ec17 in js_call_c_function quickjs/quickjs.c:16108
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Summary:
- I noticed that ps shows incorrect stack usage when running
getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
allocates its stack in the user space that needs to be
accessed with a correct address environment.
- This commit fixes this issue.
Impact:
- CONFIG_ARCH_ADDRENV=y only
Testing:
- Tested with rv-virt:knsh64 on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Current RISC-V/NuttX implementation assumes that text/data/heap
areas are continuous. In fact, CONFIG_ARCH_TEXT_VBASE and
CONFIG_ARCH_HEAP_VBASE are not used for memory allocation.
- This commit assigns dedicated virtual addresses for text and heap
which are the same approach to ARM-v7A/NuttX implementation.
Impact:
- None
Testing:
- Tested with rv-virt:knsh64 (will be updated later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
mpfs_write_tx_fifo() gets stuck in the following case:
- CDCACM is used
- ttyACM0 is opened and then closed from the remote end,
such as Linux or Windows
- data is written into ttyACM0 from NuttX
- tx fifo will never get empty and the system is stuck
Fix this by issuing an error code if the transmit fifo doesn't
proceed as expected. The error code is then propagated into
higher level keeping the system functional.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
nxsig_usleep() will wait for the next timer tick which is way
too much here. It's not sleeping 100 us, but rather, near 1/60 s.
This causes severe performance problems. Fix this by polling the
register for a while if the remote end is busy.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Clarify the macros MSSIO_EC_DEFAULT and MSSIO_EC_USB_DEFAULT
- Remove PULLDOWN bit from MSSIO_EC_DEFAULT, it was on by accident
- Fix some EC configuration macros; DRVSTR was wrong, clean up the others
- Define GPIO_PULLUP and GPIO_PULLDOWN like on many other platforms
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Since the commit cf22dd8 (related to OpenAMP update), the notifyid
is no longer NOTIFY_ALL, but the vq id.
Utilize the vq id now properly as it's being provided. However,
vq id 0 generates action.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
without UBSan
```
text data bss dec hex filename
85612 208 142258 228078 37aee nuttx
```
with UBSan:
```
text data bss dec hex filename
194290 98164 208634 501088 7a560 nuttx
```
```c
int main(int argc, FAR char *argv[])
{
uint32_t ptr[32];
printf("Hello, World!! %lu\n", ptr[64]);
return 0;
}
```
Try to run this sample:
```
nsh> hello
ubsan_prologue: ================================================================================
ubsan_prologue: UBSAN: array-index-out-of-bounds in hello_main.c:39:37
__ubsan_handle_out_of_bounds: index 64 is out of range for type 'uint32_t [32]'
ubsan_epilogue: ================================================================================
Hello, World!! 1070182368
nsh>
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
OpenSBI vendor extension calls must not cause scheduling, as they're
part of M-mode trap handling. Thus, comment out nxsig_usleep() as
well, which is occasionally taken and crashes the system in that
case. Fix this by commenting out lines that have the potential to
cause scheduling.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- I noticed that QEMU shows high CPU usage if the number of
CPUs does not match the kernel configuration. (e.g. -smp 8
and CONFIG_SMP_NCPUS=2)
- This commit fixes this issue.
Impact:
- qemu-rv only
Testing:
- Tested with the following configs
- rv-virt:smp64 (CONFIG_NCPUS=1/2/8)
- rv-virt:nsh64
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It is not really needed; g_hart_stacks is only used during SBI init as
a temporary stack area. We can use the scratch area buffers for this, as
the scratch areas define almost 4K of extra space, which is used for
exception stacks anyway.
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:
1. Composite USB driver was used (CDC/ACM + Mass storage)
2. /dev/ttyACM0 was accessed instantly from Linux side when
starting up.
3. Training data was sent to /dev/ttyACM0 from NuttX from the
very beginning periodically.
It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.
Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
