Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Execute data and instruction sync barriers after writing MPU register,
to ensure MPU setting take effects that the new changes are seen.
testing in lm3s6965-ek:qemu-protected
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
CC: unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
# if NR_IRQS <= 256
^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
CC: mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Pass CP15_CACHE_INVALIDATE argument with r1 register to cp15_dcache_op_level.
cache level is 0(L1 D-Cache) with r0 register.
prototype:
void cp15_dcache_op_level(uint32_t level, int op)
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
argument to macro is empty
SP_DSB();
^
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"
So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:
CC: common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
isb 15
------^
[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
isb 15
------^
[asarm] (error) errors during processing
According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.
In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
The following are the compile error that reported
by GreenHills compiler:
"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 156 (col. 17): error #2036-D:
cannot allocate "reg0" to specified caller-saved register
"/mnt/yang/qixinwei_commit/nuttx/include/arch/syscall.h", line 157 (col. 17): error #2036-D:
cannot allocate "reg1" to specified caller-saved register
Then we fix this greenhills compilation error by explicitly specifying
the registers in the clobber list in the inline assembly code.
This fix is successful in compiling on the
nuttx/boards/arm/mps/mps2-an500/configs/nsh platform and passes
the ostest test.
However, if we keep the implementation the same for both the default
and Greenhills compilers, the default compiler will report the
following two issues:
1. the "sys_call6" function will report compile error when
compiling on "./vendor/qemu/boards/smartspeaker/configs/smartspeaker-knsh"
platform, the detailed error info:
CC: proxies/PROXY_mq_getattr.c In file included from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/sys/syscall.h:35,
from /home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/syscall.h:30,
from proxies/PROXY_mmap.c:5:
In function 'sys_call6',
inlined from 'mmap' at proxies/PROXY_mmap.c:9:22:
/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/syscall.h:297:3: error: 'asm' operand has impossible constraints
297 | __asm__ __volatile__
| ^~~~~~~
2. when running on qemu-armv7-a platform, the modification to
"smh_call()" function will make the system fail to boot up, so
we need to keep the default compiler implementation and greenhills
compiler implementation separate
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
(cherry picked from commit cb48b749b1c9cad8cfb96bff7c5e9b6ebf20fc8a)
This adds the necessary defines to set the USARTs' kernel clock source
selection.
This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.
This is according to the reference manual RM0399 page 448.
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
The following warnings is fixed:
chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
961 | uint32_t regval;
chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
2264 | int rv;
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.
The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Following warnings were caused by incorrect naming of few defines.
chip/sam_mcan.c:415:7: warning: "MCAN1_NTSEG1" is not defined, evaluates to 0 [-Wundef]
415 | # if MCAN1_NTSEG1 > 63
| ^~~~~~~~~~~~
chip/sam_mcan.c:418:7: warning: "MCAN1_NTSEG2" is not defined, evaluates to 0 [-Wundef]
418 | # if MCAN1_NTSEG2 > 15
| ^~~~~~~~~~~~
chip/sam_mcan.c:421:7: warning: "MCAN1_NSJW" is not defined, evaluates to 0 [-Wundef]
421 | # if MCAN1_NSJW > 15
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
During the boot phase, when we transition from tee smp to ap smp, we can use a busy waitflag to wait for the completion of the initialization of ap's core0
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be restored
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
cpu0 cpu1:
user_main
signest_test
sched_unlock
nxsched_merge_pending
nxsched_add_readytorun
up_cpu_pause
arm_sigdeliver
enter_critical_section
Reason:
In the SMP, cpu0 is already in the critical section and waiting for cpu1 to enter the suspended state.
However, when cpu1 executes arm_sigdeliver, it is in the irq-disabled state but not in the critical section.
At this point, cpu1 is unable to respond to interrupts and
is continuously attempting to enter the critical section, resulting in a deadlock.
Resolve:
adjust the logic, do not entering the critical section when interrupt-disabled.
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
we can use g_cpu_lockset to determine whether we are currently in the scheduling lock,
and all accesses and modifications to g_cpu_lockset, g_cpu_irqlock, g_cpu_irqset
are in the critical section, so we can directly operate on it.
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
- In some cases, an operational Ethernet MAC may have no PHY, for example
when the system has a direct RMII MAC-to-MAC link.
- New config option STM32H7_NO_PHY
- With this option, PHY-specific code in the ethernet driver is not built
- This option is inherently incompatible with autonegotiation and speed and
duplex settings must be compiled in
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
This support may be extended to gdc (gnu) if nuttx developers demand it
or are interested in it.
Add the address alignment to keep the constraint of ARMv7-M architecture same as RAM vector.
ARMv7-M architecture describes the vector table address alignment as following.
The Vector table must be naturally aligned to a power of two
whose alignment value is greater than or equal to (Number of Exceptions supported x 4),
with a minimum alignment of 128 bytes.
I wonder why the implementation of arm_vectors.c does not follow
this constraint of address alignment about ARMv7-M architecture.
Although RAM vector is taken care about it.
I think, as the result it was done by linker script on each board.
At our system, NuttX will be started by bootloader.
To fix the address of entry point(__start) I set the address of entry point to beginning of binary,
so the beginning of binary is not a vector table.
At this case, keeping the address alignment constraint of arm_vectors.c is needed.
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Embedded flash can have user signature area on SAMv7. This is a 512
bytes large page whose data are not erased by asserting ERASE pin or by
software ERASE command.
This commit adds arch to board interface for this area. It is possible
to perform read, write and erase operation. SAMV7_USER_SIGNATURE option
has to be set in the configuration.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
By default U(S)ART clocks are enabled in sam_lowput.c but
configuration check from sam_config.h may override USART configuration
and prevent clocks from been enabled.
This commit fix inconsistency in U(S)ART pinmux and clock configuration
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Make channels synchronous (i.e. share the same timebase) with the help
of SAMV7_PWMx_CHy_SYNC defines. All the channels share the same
timebase of channel 0, so this channel must be defined too.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
With CONFIG_MMCSD_MULTIBLOCK_LIMIT not set. (No limit)
The DMA driver would overwrite the internal buffer.
By adding CONFIG_ARCH_HAVE_SDIO_PREFLIGHT and
CONFIG_FAT_DMAMEMORY we can insure alignment and
maximize performance using no CONFIG_MMCSD_MULTIBLOCK_LIMIT
Option CONFIG_SENSORS_QENCODER might be configured even if SAMv7 qencoder
over timer counter is not used (for example encoder over GPIO is selected
with CONFIG_SAMV7_GPIO_ENC). This can cause compile warnings, also build
of sam_qencoder.c file is unnecessary in that case.
New hidden option CONFIG_SAMV7_QENCODER is added and automatically
selected if at least one timer counter is enabled for qencoder. Build
is triggered on this option.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PWMx_CHy_LONLY options have been added to Kconfig, too.
If LONLY is selected, it's not possible to use complementary outputs.
If LONLY is not selected, it's possible to use H or complementary
output. If configured correctly with cpol and dcpol attributes,
a H-like behaviour can be achieved. May be useful when you run out
of free MCU pins.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
according to manual:
The FPU is not affected by any security configuration.
Thus, it appears as not present in PERIPHID[n].PERM
register located in the SPU
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.
flat and protected mode should be the same as before.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The SAMV7's qencoder driver now supports the GETINDEX ioctl call
which does not reset the internal Timer/Counter and returns
the current position, position of the last index and the number
of captured indexes to a struct qe_index_s pointer. Because the
SAMV7's timers are 16bit, the extension to 32 bits must be done.
Select CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX in the Kconfig to
enable this functionality.
This driver does not obey the instructions given in the ATSAMV7
2023 datasheet because the recommended trigger resets the internal
counter which is not desired. Instead, a capture into capture A
and capture B registers is used. This way if an event happens
(the rising edge of the index signal), the current counter's value
is captured.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
According to the qemu source code, hw/arm/virt.c.
The secure memory of the ARM Virt board is [0xe000000~0xf000000]
and the non-secure memory is configured as [0x40000000~0xffffffff].
We made the following adjustments based on the above virt board configuration
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module
Signed-off-by: W-M-R <mike_0528@163.com>
1.
In file included from chip/stm32_rtc.c:31:
chip/stm32_rtc.c: In function 'rtchw_set_alrmar':
chip/stm32_rtc.c:761:11: warning: format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'uint32_t' {aka 'volatile long unsigned int'} [-Wformat=]
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ^~~~~~~~~~~~~~~~~~
chip/stm32_rtc.c:761:25: note: format string is defined here
761 | rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
| ~~~^
| |
| unsigned int
| %08lx
2.
arm-none-eabi-ld: staging/libdrivers.a(userled_lower.o): in function `userled_setled':
drivers/leds/userled_lower.c💯 undefined reference to `board_userled'
Regression:
stm32h7/linum-stm32h753bi: add support to leds
Signed-off-by: chao an <anchao@lixiang.com>
adjust link options for userspace elf
specify system libs and apps lib to only link with nuttx target in flat build mode
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
This fixes build error (Werror):
Error: chip/stm32_foc.c:1918:12: error: 'stm32_foc_info_get' defined but not used [-Werror=unused-function]
1918 | static int stm32_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
When entering the function from an external bootloader, the CPU could be using PSP. But the following
code expects MSP to be in use.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
We can decide whether use trustzone
After this patch, we can support the following mode:
ARCH_HAVE_TRUSTZONE ARCH_TRUSTZONE_DISABLED ARCH_TRUSTZONE_SECURE ARCH_TRUSTZONE_NONSECURE
Without Security Extensions n n n n
CHIP have NO trustzone
With Security Extensions y y n n
Only one bin in sec mode
With Security Extensions y n y n
TEE bin in sec mode
With Security Extensions y n n y
REE bin in non-sec mode
Signed-off-by: ligd <liguiding1@xiaomi.com>
Purpose: make the the os crash when busyloop with interrupt disable
Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;
Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
watchdog IRQ to FIQ, so the watchdog can trigger even with the
interrupt disabled (up_irq_save() called);
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
Some stm32 has alternate USART6 pinout on G9/G14 but others have it
on A12/A11. Unfortunately it's very difficult to make proper ifdefs for
this since position is based on package (and pincount) and not chip
itself. Creating such list would take a lot of time. Because of that
I just added another possible config for this pin and moved responsibility
of proper selection onto board code.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Onewire driver wants to use "struct up_dev_s *priv", which is extracted
from "struct uart_dev_s" and "struct inode". But inode and uart dev are
only declared when TERMIOS or BSDCOMPAT is also enabled. Without these
driver fails to compile with missing declaration errors. Adding some
additional "#if defined()" to these declarations fix the issue and driver
compiles and works properly (tested with ds18b20 temp sensor).
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Reproduce:
configure:
./tools/configure.sh qemu-armv7a:nsh -j8
open kasan:
CONFIG_MM_KASAN=y
run:
qemu-system-arm -cpu cortex-a7 -nographic -machine virt,virtualization=off,gic-version=2 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
error:
run hanged
Rootcause:
In Qemu armv7a, the ram-end reserved for MMU PGTABLE:
And the up_allocate_heap() directly use the ram-end for heap in arch/arm/src/common/arm_allocateheap.c
*heap_size = CONFIG_RAM_END - g_idle_topstack;
Then they are conflict.
Usually, we won't use the heap end, so can't find the error.
BUT, the KASAN will use the heap end for shadow, so found the error.
Resolve:
up_allocate_heap() consider of MMU, re-define the RAM_END at chip.h
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit adds support for TX DMA transfers for USART peripheral. Code
refactor in sam_serial.h was also required in order to have correct
defines for all possible cases (both RX and TX DMA used, just one used,
none used).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
