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19314 Commits

Author SHA1 Message Date
Xiang Xiao
2dbf826c19 config: It's enough to let LTO_FULL depend on ARCH_TOOLCHAIN_GNU only 
since ARCH_TOOLCHAIN_CLANG automatically select ARCH_TOOLCHAIN_GNU

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-28 11:25:00 +09:00
Gustavo Henrique Nihei
ffab2dc628 risc-v: Restrict Fence instruction for chips that support S-mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
chao.an
042640abbf arch/arm: add support for GCC LTO 
1. Enable GCC link-time optimizer
2. Enable use of a linker plugin during link-time optimization

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:54 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation 
It will just become an empty object if FPU support is not included.
 2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
98d8d2a1ff arch/xtensa: Group all the macros in one file. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
Abdelatif Guettouche
541eabb535 xtensa_int_handlers.S: Refactor the calls to ps_setup. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
chao.an
db54b0b836 arm/assert: fix build warning on clang 
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
             stack, ptr[0], ptr[1], ptr[2], ptr[3],
             ^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
   __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
                                      ~~~~~~              ^~~~~~~~~~~

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 14:18:42 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-26 11:34:28 +03:00
Abdelatif Guettouche
aaa5316235 arch/xtensa: Simply use xtensa_createstack for CPU1 idle task. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-26 01:36:54 +08:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork 
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
 2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:23:03 +03:00
Xiang Xiao
e9f5eb0823 boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:22:46 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use 
FPU registers need to be written prior to updating CSR_STATUS
 2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 07:57:29 +03:00
Abdelatif Guettouche
3942f4d133 arch/xtensa: No need to save SP in EXCSAVE_1 when linking the interrupt 
frame with the previous frame.  The SP is already saved in A12.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
f130d8c143 xtensa_user_handler.S: Fix backtrace. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
7a3ad4b224 xtensa_user_handler.S: Use the ps_setup macro when dealing with an 
exception.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize 
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU 
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210 
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP 
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS 
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
Abdelatif Guettouche
56ecd44f63 arch/xtensa: Color the other CPUs task when they are created. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-22 01:12:55 +08:00
Xiang Xiao
1320e5add4 arch/arm: Move the duplicated assembly code to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Xiang Xiao
ebf1093cff arch/arm: Switch the context of save and restore from assembler to c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 15:26:05 +08:00
chao.an
875c5dac75 arm/armv[7|8]m: compare of hardware fp registers should skip REG_FP_RESERVED 
Fix fpu test break

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 14:55:54 +09:00
Abdelatif Guettouche
64e4c9ca02 arch/xtensa: Move xtensa_save_context to up_saveusercontext for 
consistency with other archs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
Abdelatif Guettouche
6db910a1aa arch/xtensa: Use syscall interface for xtensa_save/restore_context. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
chao.an
0315283c21 arch/clang: add support for Clang LTO 
add support of Clang's Link Time Optimization (LTO) on NuttX build system

Reference:
https://gcc.gnu.org/onlinedocs/gccint/LTO-Overview.html
https://llvm.org/docs/LinkTimeOptimization.html

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
chao.an
67fbfda974 arch/armv6-m: add support of LLVM Clang 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 16:08:17 +03:00
Alin Jerpelea
dda675779a arch: arm: mor1kx: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
af98967439 arch: arm: stm32l4: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
73cd86dad7 arch: arm: phy62xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
22ceda26bb arch: arm: lpc43xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
4e19a97916 arch: arm: imxrt: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
208b892efe arch: arm: cxd56xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Huang Qi
95ab7b973b arch/sparc,xtensa: Control output by $(Q) as other arch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 12:04:17 +02:00
zhuyanlin
8d756a75a2 armv7/r:cp15_cache_all: fix error in LineSize 'r5' mask 
r5 = r3 & r1

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-20 08:06:58 +09:00
chao.an
fc3565e9eb arch/z80: Unify the toolchain definition of SDCC for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
0cf8088406 arch/misoc: Unify the toolchain definition of GNU for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2df591b3bb arch/armv7-a/r: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
4a085e1cdb arch/arm/armv6-m: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2246afcdd8 arch/armv7-m: Unify the toolchain definition of eabi/clang/iar for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
a79bf8c9eb arch/armv8-m: Unify the toolchain definition of eabi/clang for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
Ville Juven
5c951d8c4a arm/arm_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
chao.an
b110c984b1 arch/armv7-[a|r]: correct the handing of group env switch 
This PR resolved 2 issues:
1. CURRENT_REGS is not set correctly on swint handling
2. group env is not changed properly

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 12:10:25 +03:00
Xiang Xiao
96fa8be5f5 arch/armv[7|8]-m: Compare all FPU registers in up_fpucmp 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
d80c2d7419 arch/arm: Remove all lazy fpu related code 
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 14 18:07:14 2022 +0800

    arm/armv7-[a|r]: move fpu save/restore to assembly handler

    Save/Restore FPU registers in C environment is dangerous practive,
    which cannot guarantee the compiler won't generate the assembly code
    with float point registers, especially in interrupt handling

    Signed-off-by: chao.an <anchao@xiaomi.com>

commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 7 13:48:04 2022 +0800

    arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only

    Signed-off-by: chao.an <anchao@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
7c5b2e3305 arch/arm: Remove FAR and CODE from common/ and arm*/ folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:23:59 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:22:45 +03:00
Xiang Xiao
84b0453ef3 arch/arm: Remove unneeded group_addrenv call which handled by arm_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 22:18:32 +03:00
Xiang Xiao
2e7b10356f arch/sparc: Remove unneeded group_addrenv call which handled by up_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
d28892e454 arch/xtensa: Remove unneeded group_addrenv call which handled by xtensa_irq_dispatch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
ef62e1c970 arch/misoc: Remove unneeded group_addrenv call which handled by [lm32|minerva]_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
9fad9ed66b arch/mips: Remove unneeded group_addrenv call which handled by mips_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch 
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
bdbbdbe242 arm/a1x: fix compile break 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 10:02:17 +08:00
Xiang Xiao
ef1a98dd00 Remove the unneeded void cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
32ee2ae407 Remove the unneeded worker_t cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
373363d750 arch/arm: Move arm_signal_dispatch.c to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:30:41 +03:00
wangbowen6
91d02f5db8 arm/arch: using __builtin_frame_address(0) implement up_getsp(). 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-18 00:49:15 +08:00
Xiang Xiao
6af167c086 arch/sparc: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
977fa987e2 arch/mips: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
1ce592e8b5 arch/misoc: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
3c82094156 arch/or1k: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
0bd9a66305 arch/x86_64: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
af00e016e9 arch/sim: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
e923875c1b arch/ceva: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
6bc61b5752 arch/xtensa: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$) 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
chao.an
aed21ba0bc arch/armv[7|8]m: enhance the clang support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
okayserh
3a015d56b0 Fixed a compile error, presumably caused by C&P error. 2022-04-16 19:21:10 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif. 
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-15 19:41:31 +08:00
Petro Karashchenko
09b3fb25ab drivers: remove unimplemented open/close/ioctl interfaces 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-15 16:56:25 +08:00
Richard Tucker
1b13d1b440 arch/arm/src/sam34/Kconfig: fix typo in device name 2022-04-15 02:22:01 +08:00
Richard Tucker
de66e18d6f arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup 2022-04-15 02:22:01 +08:00
Richard Tucker
929556d750 arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips 2022-04-15 02:22:01 +08:00
Richard Tucker
be0bcac91b arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required 2022-04-15 02:22:01 +08:00
Richard Tucker
bc7f4b2375 arch/arm/src/sam34/sam_hsmci.c: delay required after sending command 2022-04-15 02:22:01 +08:00
chao.an
dc961baaea arm/armv7-[a|r]: move fpu save/restore to assembly handler 
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 22:33:10 +08:00
Alan C. Assis
c232be541c Add SPIRAM to ESP32-S2 2022-04-14 22:10:23 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
Xiang Xiao
a94b7b9cca arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 16:35:52 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task 
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
chao.an
0c79ad9d8d arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_* 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use 
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
 2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic 
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
 2022-04-14 16:43:34 +08:00
Abdelatif Guettouche
a5c64adbe4 arch/Kconfig: Move the DUMP_ON_EXIT option out of the Bring-up group. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit. 
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT 
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do 
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
 2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address 
MTIMECMP0 was incorrect
 2022-04-13 21:56:21 +08:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler 
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register 
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default 
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp 
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
 2022-04-12 21:33:19 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break 
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
Lingao Meng
a56199c7dd sim: bt: Add specific bluetooth HCI number id 
Add option for attached the local bluetooth device use
specific bluetooth HCI number id.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
 2022-04-12 15:15:25 +08:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver 
Add critical section to scu one-shot sequencer.
 2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning 
Add necessary include header named debug.h for using ferr and
finfo.
 2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20585
 2022-04-12 07:55:00 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-11 10:59:18 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception 
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core 
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t 
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Xiang Xiao
c235c0fa43 boards/lx_cpu: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
1f7b49d700 boards/nucleo-h743zi2: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Huang Qi
c6942b68d5 arch/risc-v: Add handler for misaligned load/store 
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 23:27:07 +08:00
chao.an
8d66dbc068 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-08 14:28:41 +09:00
Huang Qi
b6cf1ac662 arch/riscv: Minor style change and text correction 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 01:07:06 +08:00
Huang Qi
4ebc581c73 esp32c3: Simplify irq dispatch logic 
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-07 18:16:35 +02:00
Ville Juven
d38b4965f8 MPFS: Prepare support for S-mode 
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
 2022-04-07 21:55:36 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-07 11:25:12 +03:00
Jiuzhu Dong
d87cf8d4ca fs/poll: change format for type pollevent_t 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-07 12:14:06 +08:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception 
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-06 22:48:46 +08:00
yinshengkai
db012687f9 arch/sim: support simulator keyboard devices 2022-04-06 15:26:57 +03:00
Alan C. Assis
1090e1a8ea xtensa/esp32: Add support to TWAI/CANBus controller 2022-04-06 15:09:46 +03:00
zhuyanlin
6a761ff087 arch:tcbinfo: update tcbinfo as xcpcontext update 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-05 13:33:00 +02:00
Ville Juven
6c22e2894c RISC-V: Fix usage of static_assert in riscv_percpu.c 
There is no alias for struct riscv_percu_s
 2022-04-04 22:44:25 +08:00
Ville Juven
7db356e720 RISC-V: Fix file name of riscv_dispatch_syscall 2022-04-04 22:44:18 +08:00
Petro Karashchenko
d08fbca679 nuttx: unify FAR attribute usage across the code 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-04 21:32:58 +08:00
Abdelatif Guettouche
f527abc324 arch/xtensa: Build the xtensa_tcbinfo.c file for S2 and S3. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-04 21:25:47 +08:00
Xiang Xiao
bf48c6d4a8 arch/riscv: Rename SCRATCH_HARTID_OFFSET to RISCV_PERCPU_HARTID_OFFSET 
and fix the typo error

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-04 08:22:08 +03:00
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-04 12:05:53 +08:00
Michael Jung
e3926ecb16 stm32u5: stm32_stdclockconfig fixes 
Fix stm32_stdclockconfig for stm32u585xx to the extend that the
B-U585I-IOT02A board's clock tree can be configured.  This board uses
the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.
 2022-04-03 23:20:03 +03:00
zhanghongyu
451c53daa4 usrsock: Move event field to usrsock_message_common_s 
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
 2022-04-03 11:38:50 +09:00
wangbowen6
bcb2530b18 arm/chip: add backtrace support for all chips that support thumb instruction set. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-03 00:22:57 +08:00
raiden00pl
b487101b87 stm32: add support for up_perf 2022-04-02 10:34:35 -03:00
Xiang Xiao
27c80f2586 arch/riscv: Rename g_scratch to g_percpu 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Xiang Xiao
e959775397 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Xiang Xiao
be2fee7d6e arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S 
since macro defined in this file is also used in the normal context

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Xiang Xiao
79aca28bd7 arch/riscv: Remove riscv_sbi.c since it doesn't exist 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Xiang Xiao
629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall 
follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Xiang Xiao
7a209e6ee8 arch/riscv: Align the macro definition in csr.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-02 14:08:37 +03:00
Abdelatif Guettouche
11807abd4e arch/xtensa: Add xtensa_tcbinfo struct that contains helpful offsets. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-02 10:39:14 +08:00
Ville Juven
71ced1f1a9 RISC-V: Implement skeleton for a per CPU structure 
It might be useful to store things in memory per CPU. The tricky part
is that all CPUs run the same code and see the same memory, so some
kind of centralized access is required.

For now, the structure contains the hart id.

Access to the structure elements is provided via sscratch, which is
unique for every hart!
 2022-04-01 16:19:42 -03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode) 
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
 2022-04-01 16:19:42 -03:00
Gustavo Henrique Nihei
c37474b5bd risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-01 15:29:14 -03:00
Gustavo Henrique Nihei
35009c5d4d sim: Fix init of static C++ constructors when using glibc >= 2.34 
glibc 2.34 changed the dynamic linker behavior during the startup
process, which makes the previous "__init_array_start" replacement trick
non-effective.
Now the dynamic linker parses the constructors/destructors information
from the DYNAMIC segment of the program.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-01 23:10:53 +08:00
chao.an
253562f11f arch/xtensa: add syscall note support in the flat build 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-01 21:04:51 +08:00
Jiuzhu Dong
0a111b7c96 fs/rpmsgfs: fix bug about using uninit variable "times" 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-01 21:02:08 +08:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-01 10:31:24 +08:00
Ville Juven
e6d6734db2 ARCH_ADDRENV: Add guard against mis-configuration 
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.

Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
 2022-04-01 02:02:10 +08:00
Petro Karashchenko
44ee76dcbd arch/risc-v: fix ARCH_RV32 offset for the stub lookup table calculation 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-31 19:34:52 +08:00
Huang Qi
264e39e121 arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
f72ca3db5c arch/risc-v: Dont' disable/enable irq in riscv_doirq 
Since these codes added to all chips but not fully tested,
so we should changd this behavior.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
a6c22b722f arch/risc-v: Remove deprecated logic from riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
692ffb60b4 arch/risc-v: Rename up_doirq to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 19:33:08 +08:00
Huang Qi
814c07c792 arch/risc-v: Store/Restore FPU register in exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-31 11:49:36 +08:00
Huang Qi
379639a371 arch/risc-v/mpfs: Remove duplicated riscv_restorefpu 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-30 13:15:35 +03:00
Gustavo Henrique Nihei
e1f28c19c2 arch/arm: Make CXX exception and RTTI depend on Kconfig options 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
06d0a9f1ad xtensa|risc-v: Make CXX exception and RTTI depend on Kconfig options 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
c7311829e0 xtensa: Build OS-assisted atomic operations on ESP32-S2 
ESP32-S2 lacks support for conditional load/store instructions.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
7926bce26b xtensa: Move XCHAL_SWINT_CALL definition into syscall header 
This is required to avoid the interface header (syscall.h) depending on
the xtensa_swi.h header from the implementation

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-30 11:19:29 +08:00
Lee Lup Yuen
4456b13c19 riscv/bl602: Remove check for LCD driver 
## Summary

`bl602_spi_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.

This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.

More details: https://github.com/apache/incubator-nuttx/pull/5898

## Impact

This change impacts LCD drivers that call `SPI_CMDDATA()`.

Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.

After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.

## Testing

We tested with LVGL and ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-30)
 2022-03-29 23:09:42 -03:00
chao.an
a98a599cb9 arm/cortex-[a|r]: IRQ Switch return should with shadow SPSR 
The SPSR is used to store the current value of the CPSR when an exception
is taken so that it can be restored after handling the exception.
Each exception handling mode can access its own SPSR.

User mode and System mode do not have an SPSR because they are not
exception handling modes.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-30 08:12:26 +09:00
Richard Tucker
6d8cd4ec92 arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver 
See the following for details on the pepheral:
https://github.com/enjoy-digital/litesdcard
 2022-03-30 02:35:27 +08:00
Richard Tucker
d557b87b25 arch/risc-v/litex: add cache_invalidate 2022-03-30 02:35:27 +08:00
Lee Lup Yuen
4f885fe6bf riscv/bl602: Implement SPI Cmd/Data 
## Summary

To control the Data/Command Pin on ST7789 SPI Display, the SPI Driver flips the MISO Pin as though it was a GPIO.

To implement this on BL602, we reconfigure MISO from SPI Pin to GPIO Pin on the fly inside `bl602_spi_cmddata()`.

When the SPI Port is deselected (after the SPI operation), we revert MISO back from GPIO Pin to SPI Pin. We implement this inside `bl602_spi_select()`.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

## Impact

This change impacts 3 LCD drivers that call `SPI_CMDDATA()`: ST7735, ST7789, GC9A01.

Previously the BL602 SPI Driver would fail with "SPI cmddata not supported" when the above drivers are used.

After the change, the above drivers will set the LCD Data/Command Pin correctly.

## Testing

We tested this implementation of SPI Cmd/Data with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-   [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

We also tested LVGL with ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-29)
 2022-03-30 02:01:29 +08:00
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU 
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-30 01:33:04 +08:00
Huang Qi
20c511fcf1 arch/risc-v: Rename up_fpuconfig to riscv_fpuconfig 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-30 01:33:04 +08:00
ligd
ed8704d90e sim/rptun: rsc must set rpmsg_vdev.config_len 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-29 10:10:33 +08:00
zhuyanlin
d7391bf6bc xtensa: add xtensa arch oneshot ops 
As xtensa timer is common in all xtensa chips,
Use oneshot ops, implement a common xtensa oneshot timer.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-28 22:55:00 +08:00
ligd
0f02791ae6 armv8-m: add wake_func arm_should_generate_nonsecure_busfault 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-28 22:52:28 +08:00
ligd
60fc933261 armv8-m: make the securefault handled by non-securefult 
tee is secure cpu and ap is non-secure cpu.
The crash PC can get by IP (R12).

[ EMERG] [tee] arm_hardfault: Hard Fault escalation:
[ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault:
[ EMERG] [tee] arm_securefault:         IRQ: 3 regs: 0x2400ff00
[ EMERG] [tee] arm_securefault:         BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c
[ EMERG] [tee] arm_securefault:         CFSR: 00000000 HFSR: 40000000 DFSR: 00000000
[ EMERG] [tee] arm_securefault:         BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0
[ EMERG] [tee] arm_securefault: Secure Fault Reason:
[ EMERG] [tee] arm_securefault:         Attribution unit violation
[ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678
[ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault:
[ EMERG] [ap] arm_busfault:     IRQ: 5 regs: 0x3c475608
[ EMERG] [ap] arm_busfault:     BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004
[ EMERG] [ap] arm_busfault:     CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000
[ EMERG] [ap] arm_busfault: Bus Fault Reason:
[ EMERG] [ap] arm_busfault:     Instruction bus error
[ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main
[ EMERG] [ap] backtrace:
[ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168
[ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60
[ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324
[ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10
[ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c
[ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c
[ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c
[ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac
[ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4
[ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74
[ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8
[ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54
[ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48
[ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c
[ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34
[ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8
[ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98  R3: 00000000
[ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000  FP: 3c476aac
[ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c
[ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4  PC: 00000000
[ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004
[ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8
[ EMERG] [ap] arm_dump_stack: IRQ Stack:
[ EMERG] [ap] arm_dump_stack: sp:     3c41c900

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-28 22:52:28 +08:00
Ville Juven
43d5f60a74 MPFS: Fix issue with external interrupt detection 
The bitmask overflow'd. Failing test is at mpfs_irq_dispatch / line 69
 2022-03-28 22:40:11 +08:00
zhuyanlin
c0c0ffdf2f xtensa: add xtensa_spill_window declaration 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-28 12:33:07 +02:00
Huang Qi
ad1098d413 arch/armv7-a: Fix a typo in Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-28 12:42:43 +03:00
Xiang Xiao
3aaa7e8591 arch/sim: Remove "or 480" from Kconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-28 09:16:38 +03:00
Xiang Xiao
30e80f2394 arch/sim: Remove the unused SIM_TCNWAITERS from Kconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-28 09:16:38 +03:00
lishaoen
aa0c9fd788 nuttx: Add new config ARM_HAVE_MVE for MVE instruction 
Signed-off-by: lishaoen <lishaoen@xiaomi.com>
 2022-03-28 08:51:24 +03:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-28 13:41:57 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-28 13:41:57 +08:00
Lee Lup Yuen
c67272f9c8 riscv/bl602: Enable SPI Master in SPI Poll Send 
## Summary

SPI Poll Send `bl602_spi_poll_send()` doesn't send any SPI Data because it doesn't enable SPI Master and it doesn't clear the SPI FIFO. Also it hangs because it loops forever waiting for the FIFO.

We fix this problem by moving the code that enables SPI Master and clears the FIFO, from SPI Poll Exchange `bl602_spi_poll_exchange()` to SPI Poll Send. (Note that SPI Poll Exchange calls SPI Poll Send)

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Impact

This problem affects all NuttX Drivers that call `SPI_SEND()` on BL602, including the ST7789 Display Driver.

Previously `SPI_SEND()` didn't send any SPI Data and never returns, because it loops forever waiting to receive data.

Now `SPI_SEND()` sends data and returns correctly.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Testing

We tested the modified SPI Poll Send with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-  [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

We also tested LVGL with ST7789 on PineCone BL602:

-  [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for the modified SPI Poll Exchange, we tested with Semtech SX1262 SPI Transceiver on PineCone BL602:

-  [Testing SPI Poll Exchange](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-25)
 2022-03-28 13:32:27 +08:00
Xiang Xiao
8c8c60f70a arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-27 23:01:47 +03:00
ligd
e87d262c7f arch/Toolchain.defs: add wildcard for EXTRA_LIBS 
VELAPLATFO-1491

Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-03-27 22:53:58 +03:00
Xiang Xiao
a2e079fdd2 arch/arm: Change arm_arch.h to arm_internal.h in arm_perf.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-27 22:31:43 +03:00
Anthony Merlino
baeb2e9af7 stm32h7: Addresses tickless PR review comments 2022-03-28 00:33:26 +08:00
Anthony Merlino
896435e7c9 Fixes formatting 2022-03-28 00:33:26 +08:00
Anthony Merlino
c3745c8441 Adjust up_timer_getmask to handle 16-bit timers correctly. 2022-03-28 00:33:26 +08:00
Anthony Merlino
30f6dbc613 Throw compile time error if tickless timer is set to TIM6/TIM7 2022-03-28 00:33:26 +08:00
Anthony Merlino
95199f4790 stm32h7 timer: Clean up some bit operations to make them more readable. 2022-03-28 00:33:26 +08:00
Anthony Merlino
e5c8bb9b34 stm32h7: Fix a bunch of tickless issues. 2022-03-28 00:33:26 +08:00
Anthony Merlino
2fad06008a stm32h7: Adds tickless support. 2022-03-28 00:33:26 +08:00
ligd
f623ac0f13 armv7-m/armv8-m: move up_pref* api to common place 
Signed-off-by: ligd <liguiding1@xiaomi.com>
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-26 13:39:18 +02:00
Huang Qi
052c071867 arch/risc-v: Minor style change 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 16:52:13 +09:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-25 10:26:15 -03:00
Abdelatif Guettouche
914e9588bb esp32/Make.defs: Organise common arch files and chip files 
appropriately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-25 11:31:24 +08:00
Gustavo Henrique Nihei
c92c4af304 xtensa/esp32s2: Initialize instruction cache on startup 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 20:05:40 -03:00
Gustavo Henrique Nihei
bc071ec243 xtensa/esp32s2: Use functions defined in xtensa_counter for TimerISR 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 19:38:28 -03:00
Gustavo Henrique Nihei
04b80cc8d2 xtensa/esp32s2: Remove unused and not unsupported configs from Kconfig 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 19:38:28 -03:00
Ville Juven
44bec4cf8e RISC-V: Add missing code to dumpstate 
Just add the kernel stack dumping for completeness
 2022-03-24 00:15:28 +08:00
Ville Juven
77e90d9c87 RISC-V: Include support for kernel stack 
Preparation for CONFIG_BUILD_KERNEL=y, which requires that a kernel
stack is allocated for each user process.
 2022-03-24 00:15:28 +08:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-23 22:18:15 +08:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-23 19:30:04 +08:00
chao.an
7b73606300 arm/schedulesigaction: update the SP to signal context top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
chao.an
a770ff2017 arm/vfork: update the SP to stack top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Xiang Xiao
9ae0dcd4a2 arch/arm: Remove the code copy register from xcpt to stack 
since xcpt always point to the stack after the below change:
commit 7b9978883c
Author: chao.an <anchao@xiaomi.com>
Date:   Tue Mar 1 01:06:24 2022 +0800

    arch/arm: optimize context switch speed

    The current context save implementation saves registers of each task
    to xcp context, which is unnecessary because most of the arm registers are
    already saved in the task stack, this commit replace the xcp context with
    stack context to improve context switching performance and reduce the tcb
    space occupation of tcb instance.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Gustavo Henrique Nihei
024364ebbd xtensa/esp32s3: Add support for GPIO pin interrupts 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 07:23:51 +09:00
Gustavo Henrique Nihei
0e67dc8637 xtensa/esp32s3: Add support for GPIO read/write operations 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-23 07:23:51 +09:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 21:22:32 +08:00
Harri Luhtala
2ee12b2c5d arch/arm/src/stm32l4: peripheral voltage monitor support for vddio2 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2022-03-22 21:08:29 +08:00
Petro Karashchenko
757d01d915 progmem: eliminate PROGMEM_ERASESTATE configuration option 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 10:01:41 -03:00
Abdelatif Guettouche
10f8f6c9e3 xtensa/esp32(s2)_user.c: For EXCCAUSE values, use macros defined in xtensa_corebits.h 
instead of those defined in core.h as they are deprecated.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-22 10:20:27 +08:00
smartether
7fbadb5c16 fixed mpu9250 not work on i2c bus issue. 
1,set rp2040 FIFO_MAX_SIZE to 16.ref: pico sdk ->
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
 2022-03-21 12:07:03 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally 
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 17:41:33 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common 
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 17:38:18 +08:00
Petro Karashchenko
20ac85860c config: finalize transition from USER_ENTRYPOINT to INIT_ENTRYPOINT 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 11:32:47 +08:00
Abdelatif Guettouche
aa84559566 xtensa_coproc.S: Replace spaces by tabs. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 01:09:22 +02:00
Abdelatif Guettouche
ce8fae2842 xtensa_coproc.S: Adjust the save reserved for local variables when 
restoring/saving coprocessor state.

These function don't use call8 or call12 and thus need to create just 16
bytes for the base save area, however they do use one variable so we
need a space for that.  The `entry` instruction works in unit of 8 bytes
so we add whole 8 bytes for one variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 01:09:22 +02:00
Gustavo Henrique Nihei
9ae826e925 xtensa/esp32s3: Fix output handling for pins numbered from 32 to 48 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
f21a9f9578 xtensa/esp32s3: Enable UART pins to use IOMUX and bypass GPIO matrix 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
77944ceb42 xtensa/esp32s3: Clean up and improve GPIO driver interface 
Also fix an inconsistenct regarding the ESP32S3_NGPIOS macro. Although
correctly defining the number of available GPIOs in ESP32-S3, it was
erroneously being used for verifying the pin range.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
43b7d9b0da xtensa/esp32s3: Sync GPIO sigmap with IDF version 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-03-19 01:08:27 +02:00
Huang Qi
edef327655 arch/arm: Move ARCHCPUFLAGS to Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 02:24:00 +08:00
Petro Karashchenko
c1fb14ccaa boards/arm/samv7/same70-qmtech: add /dev/timer0 support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 02:21:03 +08:00
Abdelatif Guettouche
2793e6f82d xtensa_releasepending.c: Remove commented out code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-03-19 02:20:36 +08:00
Petro Karashchenko
6472a698b6 style/typo: fix few style and typo issues 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-18 17:05:10 +01:00