Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:
* New files, based on STM32G474RE reference manual, RM0440 Rev 4.
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:
* Remove all mentions of DMAMUX12 from comments. This family has
at most DMAMUX1 only.
* Add missing defines DMAMUX_CCR_SPOL_NONE,
DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
DMAMUX_CCR_SPOL_BOTH.
* DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
but datasheet shows bits 24-28 (5 bits).
* DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
shows (5 bits) 0x1f.
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
datasheet shows only 2 bits (0x3).
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
but datasheet shows 5 bits (0x1f).
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_spi.h:
* Avoid numerous ifdef on STM32 part numbers and make the
different variations of SPI peripheral features more
self-documenting: based on STM32_HAVE_IP_SPI_V* defines
from chip.h, define some or all of HAVE_SPI_I2S,
HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
which registers and bitfields to define based on them.
* Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
currently used only for STM32G47XX family MCUs, including
SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
SPI_I2SCFGR_ASTRTEN.
* SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
(xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(0 << SPI_I2SCFGR_I2SSTD_SHIFT).
* SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
(0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(1 << SPI_I2SCFGR_I2SSTD_SHIFT).
* Fix nxstyle errors.
arch/arm/include/stm32/chip.h:
* Add new section "Peripheral IP versions" and specify version of
SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows only 2 bits.
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows 5 bits.
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.
Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).
This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.
This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event
There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
(gdb) b longjmp
Breakpoint 1 at 0x8270
(gdb) r
Starting program: /home/chao/code/m3/nuttx/nuttx
[ 0.000000] Assertion failed at file:task/task_onexit.c line: 99
Breakpoint 1, 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
(gdb)
(gdb) bt
|#0 0xf7b905e0 in siglongjmp () from /lib/i386-linux-gnu/libc.so.6
|#1 0xf7f9c3dc in siglongjmp_alias () from /lib/i386-linux-gnu/libpthread.so.0
|#2 0x5655d668 in up_assert (filename=0x56641018 "task/task_onexit.c", line=99) at sim/up_head.c:132
|#3 0x56567413 in _assert (filename=0x56641018 "task/task_onexit.c", linenum=99) at assert/lib_assert.c:36
|#4 0x565f8cfd in on_exit (func=0x565f8c12 <exitfunc>, arg=0x565fd780 <simuart_restoremode>) at task/task_onexit.c:99
|#5 0x565f8c89 in atexit (func=0x565fd780 <simuart_restoremode>) at task/task_atexit.c:109
|#6 0x565fd819 in simuart_start () at sim/up_simuart.c:112
|#7 0x5656c844 in up_uartinit () at sim/up_uart.c:496
|#8 0x5656ba7a in up_initialize () at sim/up_initialize.c:234
|#9 0x5655da56 in nx_start () at init/nx_start.c:701
|#10 0x5655d5e9 in main (argc=1, argv=0xffffd6f4, envp=0xffffd6fc) at sim/up_head.c:96
Change-Id: Ifd7196b2de7bf9fc7cea764c19a5c0eacf08fdb6
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:
* Merge comments when they are section separators for
similar/related registers:
- TIVA_FLASH_FWPWRITE*
- TIVA_FLASH_FSM_SECTOR1*
- TIVA_FLASH_FSM_BSLE*
- TIVA_FLASH_FSM_BSLP*
regards to the data used by the ROM.
Static alloaction sections should end at the begining of the ROM data.
The rest of memory (End of ROM data --> End of DRAM) is added to the
heap.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This adds the inital wiring for i2c bus support in the sim target
and for Linux host adds the lower half that uses the i2c chardev.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Squashed commit of the following:
sim audio: call alsa to playback/capture data
sim/audio: correct the format capability
sim/audio: add pause/resume support
sim/audio: add auto stop when meet AUDIO_APB_FINAL
sim/audio: fix abort when set small buffer_size
sim/audio: move sim_audio.c to sim_alsa.c
Change-Id: I8e00ece79159e844ca17fd4c363480b985ee0490
Signed-off-by: ligd <liguiding1@xiaomi.com>
1. function "stop" should really stop repeat timer
2. delete timer really in rt-timer task to avoid resource being broken
3. timer triggers when stopping/deleting it and skip it in ISR
When HAVE_HSI_CONTROL, adc_reset_hsi_disable() calls adc_reset()
followed by adc_shutdown() and this combination is called before
adc_setup() by upper level ADC driver. Without this patch,
priv->initialized wraps from 0 to 255 in this case.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
In the current compilation environment, the recursive assignment(=) for compile
flags will be delayed until every file is actually need to be compile.
For example:
--------------------------------------------------------------------------------
arch/arm/src/Makefile:
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
CPPFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CFLAGS += $(INCLUDES) $(EXTRAFLAGS)
CXXFLAGS += $(INCLUDES) $(EXTRAFLAGS)
AFLAGS += $(INCLUDES) $(EXTRAFLAGS)
--------------------------------------------------------------------------------
All compilation options will be included recursively,
which will be delayed until the compilation options are actually used:
tools/Config.mk:
--------------------------------------------------------------------------------
define COMPILE
@echo "CC: $1"
$(Q) $(CC) -c $(CFLAGS) $($(strip $1)_CFLAGS) $1 -o $2
endef
--------------------------------------------------------------------------------
All compile flags to be reexecuted $(INCDIR) as long as one file needs to be compiled,
but in fact, the compilation options have not changed in the current directory.
So the we recommand to change the syntax of assignment
From
Recursive (=)
To
Simple (:=)
In this way, we can ensure that all compilation options are expanded only once and reducing repeated works.
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h:
* Fix syntax error. The define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN
had an unintentional comment closing "*/" in the middle of its
name.
This separation allows to interact with the watchdog from OS code,
for example initiating the watchdog very early on boot. Moreover,
these changes make the lower-half driver support an already running
watchdog, which may happen if there's a bootloader which already
started it.
### Summary of Changes ###
Running the NuttX simulation 'as fast as possible' breaks the features
that depend on timing: eg. the Bluetooth stack. Enabling this option by
default SIM_WALLTIME=y will introduce delays and will tick the simulation at
a real pace.
Refresh defconfigs for sim targets and add depends on SIM_WALLTIME for
SIM_HCISOCKET.
Signed-off-by: Sebastian Ene <sene@apache.org>
Summary:
- This commit fixes kernel stack dump information
Impact:
- Affects armv7-a with kernel build
Testing:
- Built with sama5d4-ek:knsh
- Not tested
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects armv6-m with interrupt stack enabled
Testing:
- Built with freedom-kl25z:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv8-m with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-r with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects arm (arm7/9) and c5471 with interrupt stack enabled
Testing:
- Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove -4/-8 offset coding in imx_irq.c and arm_vectors.S
- Instead, add SP adjustment after calling setirqstack/setfiqstack
- Fix off-by-one irq/fiq stack allocation in 8-byte aligned arch
- Fix comments on the user stack pointer in arm_vectors.S
- Also, fix up_dumpstate() to extract the user stack pointer
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-a with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp with QEMU
- Tested with sabre-6quad:nsh with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes CPUx IDLE stack top for SMP
- Also removes SMP_STACK_TOP from smp.h
Impact:
- Affects armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
There is a good case on sim platform:
When we input some cmd and click enter key to start application in terminal,
this context will change to application from IDLE loop. Althrough entey key '\r'
has been received to recv buffer and complete post semaphore of reader, but
pollnotify may not be called because context change. So when application run
poll function, because no events happend and poll enter wait, context will
again change to IDLE loop, this pollnotify of IDLE loop will run to send poll
events, poll function of applicaton will wake up. It's wrong!
Change-Id: I812a889f2e90781a9c3cb4b0251cccc4d32bebd1
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
Summary:
- Modify arm_intstack_base() to return "top" of the IRQ stack for the current CPU
- This change fixes IRQ stack dump information for ARM SMP
- Add arm_intstack_alloc() to return "bottom" of the IRQ stack for the current CPU
- Also, these functions are now implemented in xxx_irq.c (imx/cxd56/lc823450)
- up_color_intstack() and up_check_intstack() now call arm_intstack_alloc()
- These semantics are now consistent with non-SMP case
- up_color_intstack() now initializes whole IRQ stack region for SMP
- Adjust IRQ stack top address for each CPU (e.g. -8)
- Fix setintstack to handle in case of NCPUS=1 (cxd56, lc823450)
- Adjust INTSTACK_SIZE to 8 bytes alignment (cxd56, lc823450)
- Refactor setintstack for lc823450
- Remove old IRQ stack coloring code from up_irqinitialize() (lc823450)
- Introduce g_cpu_intstack_top for lc823450
- Refactor header files
Impact:
- Affects imx6/cxd56xx/lc823450 SMP with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp (with QEMU, NCPUS=1 and 4)
- Tested with spresense:wifi_smp (NCPUS=1 and 2)
- Tested with lc823450-xgevk:rndis (NCPUS=1 and 2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
cfsetispeed() now stores baud rate to c_cflag member of
struct termios, so it must not be overridden later on.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
1.Get the stack pointer from sp instead of .Lstkinit's field
2.Make g_idle_topstack point to the end of the idle stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- I noticed that qemu-i486:nsh can not start
- Finally, I found that the issue was introduced by 4910d43ab0
- Actually, nuttx_elf was linked dynamically
- This commit fixes this issue
Impact:
- Affects x86 (32bit) only
Testing:
- Tested with qemu-i486:nsh
arch/arm/src/tiva/cc13xx/cc13x0_rom.h,
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h:
* Fix nxstyle errors; nxstyle was complaining about lack of a
space after comma because of the presence of line
continuation backslashes immediately after the comma.
Removed these backslashes as they are not necessary: these
lines are typedefs, not preprocessor defines.
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c:
* Fix nxstyle errors.
* No functional changes; however modified one function,
trim_wakeup_fromshutdown(), to avoid blocks that existed
only to declare variables mid-function; nxstyle was
complaining about the positions of the opening and
closing braces of those blocks.
Summary:
- During Wi-Fi audio streaming test, I noticed data corruption in tcb
- Finally, I found an issue in IRQ request handing with IPI
- This commit fixes this issue
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes crash on startup introduced by commit 232aa62f03
Impact:
- Affects all use cases for esp32
Testing:
- Tested with esp32-core:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
pads go through the same GPIO matrix to select one of the 6 possible functions.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Both CPUs are soft-reset with a call to board_reset. This is actually a
Core Reset, so both cores and all registers are reset. The only
exception is RTC.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Summary:
- This commit adds interrupt stack for SMP
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp with CONFIG_ARCH_INTERRUPTSTACK=2048
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The handle_irqreq() is used for remote IRQ control.
- The logic is called via IPI (Inter-Processor Interrupt)
- And the handler should handle only one request
- However, I noticed that the handler handles up to two requests
- This commit fixes this issue
Impact:
- Affects SMP cases only
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Not all boards have an interrupt line from the phy to
the Soc. This commit allows the phy to be polled for
link status.
This may not work on all MAC/PHY combination that
have mutually exclusive link management and operating
modes. The STM32F7 and LAN8742AI do not have such a
limitation.
Summary:
- Apply the same fix for Arm SMP
Impact:
- Affects SMP only
Testing:
- Tested with esp32-core:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same fix for Arm SMP
Impact:
- Affects SMP only
Testing:
- Tested with maix-bit:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I found an issue with up_interrupt_context() when testing.
- And finally found that up_interrupt_context() is not atomic.
- This commit fixes the issue
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp and sabre-6quad:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
There was no error handling before and it would block on common
cases like NACK which meant that you could not use the i2ctool
to perform a scan of the bus.
This does not handle the interrupt flow which also has incomplete
error handling.
This commit corrects the following compilation error:
/usr/include/cygwin/socket.h:27:8: error: redefinition of 'struct sockaddr'
27 | struct sockaddr {
| ^~~~~~~~
In file included from /usr/include/w32api/winsock2.h:57,
from sim/up_wpcap.c:48:
/usr/include/w32api/psdk_inc/_ip_types.h:70:8: note: originally defined here
70 | struct sockaddr {
| ^~~~~~~~
In file included from /usr/include/sys/socket.h:13,
from /usr/include/cygwin/in.h:21,
from /usr/include/netinet/in.h:12,
from sim/up_wpcap.c:57:
/usr/include/cygwin/socket.h:39:8: error: redefinition of 'struct sockaddr_storage'
39 | struct sockaddr_storage {
| ^~~~~~~~~~~~~~~~
In file included from sim/up_wpcap.c:48:
/usr/include/w32api/winsock2.h:269:10: note: originally defined here
269 | struct sockaddr_storage {
| ^~~~~~~~~~~~~
The compilation was broken by a couple of recent blind, unverified changes to up_wpcap.c. Most were introduced with commit: 8ce0ff5ce4 with this change:
diff --git a/arch/sim/src/sim/up_wpcap.c b/arch/sim/src/sim/up_wpcap.c
index ef7b4b3a0c..a15421e80c 100644
--- a/arch/sim/src/sim/up_wpcap.c
+++ b/arch/sim/src/sim/up_wpcap.c
@@ -55,6 +55,8 @@
#include <netinet/in.h>
+#include "up_internal.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
up_internal.h includes:
47 # include <sys/types.h>
48 # include <stdbool.h>
49 # include <netinet/in.h>
And netinet/in.h includes:
46 #include <sys/types.h>
47 #include <sys/socket.h>
48 #include <stdint.h>
Which is where the collision error is introduced since up_wpcap.c includes winsock2.h already. There were additional problems introduced to the file by other changes:
- A malformed syslog() call was added
- Some issues with netdriver_setmacaddr()
When the Head to Tail relationship was H < T, then
only the tail to end of buffer was sent.
The fix is: In the txdma completion to do a second
the DMA operation using nbuffer if the nlength is
non zero.
stm32f7:serial UART5 use actual size
UART5 was using the CONFIG_UART5_TXBUFSIZE
not the UART5_TXBUFSIZE_ADJUSTED.
Since the buffer size was adjusted up, this
has no dcache implications.
If the UART5_TXBUFSIZE_ADJUSTED is larger
then CONFIG_UART5_TXBUFSIZE it will present
a larger usable buffer to the system's
serial driver.
## Summary of Changes
Add a host timer that generates periodic signals and sends SIGALRM to
the process that runs the NuttX simulation. This logic is integrated as
part of the existing NuttX oneshot timer. The host timer installs an
irq handler which is expected to run every CONFIG_USEC_PER_TICK .
Signed-off-by: Sebastian Ene <nuttx@fitbit.com>
