Tomasz Wozniak
96d6bc9376
Build break fix: define PWM_TIM2_CH1CFG for channel 1 PWM
2017-09-26 20:55:23 +02:00
Miha Vrhovnik
b2ea300b6f
STM32 L4: Add SDMMC driver
2017-09-26 06:22:39 -06:00
Gregory Nutt
b065b1f5df
STM32 Serial: Fix some incorrect conditional compilation
2017-09-23 10:58:50 -06:00
David Sidrane
a3364b5bd9
Merged in david_s5/nuttx/master_stm32_f4_i2c (pull request #490 )
...
stm32:stm32f40xxx I2C ensure proper isr handling
Injecting data errors that causes a STOP to be perceived by the
driver, will continually re-enter the isr with SB not set and BTF
and RxNE set. This changes allows the interrupts to
be cleared and propagates a I2C_SR1_TIMEOUT to the waiting task.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-21 20:02:05 +00:00
Juha Niskanen
abcaedb990
Merged in juniskane/nuttx_stm32l4/dfsdm_adc_work_pr (pull request #487 )
...
STM32L4 ADC, DFSDM: add routing of ADC data to DFSDM filters
* configs/nucleo-l496zg: add DFSDM initialization
* STM32L4 ADC: add option for routing ADC data to DFSDM, fix DFSDM DMA
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-20 12:20:45 +00:00
Gregory Nutt
686129bb2e
Cosmetic change from review of last PR.
2017-09-19 06:46:20 -06:00
Juha Niskanen
38f44a627b
Merged in juniskane/nuttx_stm32l4/stm32l4_dfsdm_pr (pull request #486 )
...
STM32L4 DFSDM: add peripheral, DAC, TIM: small changes
* STM32L4 DAC: do not configure output pin if it is not used
* STM32L4 TIM: fix compilation of timers with complementary outputs when not PWM_MULTICHAN
* STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs
Initial version. Timer trigger support is not completed and there is
some issue with DMA.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-19 12:36:19 +00:00
Gregory Nutt
882adb2c82
drivers/video/fb.c: Fix a typo introduced in previous commit.
2017-09-17 14:07:08 -06:00
Gregory Nutt
b90b4d40b6
Fix typos/spelling. SAMV71-XULT: Update README, add support for fb_driver.
2017-09-17 10:38:34 -06:00
Rajan Gill
fd9f67c647
STM32 Tickless: The attached patch removes the restriction to 16bit counts when a 32bit timer is used for the new tickless on the stm32. As it is now, the restriction is very limiting, especially if one wants high granularity and large achievable intervals and has the hardware (namely the 32bit timers) available.
2017-09-16 08:20:07 -06:00
Gregory Nutt
37a29cf3a3
LPC31xx: Change naming of some global variables to match coding standard.
2017-09-14 15:33:28 -06:00
Gregory Nutt
13006ecca9
STM32/STM32 F7: Fix some errors found by Coverity.
2017-09-13 13:05:13 -06:00
Rajan Gill
15784ca46f
STM32 Tickless: Fixes compilation error when timer info/debug messages are enabled.
2017-09-13 07:14:13 -06:00
David Sidrane
2bbe389897
stm32:Fix coding standard error
2017-09-12 14:16:46 -10:00
David Sidrane
48f0209b84
stm32f7:I2C fixed typo in comment
2017-09-12 14:16:45 -10:00
David Sidrane
ef411578d5
stm32:stm32 alt I2C ensure proper error handling.
...
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
2017-09-12 14:16:45 -10:00
David Sidrane
617c91b373
stm32:stm32f40xxx I2C ensure proper error handling.
...
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
2017-09-12 14:16:45 -10:00
Jussi Kivilinna
61878848ad
net/sock: recvfrom: Fix double leave_cancellation_point on error path
2017-09-12 07:17:53 -06:00
Gregory Nutt
d76a541a57
Trivial, cosmetic
2017-09-11 19:22:49 -06:00
Masayuki Ishikawa
d95153706a
Merged in masayuki2009/nuttx.nuttx/lc823450 (pull request #481 )
...
latest updates on lc823450
* arch/arm/src/lc823450: Conform to the NuttX coding style
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Merge the latest fix in lc823450_rtc.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add ADC driver
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add watchdog driver
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable ADC and watchdog driver
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-12 01:00:32 +00:00
Mateusz Szafoni
2ffc2ab875
Merged in raiden00/nuttx (pull request #480 )
...
Master
* smps.c: fix error messages
* stm32f33xxx_hrtim.h: fix definition
* stm32_hrtim: fix pclk calculation
* stm32_hrtim.c: cosmetics
* smps.h: cosmetics
* add upper-half driver for high power LED driver (powerled)
* stm32f334-disco: beginning of lower half driver for high power LED (powerled)
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-10 17:43:20 +00:00
Gregory Nutt
435dd39d4c
arch/arm/Kconfig: Add more classic ARM11 architecture selections.
2017-09-09 12:44:56 -06:00
Gregory Nutt
3ca3674cca
Update/fix last commit: On some STM32's, the CSR regiser is 18 vs. 16 bits wide. Need to use 32-bit register accesses.
2017-09-08 14:21:24 -06:00
Oleg Evseev
3596c75d78
STM32: Add logic for enabling wakeup pins.
2017-09-08 13:23:08 -06:00
Juha Niskanen
3719d0a395
Merged in juniskane/nuttx_stm32l4/stm32l4_adc_kconfig_pr (pull request #478 )
...
STM32L4: ADC, Kconfig small changes
* STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK
* STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-06 22:05:44 +00:00
Jussi Kivilinna
449a891a8e
stm32f7: add new configuration option for enabling flash ART Accelerator and flash prefetcher
2017-09-04 07:56:51 -06:00
Mateusz Szafoni
23edfe2557
Merged in raiden00/nuttx (pull request #477 )
...
Master
* stm32f33xxx_hrtim.h: add some comments
* stm32_hrtim: add burst mode configuration, rename some definitions
* smps.h: add private data to the smps_s structure
* stm32_hrtim: cosmetics
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-03 18:46:41 +00:00
Gregory Nutt
860ff78d55
Kinetis: First cut implementation of the alarm read function. Pretty simple because the Kinetis RTC is just a 1Hz counter.
2017-09-03 12:44:45 -06:00
Gregory Nutt
5f67fc8f1b
RTC alarms: getalarmdatetime functions are private and should be declared static.
2017-09-03 12:20:13 -06:00
Gregory Nutt
789e204141
Correct naming of fields in struct alm_rdalarm_s. Should not be the same as the corresponding fields of struct alm_setalarm_s. The whole purpose of that naming convention is to keep the field names unique.
2017-09-03 09:51:47 -06:00
Gregory Nutt
f42a8a38eb
Add hooks for Boris Astardzhiev's RTC change for STM32L4 to Kinetis. Lower level logic not yet implemented.
2017-09-03 08:39:03 -06:00
Gregory Nutt
9021e1caeb
Port Boris Astardzhiev RTC change for STM32L4 to STM32
2017-09-03 08:39:03 -06:00
Gregory Nutt
01fa856f9b
Fix warning introduced with PR to STM32L4 RTC.
2017-09-03 08:39:03 -06:00
Gregory Nutt
92b3c9477a
Port Boris Astardzhiev RTC change for STM32L4 to STM32F7
2017-09-03 08:39:02 -06:00
Boris Astardzhiev
b1eceb838b
Extend the RTC framework with an alarm read ioctl (RTC_RD_ALARM). Through it consumer could get configuration settings about previously scheduled hardware alarms (active status, hours, minutes, seconds).
2017-09-03 08:39:02 -06:00
Mateusz Szafoni
daac3bd7f8
Merged in raiden00/nuttx (pull request #476 )
...
Master
* stm32_dac.c: fix compilation when DMA disabled for channel
* smps.h: update some comments
* smps.c: more sanity checks
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-09-02 19:52:21 +00:00
Jussi Kivilinna
fe7d8c941c
stm32f7: do not enable read-modify-write on DTCM. "AN 4667 - STM32F7 Series system architecture and performance" recommends to disable read-modify-write on DTCM: "If the DTCM-RAM is used as data location and the variables used are byte or/and halfword types, since there is no ECC management in this RAM on the STM32F7 Series, it is recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (inthe DTCMCR register) to increase the performance."
2017-09-01 08:01:54 -06:00
Juha Niskanen
258fa08e69
STM32L4 DAC: Fix naming so that DAC1 and DAC2 always refer to channels 1 and 2
...
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.
Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2017-09-01 10:01:03 +03:00
Juha Niskanen
0003ad171d
STM32L4 DAC: separate DMA buffer configuration for channels
...
Change-Id: Ibc6dc90b39b784b5534b8908eaf615bf1ddcb7ed
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2017-09-01 10:00:55 +03:00
Juha Niskanen
4025205772
STM32L4 DAC: add option for routing DAC output to ADC
...
Actually write something to the DAC DMA buffer.
Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2017-09-01 10:00:46 +03:00
Gregory Nutt
91d473b816
Revert "stm32 FLASH allow non blocking operation on constrained devices"
...
This reverts commit ad2ef95ddf
2017-08-31 15:14:26 -06:00
David Sidrane
9fc283526a
Merged in david_s5/nuttx/master_stm32_flash (pull request #474 )
...
stm32 FLASH allow non blocking operation on constrained devices
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-31 18:04:07 +00:00
Sergey Ustinov
8c35b2ddca
Add the set counter function for stm32 timers
2017-08-31 11:54:00 -06:00
David Sidrane
ad2ef95ddf
stm32 FLASH allow non blocking operation on constrained devices
...
On a very memory constrained device with a single task. The
sem_wait and sem_post operations can be disabled, to save space.
The default is blocking enabled.
2017-08-31 07:47:37 -10:00
Sergei Ustinov
795650a2fb
I'm worried about the stm32_tim_getcounter funtion. It returns always 32 bits. But major stm32 timers have 16 bits counters. I think, it's not a good idea to return the memory behind the TIMx_CNT register. This changes adds the register size checking.
2017-08-31 11:45:28 -06:00
Gregory Nutt
a7fd8eb203
Trivial removal of a blank line.
2017-08-31 11:36:18 -06:00
Gregory Nutt
27cfde9968
Protected/Kernel Builds: Review us of kmm_addregion vs. kumm_addregsion in other configurations.
2017-08-31 08:49:21 -06:00
Gregory Nutt
69f1399aa7
LPC43xx: Add external RAM to the user heap, not the kernel heap.
2017-08-31 08:12:42 -06:00
Alan Carvalho de Assis
ef3898c2dd
LPC43xx: Modify up_allocate_(k)heap() to support PROTECTED mode
2017-08-31 07:58:16 -06:00
Gregory Nutt
9d3b1af1cd
ARM syscall logic: Clear bit 0 in PC settings. Bit 0 is the thumb mode indication and should not be set in the PC.
2017-08-30 13:56:03 -06:00
raiden00pl
85c48de040
stm32_hrtim: add DMA configuration
2017-08-28 17:44:14 +02:00
Juha Niskanen
809569cda9
STM32L4 ADC: implement peripheral
2017-08-28 07:05:33 -06:00
Juha Niskanen
a2dc88e075
STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time
2017-08-28 07:05:33 -06:00
Juha Niskanen
e8cd2f88b8
STM32L4 RCC: enable ADC clock source
2017-08-28 07:05:32 -06:00
Alan Carvalho de Assis
81d6cefd65
Add support to STM32F433RC
2017-08-28 07:05:32 -06:00
raiden00pl
5695a55569
stm32_dac.c: support external triggering for DMA transfer
2017-08-27 18:25:55 +02:00
Mateusz Szafoni
ea35f31f73
Merged in raiden00/nuttx (pull request #469 )
...
Master
* stm32f0/Kconfig: remove references to HRTIM
* STM32F33: missing SYSCFG CFGR3 definitions
* stm32_hrtim.h: remove redundant definitions
* stm32_hrtim.c: fix DAC triggers configuration
* stm32_hritm.c: warning message when default value selected
* stm32_hrtim.c: missing master timer logic
* stm32_hrtim.c: add more assertions
* stm32_dac.c: fix conditional
* stm32_dac.c: conditional logic for timer triggering
* stm32_dac.c: fix TSEL configuration when HRTIM
* stm32_dac.c: unnecessary condition
* stm32_dac.c: DMA request remapping
* stm32_dac.c: fix commpilation errors
* stm32_dac.c: add DMA buffers initialization logic
* stm32_hrtim.c: enable DAC triggering
* analog/comp.c: fix compilation errors when poll disabled
* stm32_hrtim.c: remove doubled assertions
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-27 12:49:53 +00:00
Gregory Nutt
7858ed834b
Minor, cosmetic changes from review of last comment.
2017-08-27 06:48:42 -06:00
Masayuki Ishikawa
cc9c8260f0
arch/arm/src/lc823450: Add eMMC/SD and USB support
...
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2017-08-27 19:11:07 +09:00
Masayuki Ishikawa
56bf5b2a98
arch/arm/src/lc823450: Conform to the NuttX coding style
...
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2017-08-27 19:11:03 +09:00
Juha Niskanen
1be5f0a3fc
STM32L4 COMP: comparators share RCC enable bit with SYSCFG
2017-08-25 07:06:39 -06:00
Juha Niskanen
1152e4868b
STM32L4 DAC: report transfer as completed in DMA callback. Without this even O_NONBLOCK writes block the calling task if DAC was using DMA.
2017-08-25 07:05:11 -06:00
Juha Niskanen
874947d7e5
STM32L4 TIM: TIM15,16,17 are always in APB2
2017-08-25 07:02:21 -06:00
Gregory Nutt
dc8f3778a9
drivers/sensors: Fix more naming of configurations to be compliant for two more drivers. Still a few more to go.
2017-08-24 10:26:53 -06:00
Jussi Kivilinna
310a29227a
drivers/lcd: add DD-12864WO-4A/SSD1309 support to SSD1306 driver
2017-08-22 08:32:52 -06:00
Juha Niskanen
d7ae3d74c3
STM32L4 ADC: correct EXTSEL macros
2017-08-22 06:49:48 -06:00
Pekka Ervasti
6b1ccef2f9
STM32L4 COMP: bind to upper half comp driver
2017-08-22 06:47:57 -06:00
raiden00pl
a5997cb186
stm32_dac: add support for HRTIM triggering
2017-08-21 19:46:18 +02:00
raiden00pl
a5f3a5848d
stm32_dac.c typo
2017-08-21 18:59:21 +02:00
raiden00pl
db7a94288f
stm32f33xxx_dma.h: typos
2017-08-21 18:50:07 +02:00
raiden00pl
b460f2bca1
stm32f10xxx_dma.h: fix DAC names and remove STM32F33 section
2017-08-21 18:50:07 +02:00
raiden00pl
104ff2b5d8
stm32_dac: separate dma buffer configuration for channels
2017-08-21 18:50:07 +02:00
Juha Niskanen
37867ae3b9
chip.h edited online with Bitbucket: correct some STM32_NDAC
2017-08-21 07:30:58 +00:00
Mateusz Szafoni
ccd421b158
stm32_dac.c edited online with Bitbucket
2017-08-20 18:47:44 +00:00
raiden00pl
04743f3e77
stm32_dac: change name convention. Previous naming was confusing
2017-08-20 20:19:53 +02:00
raiden00pl
0bed6ac8b4
STM32F33: correct STM32_NDAC
2017-08-20 20:07:50 +02:00
raiden00pl
a8e8862ef9
stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2.
2017-08-20 19:02:56 +02:00
raiden00pl
1479fd6075
stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code
2017-08-20 10:45:55 +02:00
raiden00pl
30ebd32ab4
stm32f33xxx_pinmap.h: missing define
2017-08-20 10:45:55 +02:00
raiden00pl
241c42447f
stm32f33xxx_comp.h: typos
2017-08-20 10:45:55 +02:00
raiden00pl
01c98df18c
STM32F33: remove redundant DAC file
2017-08-20 10:45:55 +02:00
David Sidrane
b594d43d24
Merged in david_s5/nuttx/upstream_dma_dcache_fix (pull request #462 )
...
STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and SDMMC stm32_dma{recv|send}setup
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-17 20:14:24 +00:00
David Sidrane
ef42c25140
stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup
...
In the where CONFIG_SDIO_PREFLIGHT is not used and
dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
boundaries.
2017-08-17 09:51:37 -10:00
David Sidrane
1e7ddfea8e
stm32f7:SDMMC remove widebus limitation on DMA
...
There is no documantation for the STM32F7 that limits DMA on
1 bit vrs 4 bit mode.
2017-08-17 09:48:46 -10:00
David Sidrane
dffab2f4dd
stm32f7:DMA add dcache alignment check in stm32_dmacapable
...
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
2017-08-17 09:39:14 -10:00
David Sidrane
38cbf1f660
stm32f7:DMA correct comments and document stm32_dmacapable
...
Updated comment to proper refernce manual for STM32F7 not
STM32F4.
Added stm32_dmacapable input paramaters documentation.
2017-08-17 09:35:50 -10:00
Gregory Nutt
06a12bea6c
STM32L476VG Discovery: Add a knsh configuration that may be used to test the PROTECTED build mode.
2017-08-17 09:15:12 -06:00
Gregory Nutt
06473e89de
Update MRF24J40 starhub configuration for the SAME70 Xplained.
2017-08-16 09:39:25 -06:00
David Sidrane
5ef33f3e58
Merged in david_s5/nuttx/upstream_missing_semi (pull request #459 )
...
stm32f7:rtc Missing semicolon
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-08-16 02:49:24 +00:00
David Sidrane
ab578bb338
stm32f7:rtc Missing semicolon
2017-08-15 16:17:55 -10:00
Gregory Nutt
dcb8df76d0
Fix argument to SPI initializatio function
2017-08-15 19:07:35 -06:00
Juha Niskanen
f383308a02
STM32L4 ADC: add ADC register definitions
2017-08-14 06:47:12 -06:00
Juha Niskanen
2fbd7d7b59
STM32L4 DAC: port from STM32. Note that this does not address the somewhat confusing relation between STM32L4_NDACS and DAC2 config macros that comes from original STM32 code.
2017-08-14 06:38:13 -06:00
Juha Niskanen
9ac80e45f5
STM32L4 COMP: input minus pin extended selection
2017-08-14 06:29:13 -06:00
Juha Niskanen
a9343ca12b
stm32/stm32f0: Fix some funny shifts in DAC header files.
2017-08-14 06:28:09 -06:00
Gregory Nutt
e224d354b8
STM32F7: Remove unsupported configuration item the crept in when header file was cloned.
2017-08-13 12:37:59 -06:00
Gregory Nutt
f6f4856cc6
Eliminate some warnings found in build testing.
2017-08-13 12:24:48 -06:00
Gregory Nutt
873de7b480
configs/*/README.txt: Update to the new URL for obtaining the ARM toolchain.
2017-08-13 07:18:19 -06:00
Gregory Nutt
2ab8852b29
STM32F7: Some STM32F7 builds failed in build testing due to undefined STM32_SRAM1_BASE. I think that is because stm32_allocateheap.c was not including chip/stm32_memorymap.h
2017-08-13 06:50:48 -06:00
Gregory Nutt
03c26df04a
STM32F7 builds broken. This is a work around to at least keep them building.
2017-08-13 06:44:04 -06:00
Gregory Nutt
4fa6106b57
Fix some compile problems found in build testing.
2017-08-12 14:28:27 -06:00
Gregory Nutt
1f989af845
Update TODO list; SAMv7 XDMAC: Remove and unused global array.
2017-08-12 12:26:13 -06:00
Gregory Nutt
4b6f0149ec
Eliminate a warning found in build testing.
2017-08-12 11:14:11 -06:00
Gregory Nutt
6bae133e74
Fix two warnings found in build testing.
2017-08-12 11:09:48 -06:00
Gregory Nutt
bd7c84b23e
Remove CONFIG_NETDEV_MULTINIC. This increases code size by a little, but greatly reduces the complexity of the network code.
2017-08-08 14:24:12 -06:00
Stefan Kolb
22dfa875fc
I discovered while working on the SAMV7 mcan driver that the implementation of the CAN error handling is suboptimal. In the current implementation the following errors are implemented as pending errors:
...
* Receiving
* MCAN_INT_STE (Stuff Error)
More than 5 equal bits in a sequence occurred.
* MCAN_INT_CRCE (CRC Error)
Received CRC did not match the calculated CRC.
* MCAN_INT_RF0L (Receive FIFO 0 Message Lost)
Receive FIFO 0 message lost, also set after write attempt to Receive FIFO 0 of size zero.
* MCAN_INT_RF1L (Receive FIFO 1 Message Lost)
Receive FIFO 1 message lost, also set after write attempt to Receive FIFO 1 of size zero.
* Sending
* MCAN_INT_BE (Bit Error)
Device wanted to send a rec / dom level, but monitored bus level was dominant / recessive.
* MCAN_INT_TEFL (Tx Event FIFO Element Lost)
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
* General
* MCAN_INT_MRAF (Message RAM Access Failure)
The flag is set, when the Rx Handler
* has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
* was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation mode (see Section 47.5.1.5). To leave Restricted Operation mode, the processor has to reset MCAN_CCCR.ASM.
* MCAN_INT_ELO (Error Logging Overflow)
Overflow of CAN Error Logging Counter occurred.
The listed errors are not pending, the errors occurred and are gone directly afterwards. This commit changes the described behavior and simplifies the handling of CAN errors.
2017-08-07 10:31:04 -06:00
Jeff
4cbde22992
I'm working on bringing up USB full-speed support on STM32F405. My board does not include a USB power switch, VBus sensing, over current detection, or ID pin.
...
This commit add a config STM32_OTGFS_VBUS_ CONTROL which lets us selectively disable VBus sensing and control. I also sneaked in a change to disable the configgpio call for the ID pin, which is only used in OTG mode which isn't supported yet. The only pins that need to be initialized should be OTGFS_DP and OTGFS_DM.
These changes let a USB mouse enumerate on my platform if it's plugged in on power-up. Plugging, unplugging, clicking, or moving the mouse cause NSH to stop responding. Because I'm using the ramlog, I don't have useful debug messaging yet, so there's a lot more work I have to do to troubleshoot it or get my JTAG debugging set up, but these patches shouldn't hurt anything. I'm hoping my issue is something simple I overlooked in configuration.
I'm planning to add similar changes for the OTGHS peripheral (using integrated full speed phy) but I still need to test those changes before submitting patches.
2017-08-07 10:24:31 -06:00
Simon Piriou
b1f50490bd
MTD: Add driver for Macronix QuadSPI flash memory
2017-08-06 10:51:17 -06:00
Gregory Nutt
42b3ee4cfc
Fix a few errors that crept in with my review changes.
2017-08-02 09:19:29 -06:00
Gregory Nutt
5f2d4b8f84
Changes from review of commit e851a24329
2017-08-02 08:26:08 -06:00
Masayuki Ishikawa
e851a24329
arch/arm/src/lc823450: Initial support for ON Semiconductor LC823450
...
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2017-08-02 21:09:43 +09:00
Titus von Boxberg
55e9c8990c
stm32_rcc: code style
2017-08-01 16:25:19 +02:00
Titus von Boxberg
a4e97d5daf
Added functions for DSI clock source selection
2017-08-01 16:24:48 +02:00
Gregory Nutt
05ea22e9ab
STM32F7: Fix for coding standard violations that came in with cd3ca1140e -- missed a file last time
2017-07-31 18:36:38 -06:00
Gregory Nutt
5f4fdb42be
STM32F7: Fix for coding standard violations that came in with cd3ca1140e
2017-07-31 18:35:37 -06:00
Titus von Boxberg
604a6dc0fa
improved help text
2017-08-01 01:23:28 +02:00
Titus von Boxberg
bdee01f492
added function for reset
2017-08-01 01:23:28 +02:00
Titus von Boxberg
0947b31fbb
STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S; PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
2017-08-01 01:23:28 +02:00
Titus von Boxberg
9d56dbb403
comment corrected
2017-08-01 01:23:28 +02:00
Titus von Boxberg
63bce1fc34
no board specific dithering values used; corrected comment; corrected dithering init
2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec95720d13
corrected LIPOS/LIPCR calculation
2017-08-01 01:23:28 +02:00
Titus von Boxberg
28a53d8e25
change only polarity bits in LTDC_GCR
2017-08-01 01:23:28 +02:00
Titus von Boxberg
5de2468521
comments corrected
2017-08-01 01:23:28 +02:00
Titus von Boxberg
69aca28e87
commented
2017-08-01 01:23:28 +02:00
Titus von Boxberg
ec43001d91
HEAP2 depends on CONFIG_ARCH_HAVE_HEAP2, not on particular FMC RAM type
2017-08-01 01:23:28 +02:00
Titus von Boxberg
777b17928f
corrected register debugging
2017-08-01 01:23:28 +02:00
Titus von Boxberg
1944ab6f9b
added missing config option for register value debugging
2017-08-01 01:23:28 +02:00
Titus von Boxberg
dc392a6c68
enable APB2 DSI clock
2017-08-01 01:23:28 +02:00
Juha Niskanen (Haltian)
20dc5ad3b4
STM32L1: add base address for TIM11
...
STM32L4 PWR: correct PWR_SR2 REGLPS and REGLPF bits, add port I registers. Also remove duplicate section from Kconfig
2017-07-31 07:32:43 -06:00
Jeff
a420c0f369
To use an external oscillator module (not just a crystal) with the STM32F4, one needs to enable the HSEBYP bit in the RCC_CR register. This change allows an integrator to define STM32_RCC_CR_HSEBYP in their board.h file if they want this configuration.
2017-07-30 06:22:30 -06:00
Gregory Nutt
47791442a0
Squashed commit of the following:
...
commit 3fcf84a9a2673e1e1466ce5b114d7b73c257e515
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 12:00:31 2017 -0600
Spirit: Brings in the last of the PktCommon interfaces.
commit d26ebd901ba4ba84910e99b4e728b98c30fa4c0b
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:54:52 2017 -0600
Spirit: Add a few more PktCommon interfaces.
commit b5cb8041d50233a4abb8fb4d1dcef5428ae2c2b2
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:33:31 2017 -0600
libc/termios: Remember block comments before empty file sections.
commit 0fcab2c1c8c74442d40bd5e8c6af50a34f8a5821
Author: Sebastien Lorquet <sebastien@lorquet.fr>
Date: Fri Jul 28 09:31:00 2017 -0600
tcdrain implementation based on a new term ioctl
commit 797d4adf7d41068c671f0217d369b797b269de1a
Author: Stefan Kolb <Stefan.Kolb@avat.de>
Date: Fri Jul 28 09:19:04 2017 -0600
We discovered a problem with the samv7 mcan driver which results, under some circumstances, in a very high CPU load.
The problem occurs, and is easily reproducible, if the device is connected to a CAN network with a wrongly configured CAN speed (baud rate). In our tests we set the CAN speed of the device to 1000000 and the speed of the other CAN nodes to 500000. The device is restarted and sends a CANopen “bootup message” to the CAN network. This results in huge amount of errors messages on the CAN bus, probably because of the CAN feature for acknowledging error messages. The error messages can’t be read by the device because of the misconfigured CAN speed, instead the CAN chip reports lots of errors, which are reported to the application which uses the CAN driver (CONFIG_CAN_ERRORS is enabled).
The CAN errors are reported from the CAN chip via interrupts and thus the interrupt load is very high in this scenario. To fix the problem the driver now disables each RX error interrupt after it is occurred. The RX error interrupts are turned back on if at least one CAN message is received successfully.
commit e298f48e96d9e34017dcab8e4d87032862ae9322
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 28 09:06:26 2017 -0600
Spirit: Bring in PktStack interfaces.
commit 4a0f00a7058312dcf6ac392689b9f69112f613ec
Merge: 855cf97130 b458934ac4f287cc25d6598386ef90c9ff8cbab92fc0fbcf7e6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-28 12:01:05 -06:00
Gregory Nutt
5f31999b75
Trivial fix to spacing
2017-07-27 11:50:59 -06:00
Titus von Boxberg
28eab902d0
No FSMC, only FMC for STM32F7
2017-07-27 18:27:01 +02:00
Gregory Nutt
2fc0fbcf7e
Squashed commit of the following:
...
commit 89e9d426e91c056e659fccf5e5c4392618f8f777
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:44:19 2017 -0600
Update some comments
commit 9c5d8a5833350006ed389e898b11c8c8a20e5f4f
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:15:54 2017 -0600
Spirit: Rename drivers/wireless/spirit/src to lib. Move Spirit network driver out of IEEE802.15.4 into drivers/wireless/spirit/drivers
commit cabc0ec9e6eb558dcb715ab17264383aa0105e7a
Merge: 87b616414a 6bd744c4b3f4e46b0da72319ea53a9d88dc9b2e5
2017-07-24 16:46:30 -06:00
Gregory Nutt
f4e46b0da7
Missed part of 2319ea53a9. Was still getting the warning.
2017-07-22 10:55:54 -06:00
Gregory Nutt
2319ea53a9
STM32L4: Eliminate a warning about implicit definition of function. While we are at it, let's improve the naming a little too.
2017-07-22 09:53:29 -06:00
raiden00pl
f6c1d59531
stm32_hrtim: add slave timers private data, fix some bad definitions, some asserions
2017-07-22 15:14:59 +02:00
Gregory Nutt
c3b552e072
Minor cosmetic updates from review of last PR.
2017-07-20 07:39:57 -06:00
Titus von Boxberg
a20c3b17ce
warning message when using DSI (for debugging)
2017-07-19 20:39:27 +02:00
Titus von Boxberg
7b07471ece
documentation update to f7
2017-07-19 19:14:50 +02:00
Titus von Boxberg
6d29a04752
naming errors/inconsitencies/typos
2017-07-19 19:14:49 +02:00
Titus von Boxberg
1241960d4a
STM32F7: Switch from CCM to DTCM
2017-07-19 19:07:53 +02:00
Titus von Boxberg
071b2dda28
compileable with LTDC_INTERFACE and LTDC_USE_DSI
2017-07-19 19:07:53 +02:00
Titus von Boxberg
e67ba8c88d
option for DSI output
2017-07-19 19:07:53 +02:00
Titus von Boxberg
d590ba7ab2
do not enforce CONFIG_STM32_CCMEXCLUDE for CONFIG_ARCH_CHIP_STM32F7, macro rename STM32 -> STM32F7, #include corrections
2017-07-19 19:07:53 +02:00
Titus von Boxberg
1826c1165a
macro rename STM32 -> STM32F7, #include corrections
2017-07-19 19:07:53 +02:00
Titus von Boxberg
32e417c3ac
renamed STM32_LCDTFT_BASE to STM32_LTDC_BASE for consistency
2017-07-19 19:07:53 +02:00
Titus von Boxberg
58053fef0f
macro rename STM32 -> STM32F7
2017-07-19 19:07:53 +02:00
Titus von Boxberg
ec3e4cabab
added config and make stuff for stm32f7 ltdc
2017-07-19 19:07:53 +02:00
Titus von Boxberg
ea703b832a
copied from stm32
2017-07-19 19:07:53 +02:00
Titus von Boxberg
07531de2e4
Copied files from stm32
2017-07-19 19:07:53 +02:00
Matt Thompson
eff9ba514c
SAMD21: Changes needed to get USB working.
2017-07-19 07:22:14 -06:00
Titus von Boxberg
f3267ddb71
I2C4_SDA can also be on GPIO PB7
2017-07-18 11:43:53 +02:00
savinz
1b27dd32af
STM32 F7 Ethernet: Fix typo in header; Add memory sync barrier between writing to DMA TX descriptor and restarting DMA TX. Avoid calling work_queue on pollwork if it's already queued, just skip a poll cycle instead. Nucleo-144: Fix RMII TXD1 signal, connected to PB13 not to PG14.
2017-07-14 09:23:43 -06:00
Gregory Nutt
447785b264
SAMD/L21: Need to preserve errno value across syslog() call.
2017-07-12 16:22:23 -06:00
Gregory Nutt
10fbb2b089
SAMD/L21 USB: Remove all commented out logic.
2017-07-12 08:10:21 -06:00
Janne Rosberg
76ea6f09ec
SAMD/L21: Add a USB driver. Developed for Filament Inc. by Offcode, LTD.
2017-07-12 07:46:46 -06:00
Matt Thompson
5448c99ff2
I was having issues with the bus freezing up .. slaves holding SDL low.. so I rewrote a good portion of the interrupt logic based on the application notes from Atmel. One major improvement is using the RXNACK flag in the STATUS register, which indicates that no device responded to an address packet. Assuming that the chip will always give an interrupt status, I believe it's possible to eliminate the timer as well.
2017-07-12 06:44:53 -06:00
Matt Thompson
1e0560b22f
SAMD21: Fix some SPI-related issues.
2017-07-11 12:48:38 -06:00
Gregory Nutt
839019f305
SAMD/L21 I2C: Another update... needs to use enter/leave_critical_section vs. old irqsave/restore.
2017-07-11 07:01:05 -06:00
Alan Carvalho de Assis
5b9526b4c1
SAML21 I2C driver. Developed for and contributed with permissin from Filament company.
2017-07-11 06:58:58 -06:00
Gregory Nutt
79e5d2b7b6
STM32 TIM3/4 are always 16-bits; never 32-bits. Noted by Eetu Nevalainen.
2017-07-10 13:56:06 -06:00
Gregory Nutt
76587b2c6f
STM32 Kconfig: 'unfold' some of the dependencies to provide better long term configuration support. This also effective reverts the recent 15b85738e7
2017-07-06 10:34:54 -06:00
Gregory Nutt
47be509d79
Rename CONFIG_STM32_STM32F40XX to CONFIG_STM32_STM32FXXXX since it is used by F4 parts other than F40x
2017-07-06 10:20:14 -06:00
gwenhael.goavec
15b85738e7
In arch/arm/src/stm32/Kconfig when the CPU is a STM32F4, some STM32_HAVE_xx with xx = {OTGFS, TIM3, TIM4, SPI3, I2S3, I2C3} are selected by default. But for F410 these peripherals are absent. This change add tests to check if the target CPU is an F410 or not and selects according to the situation. This also adds a select for STM32_HAVE_DAC1 present on this STM32 flavor.
2017-07-06 09:52:21 -06:00
Eetu Nevalainen
21dcc8cbc7
stm32f40xxx_rtcc ISR register and write protection fix
2017-07-03 11:06:07 -06:00
Gregory Nutt
68315b7444
Merged clang into master
2017-07-03 07:04:57 -06:00
Gregory Nutt
09ab651e02
samv71-xult: Add support for the MRF24J40 radio and create a mrf24j40-starhub configuration. A few fixes to IPv6 and 6LoWPAN were required to have 6LoWPAN and Ethernet coexisting. Untested and expect some complexity in the bring-up.
2017-07-02 11:04:57 -06:00
Gregory Nutt
cf44fd6ec0
Add CLANG definitions in Kconfig and Toolchain.defs
2017-07-02 06:42:48 -06:00
Gregory Nutt
1c5ec07414
arch/: Remove dangling space at the end of lines.
2017-06-28 13:16:48 -06:00
Gregory Nutt
aa1708e7c0
6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver.
2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff
stm32f33xxx_rcc: cleanup + move hrtim clock source selection
2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd
stm32f33xxx_rcc.h: fix typo
2017-06-26 18:26:59 +02:00
Juha Niskanen
56eeb40958
STM32L4 serial: Allow configuring Rx DMA buffer size
2017-06-26 09:19:42 -06:00
Juha Niskanen
90ccdf287d
STM32 L4 DMA: Correct USART3_RX bad channel definition
2017-06-21 08:40:33 -06:00
David Sidrane
345ea957cf
Merged in david_s5/nuttx/upstream_kinetis (pull request #414 )
...
Kinetis:I2C fixed mis-placed kinetis_i2c_endwait
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-06-20 20:22:17 +00:00
David Sidrane
839a6e09f4
Kinetis:I2C fixed mis-placed kinetis_i2c_endwait
...
Fixed accedently replaced post with wait.
2017-06-20 10:01:35 -10:00
Gregory Nutt
5de74441a6
Costmetic change from review of last PR
2017-06-20 13:33:14 -06:00
David Sidrane
1ee03d7500
Merged in david_s5/nuttx/upstream_kinetis (pull request #413 )
...
Kinetis:I2C driver added I2C3, reference counting and reset
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-06-20 19:31:38 +00:00
David Sidrane
9e0f583774
Kinetis:I2C driver added I2C3, reference counting and reset
...
Refactored the driver to support reference counting and reset
added I2C3
2017-06-20 08:34:12 -10:00
Sebastien Lorquet
0bf4893b2c
STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers.
2017-06-20 11:56:54 -06:00
Juha Niskanen
326ab01a91
STM32 F7: Set I2C4 SDA and SCL pins to open drain mode
2017-06-20 08:06:30 -06:00
Juha Niskanen
2c548a4e58
STM32 L4: I2C4 was writing to wrong RCC registers
2017-06-20 08:04:09 -06:00
Gregory Nutt
47ad81b3e5
Trivial spelling fix
2017-06-20 08:02:42 -06:00
Pekka Ervasti
2eb782961f
STM32 L4: Set I2C SDA and SCL pins to open drain mode.
2017-06-20 07:59:27 -06:00
Jussi Kivilinna
a1ee9547f3
stm32_adc: invalidate dma buffer before use. Missing invalidation caused old samples being fetched from cache.
2017-06-19 07:52:19 -06:00
raiden00pl
c29c4e2ec2
stm32_hrtim: remove unneeded definitions
2017-06-18 18:08:25 +02:00
raiden00pl
4e0f45f252
stm32_hrtim: fix initialization bug, minor changes
2017-06-18 18:06:37 +02:00
raiden00pl
cd30545cd9
stm32_hrtim: ADC triggering and DAC synch events
2017-06-18 15:26:39 +02:00
raiden00pl
96e639262a
stm32_hrtim: add hrtim ops
2017-06-18 11:01:36 +02:00
raiden00pl
797e286cb0
stm32_hrtim: timers mode configuration
2017-06-18 09:28:05 +02:00
raiden00pl
dfeffefa69
stm32_hrtim: typo
2017-06-18 08:02:15 +02:00
Gregory Nutt
0024840f7d
Trivial, cosmetic changes from review of last PR
2017-06-17 14:44:11 -06:00
raiden00pl
b48a86ee33
Merge remote-tracking branch 'upstream/master'
2017-06-17 22:18:03 +02:00
raiden00pl
4d9d3c4a9c
stm32_hrtim: cosmetics
2017-06-17 22:12:56 +02:00
raiden00pl
5e3360b8b9
stm32_hrtim: faults and events configuration
2017-06-17 21:56:11 +02:00
David Sidrane
c79d4d1988
stm32:flash add CONFIG_STM32_STM32F469 to list defining OPTCR1
2017-06-16 14:16:32 -10:00
Gregory Nutt
5245cbc6f5
STM32 SPI/I2S: Back out a bad pin mapping change from 4ab2a3661e. Try to staighten out some I2C3 and SPI3 pin configuration stuff.
2017-06-16 09:34:22 -06:00
Sebastien Lorquet
4d9be9bc20
STM32 F4 FLASH: Enable/disable the flash write protection on any sector. I have verified it to work on the stm32f427.
2017-06-16 08:46:57 -06:00
raiden00pl
bd7bee5db0
stm32_hrtim: structures for deadtime and chopper, cosmetics
2017-06-16 11:36:23 +02:00
David Sidrane
64e3dc5e8b
Merged in david_s5/nuttx/upstream_samv7_twi (pull request #399 )
...
samv7:twihs driver add reference counting
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-06-15 21:45:07 +00:00
David Sidrane
d9d32ac808
samv7:twihs driver add reference counting
2017-06-15 11:16:28 -10:00
raiden00pl
268c6d0b7d
stm32_hrtim: outputs enable, period and compare functions, cosmetics
2017-06-15 16:45:21 +02:00
Gregory Nutt
d958cec7a4
Cosmetic changes from review of last PR
2017-06-15 06:58:55 -06:00
Hidetaka
0f1d388248
Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-kconfig (pull request #394 )
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Fixed typo "CORTEXR5F" in arch/arm/Kconfig
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-06-15 12:12:31 +00:00
Hidetaka
9dfa8f7df9
Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-armv7m-toolchain-def (pull request #395 )
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Fixed ARMv7-M Toolchain definition for Cortex-M4.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2017-06-15 12:12:01 +00:00
Hidetaka Takano
5591fc6b16
Fixed ARMv7-M Toolchain setting.
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- Cortex-M4 only have Single Precision FPU.
2017-06-15 20:52:37 +09:00
Hidetaka Takano
d665392873
Fixed typo "CORTEXR5F" in arch/arm/Kconfig
2017-06-15 20:44:06 +09:00
raiden00pl
96d40dec40
stm32_hrtim: cosmetic
2017-06-15 11:20:40 +02:00
Leif Jakob
4a79547fb8
multiple fixes for stm32f1xx RTC clock
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- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
2017-06-14 22:36:40 +02:00
David Sidrane
b2d929e40a
Kinetis:SPI driver
2017-06-13 17:46:57 -10:00
David Sidrane
de3695d32b
kinetis:lpserial fixed header inclusion
2017-06-13 17:46:56 -10:00
Gregory Nutt
e379491d13
STM32/STM32L4: Review of last commit -- Eliminate possible underflow
2017-06-13 07:05:46 -06:00
JM
7903a8a46c
stm32/stm32l4 PWM: While attempting to output a 70 MHz square wave from the timer output of a STM32 clocked at 140 MHz (which works fine in baremetal C), I stumbled on what I believe to be an error in arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that
...
reload = timclk / info->frequency;
which I belive to be incorrect, it should be
reload = timclk / info->frequency - 1;
since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.
Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.
I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
2017-06-13 06:01:13 -06:00
raiden00pl
f6ba4642a3
stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres
2017-06-12 18:45:58 +02:00
Gregory Nutt
f5f1c73b54
Based on the last PR, review all serial driver vector attachment. Found one additional error and updated all relevant drivers to current interrupt parameter passing.
2017-06-12 06:22:35 -06:00
Masayuki Ishikawa
93a2d52b56
i.MX6: Fix a wrong parameter passed when calling irq_attach() in imx_serial.c
2017-06-12 13:34:53 +09:00
raiden00pl
de8cd6c870
stm32_hrtim: add character driver
2017-06-11 20:51:23 +02:00
Gregory Nutt
fe813545e8
STM32F33: Forgot to add new files that were a part of the last patch before committing.
2017-06-11 11:00:29 -06:00
Mateusz Szafoni
437ad3ccb2
STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver
2017-06-11 10:49:20 -06:00
Gregory Nutt
1e5125c5d5
STM32L4: Remove some C++ style comments.
2017-06-08 13:43:47 -06:00
Gregory Nutt
8b907c4c1f
STM32L4: Fix a typo
2017-06-08 11:07:20 -06:00
Gregory Nutt
d99ceec58c
STM32L4: Add STM32L475 pinmap. Initial cut is just the the L476 pinmap with unsupported devices removed.
2017-06-08 10:55:27 -06:00
Gregory Nutt
596fe68854
STM32L4: Add STM32L475 OTGFS header file. Not fully reviewed.
2017-06-08 10:34:26 -06:00
Gregory Nutt
95fcdff1fd
STM32L4: Add STM32L475 RCC definitions/logic.
2017-06-08 10:04:28 -06:00
Gregory Nutt
1a405d2881
STM32L4: Add L475 syscfg register definitions.
2017-06-08 09:07:04 -06:00
Gregory Nutt
66e2247f30
STM32L4: Ad support for the STM32L475 family. Incomplete -- still needs pinmap, rcc, otgfs, syscfg
2017-06-08 08:52:09 -06:00
David Sidrane
4854eb1fd7
Kinetis:Fixed waning for kinetis_mpudisable
...
Missing header file added
2017-06-06 15:18:01 -10:00
David Sidrane
36da2b91c5
Kinetis:USB-FS driver
...
Removed the notion of attached. The khci_usbattach is call early in
the init either in board_initalize or in board_app_initalize. In
either case it is always done prior to the the class register.
Therefore the khci_usbattach call only set a flag, and that
flag is only tested in the class register. The class register will
enable the soft connect pull up.
2017-06-06 14:39:00 -10:00
David Sidrane
cb62675b5e
Kinetis:sim ensure isolation of clock dividers for 0 value case
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This fixes a bug were a SoC does not have a clockdivN register
and passes a 0 for the init value. This prevents overflow of
the 0 decremented to -1 (0xffffffff) spilling over to other
clockdivN feilds.
2017-06-06 14:38:59 -10:00
David Sidrane
60c552ae0f
Kinetis:usbdev clean up ensuring proper use of HW.
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Remove magic numbers from code, documented the use of
undocumented bits.
Remove comments and code that were not appropriate for this
hardware.
Removed ifdef that's that were always compiled and removed code
blocks that were never compiled.
Ensure proper access order to hardware.
Per the reference manual: disable endpoints prior to configuring buffer
descriptor, then enable endpoints
Reorganize interrupt processing order to offload data after processing
errors.
Reorganize initialization so that there is a clear initialization phase,
reset phase for both the hardware and software structures.
By breaking the initialization into smaller pieces, the reset interrupt
only resets the resources within the controller that should be reset.
Rework suspend and resume logic so they perform properly
Made attach and detach functions optional. As they do not make sense for
a bus powered device.
Ensured the calls to up_usbinitalize up_usbuninitalize do not violate the
USB spec.
2017-06-06 14:38:59 -10:00
David Sidrane
c1a3208f83
Kinetis:Disable MPU when not in protected mode.
...
The hardware reset state of the the MPU precludes any bus
masters other then DMA access to memory. Unfortunately
USB and SDHC have there own DMA and will not have access to
memory in the default reset state.
This change disabled the MPU if present on system startup.
2017-06-06 14:38:58 -10:00
Gregory Nutt
4d46979a6f
Tiva SSI: Resolves issue 52 'Copy-Paste error in tiva_ssibus_initialize()' submitted by Aleksandr Kazantsev.
2017-06-01 06:38:47 -06:00
Juha Niskanen
ad6515563b
STM32L4 RTC: store RTC MAGIC to backup reg, not to address zero
2017-06-01 06:15:28 -06:00
Jussi Kivilinna
369b72f65a
stm32f7: Add SPI DMA support
2017-05-31 09:13:20 -06:00
Juha Niskanen
14c233a2f5
STM32L4: gpio: put back EXTI line source selection
2017-05-31 06:34:14 -06:00
David Sidrane
a077d0285b
Kinetis:Added ADC channel macro
2017-05-25 16:52:08 -10:00
David Sidrane
b407020968
Kinetis:Fixed typo in kinetis_adc.h
2017-05-25 16:51:25 -10:00
David Sidrane
488f42588b
Kinetis:Removed base address from kinetis_adc.h
2017-05-25 16:50:42 -10:00
Juha Niskanen
0c9abbfe67
STM32L4: Add IWDG peripheral. This is the same as for STM32 except that prescale and reload can be
...
changed after watchdog has been started, as this seems to work on L4.
2017-05-23 07:02:36 -06:00
Gregory Nutt
32eb5ca99a
Missed one change in the previous commit.
2017-05-21 15:02:00 -06:00
Gregory Nutt
7ffbb704d6
This is based on a patch by Taras Drozdovsky. Basically, the delay that was added during the integration of the CDC/ACM host driver was interfering with streaming audio. That delay was put there to prevent build endpoints from hogging the system bandwidth. So what do we do? Do we hog the bandwidth or do we insert arbitrarity delays. I think both ideas such.
2017-05-21 14:28:29 -06:00
Taras Drozdovsky
4ab2a3661e
STM32F4: add cs43l22 audio driver and i2s driver
2017-05-21 14:14:09 -06:00
Juha Niskanen
819a6e049e
stm32_i2c: make private symbols static
2017-05-19 07:16:01 -06:00
Gregory Nutt
989195cec8
STM32 Ethernet: Last patch breaks every board that does not use the KSZ80801 PHY.
2017-05-17 15:36:57 -06:00
Gregory Nutt
aac3a3df8e
STM32 Ethernet: Should not stm32_phyintenable() return a failure if it could not enable the PHY interrupt?
2017-05-17 10:07:09 -06:00
Sebastien Lorquet
2c6ea23aee
STM32 Ethernet: Add support for KSZ8081 PHY interrupts.
2017-05-17 10:04:49 -06:00
Juha Niskanen
8896f91f53
STM32L4: remove duplicate USART selects from Kconfig
2017-05-17 08:05:24 -06:00
Jussi Kivilinna
9169ff6a15
stm32_serial: fix freezing serial port. Serial interrupt enable/disable functions do not disable interrupts and can freeze device when serial interrupt is received while execution is at those functions.
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Trivially triggered with two or more threads write to regular syslog stream and to emergency stream. In this case, freeze happens because of mismatch of priv->ie (TXEIE == 0) and actually enabled interrupts in USART registers (TXEIE == 1), which leads to unhandled TXE interrupt
and causes interrupt storm for USART.
2017-05-17 06:50:46 -06:00
Lederhilger Martin
b8e7d5c455
I had the problem that the transmit FIFO size (= actual elements in FIFO) was slowly increasing over time, and was full after a few hours.
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The reason was that the code hit the line "canerr("ERROR: No available mailbox\n");" in stm32_cansend, so can_xmit thinks it has sent the packet to the hardware, but actually has not. Therefore the transmit interrupt never happens which would call can_txdone, and so the size of the FIFO size does not decrease.
The reason why the code actually hit the mentioned line above, is because stm32can_txready uses a different (incomplete) condition than stm32can_send to determine if the mailbox can be used for sending, and thus can_xmit forwards the packet to stm32can_send. stm32can_txready considered mailboxes OK for sending if the mailbox was empty, but did not consider that mailboxes may not yet be used if the request completed bit is set - stm32can_txinterrupt has to process these mailboxes first.
Note that I have also modified stm32can_txinterrupt - I removed the if condition, because the CAN controller retries to send the packet until it succeeds. Also if the condition would not evaluate to true, can_txdone would not be called and the FIFO size would not decrease also.
2017-05-16 07:47:18 -06:00
