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18352 Commits

Author SHA1 Message Date
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos
5b7ff03f40 lpc17_40: Fixed I2C port sanity check. 2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
51b24c4bad stm32/qenco: add support for QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
092a0c8453 stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit 
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
 2021-08-10 11:18:40 -03:00
raiden00pl
b0c9a6133e stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit 
STM32F3 has timers of the same length as in STM32F4.
 2021-08-10 11:18:40 -03:00
raiden00pl
3dd385ac0c stm32/qenco: add support for STM32G4 
This required generalization of RCC definitions that are not compatible with previous chips
 2021-08-10 11:18:40 -03:00
raiden00pl
21f59c874f stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 2021-08-10 11:18:40 -03:00
Sara Souza
af6c311fd1 risc-v/esp32-c3: Complete the support for RWDT 2021-08-10 11:17:15 -03:00
Sara Souza
61ab4f9f14 xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk 2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Daniel P. Carvalho
a7be1c9a2e stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop. 2021-08-05 14:48:44 -03:00
Michal Lenc
a3986eeba3 arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set 
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-05 09:57:49 -07:00
zhuyanlin
ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. 
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
 2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059 arch:xtensa:vector: fix typo error in level4_ventor 
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
 2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317 arch: xtensa: save current SP before overwrting in dispatch_c_isr. 
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
 2021-08-04 20:16:41 -07:00
Daniel P. Carvalho
2593089f84 stm32_dac: add support for DAC3 2021-08-04 20:22:58 +02:00
zhuyanlin
4fc5b62ec3 arch:xtensa: use letter 'i' in inline assemble constraint instead of I 
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
 2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80 arch:xtensa_testset: remove include arch/spinlock.h 
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
 2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218 arch:xtensa: add new GNU toolchain for xtensa. 
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
 2021-08-04 18:16:14 +02:00
Xiang Xiao
6a396eb224 Fix the printf warning after off_t change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
 2021-08-04 06:48:30 -07:00
Abdelatif Guettouche
238a96e7de arch/esp32_cpuint.c: Simplify up_disable/enable_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. 
This is used when dettaching.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP 
mode.  up_cpu_index already does that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
licheng
431df45e97 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-02 23:20:34 -07:00
Alexander Lunev
95abf562f4 boards: added a basic support for chipKIT Wi-FIRE board; 
added Sourcery CodeBench Lite for MIPS ELF Toolchain option;
corrected inaccuracies in Photon board and EMW3162 board README.txt files.
 2021-08-01 08:45:02 -07:00
buyuer
ae3709819c Use exit func iml host_abort. 
When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.

Signed-off-by: buyuer <dingddding@163.com>
 2021-07-31 08:02:10 -07:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
69df58c2e8 Replace __attribute__((no_instrument_function)) with noinstrument_function; 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
7bcd29dae0 Replace __attribute__((naked, no_instrument_function)) with naked_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
919f8a9a72 Define __ramfunc__ to "locate_code(".ramfunc") farcall_function noinline_function" 
instead of "__attribute__ ((section(".ramfunc"),long_call,noinline))"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
21b69cfd5d Replace all __attribute__((weak)) with weak_data/weak_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei
a7a922611b xtensa/esp32: Enable the allocation of multiple SPI Flash partitions 
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-29 20:17:13 +02:00
Alexander Lunev
98e7776714 pic32mz: added support for PIC32MZ2048EFG MCU 2021-07-29 07:46:26 -07:00
raiden00pl
f9937b28cc stm32g4: add CORDIC driver 2021-07-28 14:23:13 -03:00
raiden00pl
6128b298ee stm32g4: add CORDIC definitions 2021-07-28 14:23:13 -03:00
Sara Souza
cdbfacc1fe risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it 2021-07-27 20:43:34 -07:00
Sara Souza
857414e95d xtensa/esp32: expose SPI2 as a char driver 2021-07-27 09:55:49 -07:00
Michal Lenc
9fc806984c adc: add ioctl command to get the number of configured channels 
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 19:45:47 -07:00
Sara Souza
400d927011 xtensa/esp32s2: Disable wdt and wrap it. 2021-07-26 19:44:30 -07:00
Sara Souza
0794991a07 risc-v/esp32-c3: Disable wdt in the start function. 2021-07-26 19:44:30 -07:00
Sara Souza
5baeb7430b xtensa/esp32: Wrap wdt deinitialization in a function 2021-07-26 19:44:30 -07:00
Jiuzhu Dong
7e393762a7 sim/rptun: optimize multi-core startup and don't need to wait each other. 
Change-Id: I6172823c84a96e4082fa5f33bdb05d7bd1d3b056
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:38:07 -07:00
Gustavo Henrique Nihei
2d676f5e46 xtensa/esp32: Enable configuration of GPIO pad's drive strength 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-26 19:37:06 -07:00
Jiuzhu Dong
e98220c81a sim/cmdline: save boot cmdline to g_argc g_argv 
Change-Id: I989850a09528e3868957284c9f419d0992ae8d1f
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:35:58 -07:00
Xiang Xiao
5e01fe050a arch/sim: Copy include/nuttx/config.h to the local folder 
so the source code compiled by host environment can include config.h
directly and then avoid pass Kconfig option through Makefile manually

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf
 2021-07-27 07:44:33 +09:00
Xiang Xiao
3488a98bd7 sim: Correct the typedef in nuttx/hostfs.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5fbfd519417c5686325822549c068b1d42f83946
 2021-07-27 07:44:33 +09:00
Jiuzhu Dong
5029712283 renesas/rx65n: add long type for all PRI*PTR 
Error: wqueue/kwork_thread.c:202:3: error: format '%x' expects argument of type 'unsigned int',
 but argument 4 has type 'long unsigned int' [-Werror=format=]
    snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 08:44:05 -07:00
Michal Lenc
7354ab187e pwm: add option to break the loops when using multiple PWM channels 
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 10:34:16 -03:00
Nathan Hartman
b92aeb8209 Fix various typos 
arch/arm/src/eoss3/eoss3_serial.c:
arch/arm/src/imxrt/hardware/imxrt_flexcan.h:
arch/arm/src/imxrt/imxrt_flexcan.c:
arch/arm/src/imxrt/imxrt_flexpwm.c:
arch/arm/src/imxrt/imxrt_lpi2c.c:
arch/arm/src/kinetis/kinetis_flexcan.c:
arch/arm/src/nrf52/hardware/nrf52_rtc.h:
arch/arm/src/nrf52/nrf52_clockconfig.c:
arch/arm/src/nrf52/nrf52_radio.c:
arch/arm/src/nrf52/nrf52_tim.c:
arch/arm/src/rtl8720c/amebaz_depend.c:
arch/arm/src/s32k1xx/Kconfig:
arch/arm/src/s32k1xx/s32k1xx_flexcan.c:
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c:
arch/arm/src/sama5/hardware/sam_sdmmc.h:
arch/arm/src/sama5/sam_gmac.c:
arch/arm/src/samd5e5/sam_wdt.c:
arch/avr/src/avr32/up_exceptions.S:
arch/avr/src/avr32/up_fullcontextrestore.S:
arch/renesas/src/rx65n/rx65n_dtc.c:
arch/renesas/src/rx65n/rx65n_usbhost.c:
arch/risc-v/src/esp32c3/esp32c3_tickless.c:
boards/arm/stm32h7/stm32h747i-disco/include/board.h:
include/nuttx/lcd/ili9225.h:
libs/libc/stdio/lib_fgetpos.c:
libs/libc/stdio/lib_fseek.c:
libs/libc/stdio/lib_fsetpos.c:

    * Fix typos.
 2021-07-25 18:36:53 -07:00
hartmannathan
c475a71d1c Update arch/arm/src/stm32/Kconfig 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-07-25 14:16:22 -03:00
hartmannathan
bb5f302361 Update arch/arm/src/stm32l5/stm32l5_serial.c 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
 2021-07-25 14:16:22 -03:00
Nathan Hartman
f617c27a8c arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos. 
arch/arm/src/stm32/stm32_foc.c,
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h,
arch/arm/src/stm32h7/stm32_allocateheap.c,
arch/arm/src/stm32h7/stm32_fmc.c,
arch/arm/src/stm32h7/stm32_pmstandby.c,
arch/arm/src/stm32h7/stm32_spi.h,
arch/arm/src/stm32h7/stm32_spi_slave.c,
arch/arm/src/stm32h7/stm32_wwdg.c,
arch/arm/src/stm32l4/stm32l4_adc.h,
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h,
arch/arm/src/stm32l5/stm32l5_gpio.c,
arch/arm/src/stm32l5/stm32l5_gpio.h,
arch/arm/src/stm32l5/stm32l5_irq.c,
arch/arm/src/stm32l5/stm32l5_rcc.c,
arch/arm/src/stm32l5/stm32l5_rcc.h,
arch/arm/src/stm32l5/stm32l5_serial.c, and
arch/arm/src/stm32l5/stm32l5_spi.c:

    * Fix typos in comments. No functional changes.
 2021-07-25 14:16:22 -03:00
Nathan Hartman
3346ba304b arch: arm: stm32, stm32h7, stm32l5: Fix typos in KConfig help texts 
arch/arm/src/stm32/Kconfig:
* In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY:
  Fix typos in help text.

arch/arm/src/stm32h7/Kconfig:
* In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY,
  STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY,
  and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text.

arch/arm/src/stm32l5/Kconfig:
* In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix
  typos in help text.
 2021-07-25 14:16:22 -03:00
Nathan Hartman
d178ff8a02 arch: arm: stm: Fix STM32_EXTI2_OFFSET 
arch/arm/src/stm32/hardware/stm32_exti.h:
* Change STM32_EXTI2_OFFSET (offset to EXTI2 registers) from 0x18
  to 0x20. This symbol is defined when CONFIG_STM32_STM32F30XX or
  CONFIG_STM32_STM32F33XX. According to the current reference
  manuals for STM32F334xx (RM0364 rev 4) and STM32F302xx (RM0365
  rev 8), EXTI_IMR1 is at offset 0x00 and EXTI_IMR2 is at offset
  0x20, i.e., 0x20 apart. The same offset applies to the rest of
  the registers: EMR1/EMR2, RTSR1/RTSR2, etc.
 2021-07-24 16:53:14 +02:00
Michal Lenc
4985f47155 arch/arm/src/stm32/stm32_qencoder.c: print uint32_t by using standard format PRIx32 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-24 04:22:11 -07:00
jordi
b87333bae8 Kconfig: remove empty help sections 
To avoid the setconfig warning: "has 'help' but empty help text"
 2021-07-23 02:32:19 -07:00
jordi
1e44270558 Kconfig: add quotes in default string value 
To avoid the setconfig warning: "style: quotes recommended around
default value for string symbol"
 2021-07-23 02:32:19 -07:00
jordi
f3af6edf93 Kconfig: add quotes in source to clean warnings from setconfig 
To avoid the setconfig warning "style: quotes recommended around xxx in
source xxx"
 2021-07-23 02:32:19 -07:00
Masayuki Ishikawa
6d65e9f38e arch: sim: Add NuttX symbols to make SMP work correctly 
Summary:
- I noticed that sim:smp does not work correctly on macOS
  due to the recent changes
- Actually, it can not receive the IPI host signal, so if
  a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found that sim_cpu_start() calls pthread_attr_init()
  which locates not on the host OS but on the NuttX
- This commit fixes this issue by adding the symbol names
  to nuttx-names.in

Impact:
- sim in SMP mode
- NOTE: stack usage for CPU1/2/3 IDLE is still incorrect on macOS

Testing:
- Tested with ostest on Ubuntu 18.04 (x86_64) and macOS 11.4 (x86_64)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-22 09:03:30 -07:00
Masayuki Ishikawa
4f1e63f939 Revert "arch: sim: Workaround to make the IPI work on macOS" 
This reverts commit b68fc9eb1d.
 2021-07-22 09:03:30 -07:00
Xiang Xiao
2ef6428aa8 arch/sim: Don't need pass CONFIG_SCHED_INSTRUMENTATION to host side 
since this macro isn't check from host side after:
commit cee43ce280
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Fri Jul 16 02:23:59 2021 +0800

    arch/sim: Initialize the idle thread stack info correctly

    and change the default value of IDLETHREAD_STACKSIZE to 65536

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-22 07:59:58 -07:00
ligd
4919d9b7df arm: add up_secure_irq support 
Change-Id: Ibc9402dcef4045ca122da400940d57de6b508308
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-22 10:50:53 -03:00
ligd
29d6a6dcd3 arch: add depends to trigger_irq 
Change-Id: I334f625f8f1a6ebaa4fa5ea292de142a93120f51
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-22 10:50:53 -03:00
Masayuki Ishikawa
b68fc9eb1d arch: sim: Workaround to make the IPI work on macOS 
Summary:
- I noticed that sim:smp does not work correctly on macOS
  due to the recent changes
- Actually, it can not receive the IPI host signal, so if
  a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found the issue depends on pthread stack settings
  and perhaps it might affect the host signal handling.
- This commit fixes this issue by just reverting the pthread
  stack setting only for macOS.

Impact:
- sim:smp on macOS
- Stack usage for CPU1/2/3 IDLE will be incorrect

Testing:
- Tested with ostest on macOS 11.4 (x86_64)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-22 09:47:19 +02:00
Abdelatif Guettouche
e85b119363 arch/: Clean what was made during context in distclean. 
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued.  That's because `menuconfig` has a
`clean_context` on its way.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 16:52:36 -03:00
Abdelatif Guettouche
315ba8c77f esp32_allocateheap.c: Remove the amount reserved to himem from the heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-07-21 08:58:18 -07:00
Alan C. Assis
011c938116 Remove xtensa_backtrace.S reference from esp32s2 as well 2021-07-20 19:30:09 -07:00
Alan C. Assis
d2eeeee262 Fix xtensa_btdump() to look at the exception frame 
Remove xtensa_backtrace_start() since it is not used anymore
 2021-07-20 19:30:09 -07:00
David Sidrane
19fddc451c Kintis:LPUART add RX DMA 2021-07-20 19:28:51 -07:00
David Sidrane
34eb918665 kinetis:LPUART Add IOCTL for invert 2021-07-20 19:28:51 -07:00
Nathan Hartman
609ee6b54b Fix typos in comments and identifiers 2021-07-19 22:55:30 -03:00
ligd
aac0db368c ARM: fix CPSR corruption after exception handling 
It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:

    msr spsr, r1

GCC translates this to:

    msr spsr_fc, r1

As a result, not all SPSR fields are updated on exception return. This
should be:

    msr spsr_fsxc, r1

This bug has been fixed by Heesub Shin in:
343243c7c0

Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
 2021-07-19 08:41:06 -03:00
Gustavo Henrique Nihei
c05feda208 risc-v/esp32c3: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei
50ea22314e arm/lpc43xx: Implement MTDIOC_ERASESTATE for SPIFI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei
df2e890cfc xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-17 09:00:41 -07:00
Xiang Xiao
4444c13c14 arch/sim: The second CPU shouldn't call up_irqinitialize 
since the signal handler the process concept

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-17 07:48:27 +09:00
Xiang Xiao
98b5724b59 arch: Fix rtcb can't found error 
use the same condition check in declaration and reference

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
 2021-07-16 12:48:09 -03:00
Xiang Xiao
3204c75c1d arch/sim: Remove the unused sim_host_timer_handler 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icacbe74308580b7fc2449cdf9e41f85fce43d5a4
 2021-07-16 17:41:00 +09:00
ChenWen
2abb75fee7 risc-v/esp32c3: Fix some ESP32-C3 Wi-Fi driver issues 2021-07-15 23:20:29 -07:00
Roberto Bucher
fc810e3db4 Restored previous files 2021-07-15 23:19:59 -07:00
Xiang Xiao
cee43ce280 arch/sim: Initialize the idle thread stack info correctly 
and change the default value of IDLETHREAD_STACKSIZE to 65536

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ia54efbbca4b69706150bc4178844b316688a104e
 2021-07-16 08:37:53 +09:00
David Sidrane
da01a39e39 Revert "Kinetis:Serial No DMA Poll needed" 
This reverts commit e659ae83b0.

    It turns out the DMA polling is needed. The IDLE INT will
    not happen on repetitive signals.
 2021-07-15 12:28:04 -07:00
Daniel P. Carvalho
3ca46ea8e2 Change DAC driver to support STM32G4. 2021-07-15 14:33:15 -03:00
Fotis Panagiotopoulos
7f361daf60 lpc17_40: style fix in WDT definitions. 2021-07-13 08:32:42 -07:00
Michal Lenc
3d26c3efb6 fix nxstyle errors and warnings 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-13 09:55:29 -03:00
Michal Lenc
b2a9f853e8 arch/arm/src/imxrt: added support for Tickless OS 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-13 09:55:29 -03:00
Virus.V
063e1d6b74 risc-v/bl602: update wifi firmware and some fixup. 
1. Added check for repeated connection wifi operations.
2. Invoke the carrier on/off operation in the wrong place.
3. The RTC initialization time is incorrect.
4. Reserve 32K I-Cache space in the linker script.
5. Increase the size of the wifi firmware receiving buffer.

Signed-off-by: Virus.V <virusv@live.com>
 2021-07-13 05:12:12 -07:00
Sara Souza
48f2b10ee3 risc-v/esp32-c3: Use systimer 0 to RTOS TICK 2021-07-12 21:03:27 -07:00
Sara Souza
c7bf5c7a1d xtensa/esp32: Make UART TX DMA depends on EXPERIMENTAL and adds caveats regarding its use 2021-07-12 21:03:06 -07:00
Sara Souza
2abeba041d xtensa/esp32: Fixes termios issue. 2021-07-12 21:02:26 -07:00
Dong Heng
f5eaf82c93 risc-v/esp32c3: Use onexit to free thread private semaphore 2021-07-12 09:38:21 -03:00
Jiuzhu Dong
9b1f554429 sched: Dynamically extend the pid hash table 
Change-Id: I3a719bc575cd408cd530a39efa203f507b44fa9c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-11 19:42:30 -07:00
Xiang Xiao
5fe51b923a mm: Simplify the semaphore handling 
1.Move all special process to mm_takesemaphore
2.Remove the support of recurive lock
3.Remove mm_trysemaphore function

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ie216a6294ab67c5d427f31b089beb15c532f08fe
 2021-07-10 16:10:32 -03:00
ligd
f5279f8583 sim: fix loop add delaylist when mm_free in IDLE thread 
Change-Id: I1827c663275f47c9dc30d63e17e3d016b0000166
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-10 16:10:32 -03:00
Fotis Panagiotopoulos
61cb524fa2 lpc17_40: Fixed progmem driver. 2021-07-09 21:49:16 -07:00
Jerry_tang
1e3a985155 AmebaZ2: Add soc src code 
Add soc src code for rtl8720c

Signed-off-by: Jerry_tang <jerry_tang@realsil.com.cn>
 2021-07-09 14:29:06 -03:00
guowei15
95b5dc523e arm/setjmp.h:add c++ support 
N/A

Change-Id: I619cc15570adeff10f3a9b69bf9a3cff83e625c1
Signed-off-by: guowei15 <guowei15@xiaomi.com>
 2021-07-09 14:06:10 -03:00
David Sidrane
282ab797bf stm32h7:Ethernet Add some delays so that ifup() does not hog the CPU. 2021-07-08 21:14:29 -05:00
David Sidrane
70c9cd1508 stm32h7:ethernet add timeout on MAC reset 2021-07-08 21:14:29 -05:00
David Sidrane
bf4e97177a stm32h7:Ethernet fix formating 2021-07-08 21:14:29 -05:00
Xiang Xiao
e97ffb1f79 arch/armv7-a: Remove the special SMP SGI process 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Iaf7fe77a3ab7cbf145d907dafb0b7ca54cc4a012
 2021-07-09 07:53:05 +09:00
Daniel P. Carvalho
2692b61a72 Fix newline at end of file. 2021-07-07 21:34:58 -03:00
Daniel P. Carvalho
ea701a84f2 Fix comments. 2021-07-07 21:34:58 -03:00
Daniel P. Carvalho
2a21c45e0a Add STM32G43XX Analog Comparator driver. 2021-07-07 21:34:58 -03:00
Xiang Xiao
76cdd5c329 mm: Remove mm_heap_impl_s struct 
it's more simple to make mm_heap_s opaque outside of mm

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
 2021-07-07 04:25:15 -07:00
cgeng
d656417917 Fix compilation error when CONFIG_DEBUG_PWM_INFO on stm32h7 2021-07-07 03:46:31 -05:00
Alexander Lunev
8fd64854f5 stm32,stm32f7,stm32h7: supported ETH MAC promiscuous mode 2021-07-06 19:11:56 -03:00
Fotis Panagiotopoulos
9976635390 lpc17_40: fixed compiler warnings. 2021-07-06 06:17:59 -05:00
Sara Souza
a5bf47b93e xtensa/esp32: Fixes issue with UART 2 2021-07-05 23:20:26 -05:00
Sara Souza
d67852da4b xtensa/esp32: Change default pins of UART2 2021-07-05 23:20:26 -05:00
Dong Heng
475becac37 risc-v/esp32c3: Add board_ioctl and board_uniqueid 2021-07-05 23:12:17 -05:00
Fotis Panagiotopoulos
2f0b4eb363 lpc17xx: Added WDT driver. 2021-07-05 11:25:51 -05:00
Xiang Xiao
75bfa4584c mm: Add kmm_malloc_size and mm_malloc_size 
make malloc_size implementation align with malloc

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I8d7781925f06e58a880437a16569dccbfd2ea035
 2021-07-05 14:23:24 +09:00
Xiang Xiao
ddaa3e42b9 mm: Move the real implementation of mm_sbrk to sbrk 
and remove mm_sbrk and kmm_sbrk since it's wrong to expose
sbrk to other heaps except the default userspace heap.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-05 08:02:08 +09:00
Xiang Xiao
b3f568c216 boards/sim: Add asan config to test the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
4589c369be arch/sim: Implement mm_mallinfo for the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
8ebf9c92cf arch/sim: Implement malloc_size for the custom heap 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
f240b2e631 arch/sim: Remove host_malloc and host_calloc 
use host_realloc instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
97216c220b mm: Support malloc_size function 
and rename malloc_usable_size to malloc_size

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:53:44 -03:00
Xiang Xiao
0941bad877 note: Move up_schednote.c to drivers/note folder 
since it is general enough to work on other target

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 18:52:32 -03:00
Nathan Hartman
ce20211357 Fix various typos in comments and documentation 
Fix typos in these files:
    * Documentation/components/drivers/character/foc.rst
    * Documentation/guides/cpp_cmake.rst
    * Kconfig
    * arch/arm/src/imxrt/imxrt_lpspi.c
    * arch/arm/src/kinetis/kinetis_spi.c
    * arch/arm/src/kl/kl_spi.c
    * arch/arm/src/lpc31xx/lpc31_spi.c
    * arch/arm/src/nrf52/nrf52_radio.h
    * arch/arm/src/s32k1xx/s32k1xx_lpspi.c
    * arch/arm/src/stm32/Kconfig
    * arch/arm/src/stm32/stm32_adc.c
    * arch/arm/src/stm32/stm32_foc.c
    * arch/arm/src/stm32/stm32_foc.h
    * arch/arm/src/stm32/stm32_pwm.c
    * arch/arm/src/stm32/stm32_spi.c
    * arch/arm/src/stm32f0l0g0/stm32_spi.c
    * arch/arm/src/stm32f7/Kconfig
    * arch/arm/src/stm32f7/stm32_spi.c
    * arch/arm/src/stm32h7/Kconfig
    * arch/arm/src/stm32h7/stm32_allocateheap.c
    * arch/arm/src/stm32h7/stm32_fmc.c
    * arch/arm/src/stm32h7/stm32_fmc.h
    * arch/arm/src/stm32h7/stm32_pwm.c
    * arch/arm/src/stm32h7/stm32_qspi.c
    * arch/arm/src/stm32h7/stm32_spi.c
    * arch/arm/src/stm32l4/stm32l4_pwm.c
    * arch/arm/src/stm32l4/stm32l4_spi.c
    * arch/arm/src/stm32l5/Kconfig
    * arch/arm/src/stm32l5/stm32l5_spi.c
    * arch/renesas/src/rx65n/rx65n_dtc.c
    * arch/renesas/src/rx65n/rx65n_usbdev.c
    * arch/risc-v/src/rv32m1/rv32m1_serial.c
    * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c
    * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32h7/nucleo-h743zi2/README.txt
    * boards/risc-v/rv32m1/rv32m1-vega/README.txt
    * boards/sim/sim/sim/scripts/Make.defs
    * drivers/1wire/1wire.c
    * drivers/1wire/1wire_internal.h
    * drivers/lcd/Kconfig
    * drivers/syslog/ramlog.c
    * fs/fat/Kconfig
    * libs/libc/debug/Kconfig
    * libs/libc/machine/Kconfig
    * libs/libc/stdio/lib_libvsprintf.c
    * libs/libc/stdlib/lib_div.c
    * libs/libc/stdlib/lib_ldiv.c
    * libs/libc/stdlib/lib_lldiv.c
    * libs/libdsp/lib_observer.c
 2021-07-04 11:23:26 -05:00
SPRESENSE
b3389cf751 arch: cxd56x: Add support for power management debug output 
Add support for power management debug output.
 2021-07-04 00:36:07 -05:00
SPRESENSE
7af6b394de arch: cxd56x: Add Kconfig for power management debug output 
Add configurations for power management debug output to Kconfig.
 2021-07-04 00:36:07 -05:00
SPRESENSE
4738f69569 arch: cxd56x: pmic: Fix a compile error 
Replace undefined logerr to _err function.
 2021-07-04 00:36:07 -05:00
SPRESENSE
5c26d68f31 arch: cxd56x: Add a configuration for PMIC interrupts 
Add a configuration for PMIC interrupts to Kconfig.
 2021-07-04 00:36:07 -05:00
SPRESENSE
618661df93 arch: cxd56xx: Fix compile error when CONFIG_LIBM is disabled 
It is no longer necessary to define CONFIG_ARCH_MATH_H when we would
like to link libm.a other than nuttx math library. So, this commit
removes the error condition.
 2021-07-04 00:36:07 -05:00
SPRESENSE
d29db87bdc arch: cxd56xx: Add eMMC configuration for vendor-specific commands 
The eMMC driver for cxd56xx has been implemented a vendor-specific command
for Toshiba eMMC device, and so add a new configuration to enable the code.
 2021-07-04 00:36:07 -05:00
SPRESENSE
cd06fc9761 arch: cxd56x: sdhci: Minor fix configuration name 
Modify the referenced CONFIG to CONFIG_DEBUG_MEMCARD_INFO.
 2021-07-04 00:36:07 -05:00
SPRESENSE
6a2733dd05 arch: cxd56x: emmc: Minor fix undefined configuration name 
Replace obsolete CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_FS_INFO.
 2021-07-04 00:36:07 -05:00
SPRESENSE
fa12fe9df1 arch: cxd56x: scu: Fix some printf format warnings 
Fix some printf format warnings by -Wformat.
 2021-07-04 00:36:07 -05:00
SPRESENSE
845da344fd arch: cxd56xx: Fix compile warning 
Fix warning by -Wimplicit-function-declaration
 2021-07-04 00:36:07 -05:00
SPRESENSE
75b6a260e0 arch: cxd56xx: Rename to nxsem_set_protocol 
nxsem_setprotocol function name was changed to nxsem_set_protocol.
Replace and fix hostif compile error.
 2021-07-04 00:36:07 -05:00
SPRESENSE
4364a291f0 arch: cxd56xx: Use arm_arch.h instead of up_arch.h 
Use arm_arch.h instead of up_arch.h and fix hostif compile error.
 2021-07-04 00:36:07 -05:00
SPRESENSE
cb6ad9dfbd arch: cxd56xx: Fix getting stuck by nested spinlock in serial 
Fix an issue the serial console gets stuck in SMP caused by nested
spin_lock_irqsave.
 2021-07-04 00:36:07 -05:00
Xiang Xiao
a18b807fa9 arch/sim: Fix bt and audio simulation stop work in SMP mode 
by removing the SMP up_idle and sim_timer_handler

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-04 10:16:12 +09:00
Xiang Xiao
b1f711f790 mm: Move procfs_register_meminfo into common place 
to avoid the code duplication and ensure the consistent behaviour

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-03 09:39:32 -07:00
Masanari Iida
707404d415 rx65n: Add missing parameters in printf 
Printf format string requires 2 parameters, but 0
parameter was given. Add these missing parameters.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
 2021-07-03 09:25:57 -05:00
Dong Heng
4f2df0311d risc-v/esp32c3: Fix some BLE driver issues 
1. remove SMP functions because ESP32-C3 is singal core
2. disable phy_printf in ble adapter when enable Wi-Fi
3. fix BLE character device macro
 2021-07-03 07:28:30 -05:00
Masayuki Ishikawa
6370c820ea arch: rp2040: Introduce setintstack macro for SMP 
Summary:
- This commit introduces setintstack macro to rp2040
  which is used for SMP with interrupt stack

Impact:
- SMP with interrupt stack

Testing:
- Tested with raspberrypi-pico:smp
- NOTE: seed to set CONFIG_ARCH_INTERRUPTSTACK=2048

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-03 04:13:13 -05:00
Masayuki Ishikawa
9f206f2bb6 arch: armv6-m: Introduce setintstack macro 
Summary:
- This commit introduces setintstack macro which can be
  overridden for SMP with interrupt stack

Impact:
- SMP only

Testing:
- Tested with raspberrypi-pico:smp
- NOTE: more commits will be added later

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-07-03 04:13:13 -05:00
Virus.V
5f67d65e9e risc-v/bl602: add efuse driver 
Signed-off-by: Virus.V <virusv@live.com>
 2021-07-02 13:17:39 -05:00
ligd
f479ca9096 sim/smp: fix smp can't start, caused by signal too busy 
Change-Id: Ia9cad04759a869f9bed871fa0acd002115eefb0a
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-02 23:19:15 +09:00
ligd
2ab1dcf763 sim: add setitimer to nuttx-names.in 
Change-Id: Id6d91d81b3d67cbe9215eb94f4ef394d61156fe8
 2021-07-02 05:02:36 -05:00
ligd
a7a8c20083 sim: fix host_sleep unit error 
Change-Id: Iaddd6381eb9870b709147d33b36482ae2e37c04d
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-02 05:02:36 -05:00
ligd
36c1bba88c sim/up_oneshot.c: take host time as current 
Change-Id: I34625f3d3f9557a103017124388dba6104aba7cc
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-02 05:02:36 -05:00
ligd
92cd7628e0 sim: remove CONFIG_SIM_WALLTIME fast timing maybe harmful for IOs 
Change-Id: Ic4ff5ec0aa99d2d229a07c4d1a9a4dae738d3cd9
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-02 05:02:36 -05:00
ligd
aa43a0215d mm: fix memory corruption when loop create/exit thread in SMP mode 
Root casue:
when do thread exit, need add free stack operation to mm_delaylist,
but in SMP mode, CPU0 thread1 exit, at this time, CPU1 call malloc
and free mm_delaylist.

Fix:
Divide mm_delaylist for per CPU in SMP mode.

Change-Id: Ibf7d04614ea2f99fb5b506356b7346a0d94f0590
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-02 04:55:46 -05:00
ligd
50eee2f081 arm: fix enable interrupt too earlier caused system crash 
reason:
	msr	cpsr, r2   /* Set the CPSR */

    // interrupt hanppend, context switch

	pop	{r0-r2, pc}

resolve:
    use SPSR instead, and recover with ldmia ^

Change-Id: Id7cee6452997ec19919eeecf6e7616164b3a0ab3
Signed-off-by: ligd <liguiding1@xiaomi.com>
(cherry picked from commit 6fa6c1676932d7babb7ff22ef556a17bb18f1c0d)
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-07-01 22:20:36 -05:00
Fotis Panagiotopoulos
de213401a7 lpc17_40_progmem: fixed compilation issues. 2021-07-01 09:11:12 -05:00
Masanari Iida
839414987c efm32: Fix missing closing bracket 
This patch fixes missing closing bracket and semicolon.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
 2021-07-01 06:37:17 -07:00
Sara Souza
b45ccad6a0 xtensa/esp32: Adds support for SERIAL_TXDMA. 2021-07-01 01:50:13 -05:00
David Sidrane
e659ae83b0 Kinetis:Serial No DMA Poll needed 2021-07-01 01:44:46 -05:00
David Sidrane
78584b4569 kinetis:Serial use eDMA 
kinetis:serial mark priv->rxdma after use
 2021-07-01 01:44:46 -05:00
David Sidrane
e5a1b2e797 kinetis:SPI use eDMA 
Kinetis:SPI only allocate DMA once
 2021-07-01 01:44:46 -05:00
David Sidrane
78bf264af0 kinetis:Replace DMA 
Kinetis:DMAMUX use hex in mask
 2021-07-01 01:44:46 -05:00
David Sidrane
3439c40044 stm32h7:SDMMC fix reset of do_gpio 
For the case when the watchdog is triggering a timeout we did not
correctly reset the d0 GPIO.

Without this fix, the SD card can become inaccessible.
 2021-07-01 01:37:58 -05:00
Julian Oes
6d6ca8f0b6 stm32:sdio: fix wrong ifdefs 
This was wrong but presumably did not matter.
 2021-07-01 01:37:58 -05:00
Julian Oes
2a86335055 stm32:sdio: fix reset of GPIO_SDIO_D0 
For the case when the watchdog is triggering a timeout we did not
correctly reset the GPIO_SDIO_D0.

Without this fix, the SD card can become inaccessible.
 2021-07-01 01:37:58 -05:00
Julian Oes
665f847760 stm32f7: fix reset of d0_gpio 
For the case when the watchdog is triggering a timeout we did not
correctly reset the d0 GPIO.

Without this fix, the SD card can become inaccessible.
 2021-07-01 01:37:58 -05:00
Julian Oes
154795a247 stm32f7: Removed bit that is reserved for f7 2021-07-01 01:37:58 -05:00
Julian Oes
87fd8903a0 stm32f7: whitespace fix 2021-07-01 01:37:58 -05:00
Julian Oes
804445fc15 stm32f7: unify identical sdmmc.h header files 
It turns out there is no difference in these two files as well as the
reference manual for the registers between the two parts, so it probably
makes sense to unify them
 2021-07-01 01:37:58 -05:00
chenwen
31a6da2343 risc-v/esp32c3: Notifies networking layer whether the carrier is available 2021-06-30 23:09:34 -05:00
McKay Ransom
863834057b Renesas/RX: add RX setjmp, ARCH_RENESAS_RX, and RX65N ioctl 2021-06-30 23:01:57 -05:00
Sara Souza
87fabb2bc7 xtensa/esp32: Support to select different clock source for RTC controller and close TODOs. 2021-06-30 21:27:27 -05:00
Virus.V
84100128b2 risc-v/bl602: update wifi firmware version 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-30 01:08:10 -05:00
xiewenxiang
5fd3eca9c9 riscv/esp32c3: Support BLE sleep mode 2021-06-28 23:14:30 -05:00
xiewenxiang
145d917587 riscv/esp32c3: Add Wi-Fi and BLE coexist 2021-06-28 23:14:30 -05:00
xiewenxiang
8b96edc3a5 riscv/esp32c3: Add esp32c3 BLE driver 2021-06-28 23:14:30 -05:00
Michal Lenc
b36171026e arch/arm/src/imxrt/imxrt_flexpwm.c: fix mistake in submodules address offset 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-28 09:03:06 -05:00
Virus.V
8452c571ec risc-v/bl602: BLE firmware adapts to the new framework 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-28 07:03:04 -05:00
Virus.V
cd50650583 risc-v/bl602: Support AP and STA as independent network interface device 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-28 07:03:04 -05:00
Michal Lenc
addfe182ae arch/arm/src/imxrt: added support for FlexPWM driver 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-26 09:58:52 -05:00
Abdelatif Guettouche
553f070357 arch/xtensa/esp32: Remove up_textheap_init function since it's not 
needed anymore.

Decouple the IRAM heap from the text allocator since that heap can
still be used as a generic pool of memory.

Implement the up_extraheaps_init function to initialize all of the
additional heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Abdelatif Guettouche
add18b9592 arch/risc-v/esp32c3: Remove the up_textheap_init function since it's not 
needed anymore.

Implement the up_extraheaps_init function to initialize all separate
heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Abdelatif Guettouche
fc9c320bd8 arch/arm/cxd56xx: Remove the up_textheap_init function since it's not 
needed anymore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Abdelatif Guettouche
0a4982a80e Introduce ARCH_HAVE_EXTRA_HEAPS, this config is going to be used for 
chips that have multiple separate heaps.
For now it's used to enable APIs to initialize the different heaps
during the start sequence but can be extended for other purposes that
manage those heaps.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-26 09:52:43 -05:00
Gustavo Henrique Nihei
db18a12844 xtensa/esp32: Move RTC WDT deinit after initial setup 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-06-25 10:58:39 -03:00
Gustavo Henrique Nihei
8c70e4f1c1 xtensa/esp32: Fix RTC watchdog timer deinit at startup 
Write protection must be disabled before performing changes to the WDT
registers. Furthermore, the routine was resetting the wrong field from
the RTC WDT register.
The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
takes care of disabling it.
Then the 2nd stage bootloader enables the RTC WDT for checking the
startup sequence of the application image.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-06-25 10:58:39 -03:00
Xiang Xiao
ae9b5fd306 Replace mktime with timegm in rtc and fs driver 
since kernel component should use UTC instead local time

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icf939e1ab0af8e577105f539d2553bc67b3b3d10
 2021-06-23 13:43:32 -03:00
Abdelatif Guettouche
60da4317b9 arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for 
consistency.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
bdbc9ef04f arch/risc-v/esp32c3_rtc_heap.c: Correct the name of the procfs info 
variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
55a210d305 arch/xtensa/esp32_textheap.c: When allocating text prioritize alloacting 
from the RTC heap.  If that's not available fall back to the IRAM heap.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1e49f2929f arch/xtensa/src/esp32: Extract the IRAM region as a separate heap. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
1719e9df94 arch/xtensa/esp32: Add the RTC Slow memory as a separate heap. 
This memory region can be accessed by both I & D buses, so the heap can
be used for data storage and code execution.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
6582c19904 arch/xtensa/src/esp32/hardware/esp32_soc.h: Add a function to check if a 
buffer comes from the RTC Slow memory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-23 08:37:01 +09:00
Abdelatif Guettouche
a4289c4f84 xtensa/esp32_aes.c: Use the same output when testing the AES driver. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-21 06:23:55 -05:00
Masayuki Ishikawa
841fb02ac0 arch: esp32: Replace getcoreid with the latest esp-idf's 
Summary:
- I noticed that the getcoreid macro in the latest esp-idf
  is much simpler than the current NuttX's.
- This commit replaces the macro with the latest esp-idf's

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-21 06:21:39 -05:00
Alexander Lunev
f7c8875fd7 sdio,stm32h7: fixed an issue with not starting IDMA data transfer in case of IO_RW_EXTENDED command (CMD53); 
corrected setting SDMMC_DCTRL.DTMODE field for block data transfers ending on block count
and for block data transfers ending with STOP_TRANSMISSION command;
stm32_sdio: added more debug messages
 2021-06-21 02:47:46 -05:00
Liu Han
2dd081ed7d risc-v/esp32c3: Support ESP32-C3 SHA accelerator 2021-06-21 02:41:53 -05:00
chenwen
8648970994 esp32&esp32c3/wifi: Fix the issues of Wi-Fi configuration being overwritten 2021-06-19 08:00:35 -03:00
chenwen
ee3350ed1d risc-v/esp32c3: Disable Wi-Fi reconnect by default 2021-06-19 08:00:35 -03:00
chenwen
c3792f0aae xtensa/esp32: Support ESP32 RTC driver 2021-06-18 22:01:34 -05:00
Xiang Xiao
ab974edc84 sched: Identify the stack need to free by TCB_FLAG_FREE_STACK 
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
 2021-06-18 05:44:41 -07:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 07:14:17 -05:00
Abdelatif Guettouche
79e9347551 arch/risc-v/esp32c3/esp32c3_modtext.c: Prioritise allocation from the 
RTC heap when available.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
f54804bafc arch/risc-v/esp32c3: Create a separate heap for the RTC memory. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
7198b3ef4b risc-v/esp32c3/esp32c3_soc.h: Add a function to check if a pointer is 
within the RTC RAM range.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-18 00:53:42 -05:00
Daniel P. Carvalho
91e82d1597 Changed the STM32 Analog Comparator driver. 2021-06-18 00:50:24 -05:00
Sara Souza
00edeee1ff xtensa/esp32: Adds I2C Bit banging reset 2021-06-18 00:48:27 -05:00
Masayuki Ishikawa
83ac6cd399 arch: xtensa: Remove ISYNC from xtensa_compareset() 
Summary:
- According to the Xtensa ISA document, this ISYNC instruction
  between WSR SCOMPARE1 and S32C1I is unnecessary

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-17 09:58:29 -05:00
Masayuki Ishikawa
2d016f8d21 arch: xtensa: Fix the PS register handling 
Summary:
- I noticed that DEBUGASSERT sometimes happens in nxsem_wait()
  when testing Wi-Fi with esp32-devkitc:wsifi_smp
- The call stack was not from an interrupt handler and actually
  g_current_regs[] were correct, even though asserted with
  (up_interrupt_handler() == false)
- Finally, I found that we need to call rsync after we set
  a new value to the PS register which is described in the
  Xtensa document.
- This commit fixes this issue

Impact:
- All xtensa architectures

Testing:
- Tested with esp32-devkitc:wifi_smp and esp32-devkitc:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-17 09:58:29 -05:00
Sara Souza
8f59054ef2 risc-v/esp32c3: Adds I2C RESET support via hardware. 2021-06-16 21:22:26 -05:00
Michal Lenc
6dc3c3d1b2 arch/arm/src/imxrt: fix nxstyle warnings and errors 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-16 21:22:03 -05:00
Michal Lenc
7bcd50955f arch/arm/src/imxrt: add missing clock to imxrt_xbar.c and fix usage of imxrt_enc.c while debug option is enable 
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-06-16 21:22:03 -05:00
Janne Rosberg
673f9519eb risc-v/mpfs: add dma support 2021-06-16 12:22:54 -05:00
Eero Nurkkala
502210e98c riscv/mpfs: add i2c reset handler 
Add reset functionality into the mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-16 12:31:36 -03:00
Liu Han
04c805207a risc-v/esp32c3: Support ESP32-C3 efuse 2021-06-16 09:35:09 -03:00
retogaeh
f109a96ad2 Update arch/arm/src/stm32h7/stm32_adc.c 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-06-16 04:58:06 -07:00
GAEHWILER Reto
b9fba3edae stm32h7 fix adc port to handle overrun and the DR's fifo, adapt adc driver 
* port didn't know about data-register fifo
* port didn't handle overrun condition
* driver could get stuck if interrupts were skipped due to saturation
 2021-06-16 04:58:06 -07:00
Virus.V
69fce77718 risc-v/bl602: update firmware to fix undefined up_irq_* symbols when linking 
Signed-off-by: Virus.V <virusv@live.com>
 2021-06-15 23:25:16 -05:00
Dong Heng
60fb1adaca riscv: Add inline IRQ process functions 
Remove functions from RISC-V chips.
 2021-06-15 23:25:16 -05:00
Xiang Xiao
2e49e1bc5c mtd: Add MTDIOC_FLUSH IOCTL like MTDIOC_XIPBASE 
since the old design reuse BIOC_FLUSH for
MTD device which make some confusion

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-15 13:26:45 -03:00
Sara Souza
2a7b97c0cd risc-v/esp32-c3: Adds I2C polled support 2021-06-15 10:51:18 -05:00
Daniel P. Carvalho
4b351fc447 Adds PWM example to nucleo-g431kb board. 2021-06-14 18:45:04 -03:00
Liu Han
8eaaf6d462 risc-v/esp32c3: Support ESP32-C3 RSA accelerator 2021-06-14 15:03:11 -03:00
Yuichi Nakamura
9b8e81ebc1 arm/rp2040: Fix warnings when UART console is not used 2021-06-14 09:05:19 -03:00
Yuichi Nakamura
b860e3c4ad arm/rp2040:USB device controller support 
Summary:
- Add Raspberry Pi Pico (RP2040) USB device controller support.
- Confirmed that CDC/ACM, MSC and these composite device are working.
- The current implementation have an unresolved issue and some workaround
  for USB MSC SCSI driver is required.
  See the comment in the patch "usbmsc: Add USBMSC_NOT_STALL_BULKEP for RP2040 workaround".

Impact:
- RP2040 only

Testing:
- Tested with Windows 10 and Ubuntu-18.04/20.04 as the USB host.
- Tested configurations:
  - raspberrypi-pico:usbnsh
  - raspberrypi-pico:usbmsc
  - raspberrypi-pico:composite
 2021-06-14 09:05:19 -03:00
Sara Souza
7300bc8f1c xtensa/esp32: Adds I2C polled support. 2021-06-13 05:04:51 -05:00
Masayuki Ishikawa
bafac8b560 arch: k210: Fix stack coloring for the idle thread stack 
Summary:
- I noticed that stack coloring for the idle thread stacks does
  not work due to the recent changes
- This commit fixes this issue

Impact:
- k210 only

Testing:
- Tested with both maix-bit (dev board) and QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-12 05:54:08 -05:00
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver 
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 21:03:42 -05:00
Daniel P. Carvalho
361703a881 Added basic support for nucleo-g431kb board. 2021-06-11 20:51:56 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver 
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-06-11 09:10:03 -05:00
Abdelatif Guettouche
96bcf7678b risc-v/esp32c3_wifi_adapter.c: Remove a config that's only used in 
Xtensa chips.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-11 10:49:52 -03:00
Jiuzhu Dong
2fd25d7ea7 arch/armv7-a: Colorize the idle thread stack for other cpu(SMP) 
Keep previous modification.

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-06-11 01:26:50 -05:00
raiden00pl
d76f8ea04a arch/arm/src/stm32/stm32_foc.c: add workaround for an issue found in STM32G4 family 
From G4 erratas: "ADC channel 0 converted instead of the required ADC channel"
 2021-06-10 13:58:33 -03:00
raiden00pl
7c47f32a19 arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h: rename OPAMP pins to match the manual 2021-06-10 13:58:33 -03:00
raiden00pl
76824ba2a9 stm32g4xxxx_memorymap.h: remove invalid OPAMP1-6 definitions 2021-06-10 13:58:33 -03:00
raiden00pl
af0f2b4f37 stm32g4: add OPAMP defs 2021-06-10 13:58:33 -03:00
Alexander Vasiljev
9d0da9818c arch/arm/src/stm32h7: qspi use indirect write instead indirect read without data. 2021-06-10 10:46:34 -05:00
Virus.V
7c20199a61 riscv/bl602:replace syslog to debugging log macros 2021-06-10 08:59:16 -05:00
Fotis Panagiotopoulos
2ef90786c8 setjmp.h: Added missing include. 2021-06-10 08:58:52 -05:00
Xiang Xiao
c0fdddc5d7 arch: Remove all go_nx_start from chip specifc source 
since the idle stack color is done in the common code now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-10 06:50:41 -07:00
Xiang Xiao
fa0d123f87 arch: Colorize the idle thread stack in an unified way 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Idae8da53e5a4799a8edc0e882f17fd515b70cb14
 2021-06-10 06:50:41 -07:00
Chen Wen
dbf9c87a42 risc-v/esp32c3: Support ESP32-C3 RTC driver 2021-06-10 09:33:04 -03:00
Alexander Vasiljev
45672c269d Make: use gcc as LD 2021-06-10 03:43:18 -07:00
Peter van der Perk
3b94669b7f FlexCAN Fix TX abort process 2021-06-09 13:34:13 -05:00
Xiang Xiao
6576306bca arch: Rename xxx_getsp to up_getsp 
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-09 10:20:02 -07:00
Juha Niskanen
939e547ca8 arch/arm/src/stm32l4: fix some printf format errors and warnings 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-06-09 11:52:33 -05:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-08 13:06:08 -07:00
David Sidrane
131e2490c9 stm32f7:bbsram add assert header 2021-06-08 13:19:22 -05:00
David Sidrane
a1de902708 stm32h7:bbsram add assert header 2021-06-08 13:19:22 -05:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Gustavo Henrique Nihei
0b3c2c7603 spi: Refactor SPI Slave interface prefix to sync with I2C Slave 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
27782aca19 risc-v/esp32c3: Include missing debug.h header 2021-06-05 04:50:34 -07:00
Gustavo Henrique Nihei
77dfb39260 risc-v/esp32c3: Uniformize references to CPU interrupt ID 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
f53306f9af risc-v/esp32c3: Ensure internal linkage of interrupt map 2021-06-04 23:26:13 +01:00
Gustavo Henrique Nihei
a2bcffde73 risc-v/esp32c3: Remove unused macros 2021-06-04 23:26:13 +01:00
Abdelatif Guettouche
2d55f2659e riscv/esp32c3: Add module text allocator. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
778e3ed4ad arch/risc-v/rv32im/riscv_assert.c: Provide dummy definitions of dump 
functions when ARCH_STACKDUMP is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Abdelatif Guettouche
94ded7a695 arch/riscv/rv32im/riscv_assert.c: Fix preprocessor condition. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-06-04 12:20:18 -05:00
Janne Rosberg
7b882c3588 risc-v/mpfs: fix ext irq 1-12 
Handle irq numbers 1-12 correctly
 2021-06-04 10:14:58 -05:00
Jani Paalijarvi
ebdc7a06b1 risc-v/mpfs: add MSTimer register offsets and bitmasks 2021-06-04 10:14:58 -05:00
Janne Rosberg
f7cbed0256 risc-v/mpfs: enable up_systemreset() 2021-06-04 10:14:58 -05:00
Janne Rosberg
ec11643394 risc-v/mpfs: add sysreg register defines 
This adds minimal set of sysreg defines for MPFS
 2021-06-04 10:14:58 -05:00
Masayuki Ishikawa
386946ee54 arch: cxd56xx: Fix address mapping in cxd56_modtext.c 
Summary:
- I noticed that DEBUGASSERTION() happens when executing
  an ELF application
- This commit fixes this issue by re-mapping the address
  to SYSBUS in up_module_text_free()

Impact:
- None

Testing:
- Tested with spresense (both DEBUG_ASSERTIONS=n and y)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-04 01:40:37 -05:00
Masayuki Ishikawa
f0b689a063 arch: arm: Add select ARCH_HAVE_MODULE_TEXT to ARCH_CHIP_CXD56XX 
Summary:
- I noticed that make savedefconfig shows warnings regarding
  'unmet direct dependencies (ARCH_HAVE_MODULE_TEXT)'
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with spresense:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-04 01:40:37 -05:00
Jaroslav Beran
d13be4ea57 samv7/spi: Allow 16-bit word size in spi_send 
Signed-off-by: Jaroslav Beran <jara.beran@gmail.com>
 2021-06-03 21:33:52 -05:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Kazuya Hioki
038941b11d arch: cxd56xx: Fix a register name in cxd56_sdhci.c 
Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
cfe6e313fb arch: cxd56xx: Introduce up_testset2 in cxd56_testset.c 
Summary:
- In cxd56xx, ldrex/strex behavior is slightly different from
  other Arm architectures. Dummy strex must be issued to release
  the exclusive load & store unit.

Impact:
- SMP only

Testing:
- Tested with spresense:smp
- Tested with spresese:wifi_smp, spresense:rndis_smp
- NOTE: CONFIG_CXD56_TESTSET=y must be removed from defconfigs

Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
2fc6361231 arch: cxd56xx: Introduce CXD56_PHYSADDR 
Summary:
- This commit converts data to the physical address for DMA transfer.

Impact:
- cxd56_dmac.c, cxd56_sdhci.c, cxd56_usbdev.c
- cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c

Testing:
- Tested with following configurations
- spresense:wifi, spresense:wifi_smp, spresense_rndis, spresense_rndis_smp
- NOTE: additional commits are needed for the test
- NOTE: cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c are not tested

Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
a6572fc8c9 arch: cxd56xx: Use uintptr_t for srcend/dstend in dma_descriptor_s 
Summary:
- This commit uses uintptr_t for srcend/dstend in dma_descriptor_s

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
4ba5740c6e arch: cxd56xx: Introduce CONFIG_CXD56_USE_SYSBUS in Kconfig 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
8c97db37e0 arch: cxd56xx: Introduce cxd56_modtext.c 
Summary:
- This commit introduces cxd56_modtext.c to allocate a separate
  text memory for ELF

Impact:
- None

Testing:
- Tested with spresense:elf

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Masayuki Ishikawa
588deffb6c arch: cxd56xx: Adjust loops per msec for the new memory map 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-06-02 22:13:10 -05:00
Xiang Xiao
281921bcf9 arch: Flush syslog buffer for sim and x86_64 arch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:27:24 +09:00
David Sidrane
9b29641bf5 s32k1xx:eeprom fix missing debug.h 2021-06-02 17:36:06 -03:00
Sara Souza
7dd131b4c1 xtensa/esp32: Fixes support for HW flow control 2021-06-02 09:55:50 -05:00
Sara Souza
a54fe4ee1e xtensa/esp32-s2: Add support for serial HW flow control. 2021-06-01 21:37:37 -05:00
Sara Souza
b54be4e946 risc-v/esp32-c3: Add support for HW flow control. 2021-06-01 21:37:27 -05:00
Gustavo Henrique Nihei
24c206b3f8 risc-v/esp32c3: Add DMA support for the SPI Slave controller 2021-06-01 21:37:09 -05:00
Gustavo Henrique Nihei
15a93ae974 risc-v/esp32c3: Remove Master-only settings on SPI Slave driver 2021-06-01 21:37:09 -05:00
Alan C. Assis
929a4a7278 Fix dangling whitespace at the end of line 2021-06-01 07:49:54 +02:00
Sara Souza
f1d653c08c xtensa/esp32-s2: Adds support for serial driver, lowputc and termios. 2021-06-01 07:49:54 +02:00
Alan C. Assis
06795a221a Clean ESP32S2 Xtensa files 2021-06-01 07:49:54 +02:00
Abdelatif Guettouche
fccd5fbdd2 esp32s2_allocateheap.c: Use the address of the ROM data from the ROM linker script. 2021-06-01 07:49:54 +02:00
Alan C. Assis
7767acd24a Add initial ESP32S2 Xtensa support 2021-06-01 07:49:54 +02:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-01 06:42:02 +09:00
Gustavo Henrique Nihei
1530b0f639 risc-v/esp32c3: Fix overwriting of registered-but-disabled interrupts 2021-05-31 09:15:40 -05:00
Gustavo Henrique Nihei
da78cf78eb risc-v/esp32c3: Remove useless parameter from DMA macro 2021-05-31 09:14:14 -05:00
chao.an
99bfd355c7 serial/uart/h4: add bt h4 uart serial driver 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
chao.an
6c69b12000 wireless/bluetooth: decoupling bt_driver_s and bt_buf_s 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
chao.an
6837d4e1ba arch/sim: remove BT uart implement 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-31 09:50:54 -03:00
Gustavo Henrique Nihei
7e15d897bd risc-v/esp32c3: Add driver for SPI Slave controller 2021-05-31 12:54:15 +01:00
chenwen
1d1dd8512f esp32&esp32c3/wifi: Support specific channel and bssid scan 2021-05-31 11:09:19 +01:00
Alin Jerpelea
02b244cb6f arch: arm: update licenses to Apache 
Sebastien Lorquet has submitted the CLA

Uros Platise has submitted the CLA

Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
7e84ea3104 arch: renesas: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
3b87c32bcc arch: or1k: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Alin Jerpelea
5a37ddfbe6 arch: misoc: update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-05-31 01:37:27 -05:00
Jiuzhu Dong
dab99acfe3 sim/rptun: support multi(>2) core interactive by share memory 
N/A

Change-Id: Ia8254bfe369e40a04ed54adfa64afa38974b165c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-30 23:28:40 -05:00
Abdelatif Guettouche
45d01ae2a8 arch/xtensa/esp32_emac.c: Call phy_enable_interrupt correctly. 2021-05-28 20:46:27 -03:00
Han Raaijmakers
04d81b24e3 S32K1XX LSPI Double word up to 64 bits support 2021-05-27 11:37:46 -07:00
Abdelatif Guettouche
e29da149e3 arch/riscv/src/esp32c3/esp32c3_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
08aa9ce540 arch/xtensa/src/esp32/esp32_rt_timer: Fix typos and re-word some 
comments.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
0f3d94e8e8 arch/risc-v/src/esp32c3/esp32c3_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Abdelatif Guettouche
f24a687f8e arch/xtensa/src/esp32/esp32_rt_timer.h: Add section headers. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-27 05:01:54 -07:00
Virus.V
c6317650f9 risc-v/bl602: Add RTC support 2021-05-26 20:03:19 -03:00
Gustavo Henrique Nihei
1d940b2982 risc-v/esp32c3: Constify DMA descriptor pointer to buffer 2021-05-26 14:05:27 -03:00
Gustavo Henrique Nihei
29cae80533 risc-v/esp32c3: Fix DMA TX Burst being set to input register 2021-05-26 14:05:27 -03:00
Dong Heng
73dcbac09d riscv/esp32c3: Add ESP32-C3 AES driver 2021-05-25 11:02:59 -03:00
Masayuki Ishikawa
88c6524d7c arch: imx6: Add termios support to imx6 
Summary:
- This commit adds termios support to imx6

Impact:
- None

Testing:
- Tested with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-05-25 07:17:29 -05:00
Govind Singh
2975050c96 arch/riscv/bl602: Fix typo in i2c driver 
Signed-off-by: Govind Singh <govind.sk85@gmail.com>
 2021-05-25 01:37:28 -05:00
Janne Rosberg
d6205642ab add support for PolarFire SoC and icicle board 
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2021-05-24 22:55:44 -05:00
Sara Souza
3144a5a272 xtensa: Fixes names of serial functions 2021-05-24 10:04:50 -05:00
Xiang Xiao
001e7c3e76 sched: Don't include nuttx/sched.h inside sched.h 
But let nuttx/sched.h include sched.h instead to
avoid expose nuttx kernel API to userspace.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-05-24 12:11:53 +09:00
Dong Heng
76df958e34 riscv/esp32c3: Support SPI Flash encryption read/write 2021-05-23 08:37:25 -03:00
David Sidrane
86523318fc stm32f7:i2c use inttypes 2021-05-22 08:53:07 -05:00
David Sidrane
8596fdd0bf stm32h7:i2c use inttypes 2021-05-22 08:53:07 -05:00
Alan C. Assis
1a84314f5d xtensa: #ifdef SYMBOL is always true if SYMBOL defined as 0 2021-05-22 08:35:12 -05:00
Huang Qi
f4a0b7aedd libc: Call pthread_exit in user-space by up_pthread_exit 
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.

* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Huang Qi
81a01d089b libc/pthread: Fix comment and document issue 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2021-05-21 22:46:52 -06:00
Gregory Nutt
bb9b58bdde libc: Move pthread_create to user space 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: I5c447d94077debc79158686935f288e4c8e51e01
 2021-05-21 22:46:52 -06:00
chao.an
6c40185985 arm/v7-a/fpu: add VFP-v3 D32 support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-05-21 09:55:00 -03:00
Jukka Laitinen
e4fd99682e rv64gc: use PRIx64 format for alert and assert 
This fixes compilation warnings caused by number formatting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Jukka Laitinen
e79a45bb93 rv64gc/riscv_assert.c: Fix compilation without CONFIG_DEBUG_ALERT 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2021-05-20 05:42:01 -05:00
Anthony Merlino
c9ccbb9e03 stm32h7xxxx_rcc.c: Fixes typo in comment 2021-05-20 00:53:49 -07:00
Anthony Merlino
35553147ba stm32h7 rcc: Sync h7x7xx and h7x3xx. Changes are relevant to both 2021-05-20 00:53:49 -07:00
SPRESENSE
6b5a4cbfd3 arch: cxd56xx: Fix parameter check of hostif buffer 
Fix a parameter check of the buffer attribute in opening hostif driver.
 2021-05-20 07:23:48 +02:00
SPRESENSE
db9c94962b arch: cxd56xx: Add host interface driver 
Add host interface driver which supports I2C or SPI slave feature.
 2021-05-20 07:23:48 +02:00
SPRESENSE
5a7a118320 arch: cxd56xx: Fix uninitialized variable for gnss driver 
Fix uninitialized variable in gnss driver.
CodeSonar Warning 518288 - 518292
 2021-05-20 07:23:48 +02:00
SPRESENSE
151fec4e98 arch: cxd56xx: Do not re-initialize the console for subcore 
If the subcore configuration, which is mainly used in the Spresense
Arduino environment, is enabled, the serial console has been already
initialized by maincore. Then, don't need to re-initialize the UART1
serial driver.
 2021-05-20 07:23:48 +02:00
SPRESENSE
efd4789b72 arch: cxd56xx: gauge: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
50cb0306b6 arch: cxd56xx: charger: Use the dedicated debug macro 
Replace to the battery dedicated debug macro instead of standard one.
 2021-05-20 07:23:48 +02:00
SPRESENSE
bb348cc464 arch: cxd56xx: gnss: Fix compile error in debug log 
Fix compile error when debug log is enabled.
Replace debug message from obsolete logerr() to _err().
 2021-05-20 07:23:48 +02:00
SPRESENSE
6d3fb9ee81 arch: cxd56xx: wdt: Fix compile error in debug log 
Fix compile error when CXD56_WDT_REGDEBUG is enabled.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f0cae6cdf3 arch: cxd56xx: Fix multiple open and close ADC driver 
ADC driver does not support multiple open and close. It causes the memory
corruption by multiple free. This commit fixes this problem by introducing
the reference counter.
 2021-05-20 07:23:48 +02:00
SPRESENSE
98871e58af arch: cxd56xx: Fix gnss open error by clock change 
If the system clock is changed during loading gnssfw, gnss open may be
failed. So this commit prohibits clock change until loading gnssfw is
completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
e26da5f564 arch: cxd56xx: Update isop firmware 
Update isop firmware which supports for the error handling and i2c
multi-master environment.
 2021-05-20 07:23:48 +02:00
SPRESENSE
f548ffa7a7 arch: cxd56xx: Support execution error by SCU sequencer 
Enable interrupt by SCU sequencer execution error. If the interrupt
occurs, then it stops the sequencer and returns the error code.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ba6201401f arch: cxd56xx: Remove unnecessary i2c settings 
Remove slave address register setting that is unnecessary for the
transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00
SPRESENSE
ade26c17d2 arch: cxd56xx: Update i2c register initialization 
Enable RX_FIFO_FULL_HLD_CTRL and RESTART of i2c control register in
i2c initial settings for transfer by SCU sequencer.
 2021-05-20 07:23:48 +02:00
SPRESENSE
a10a4c483f arch: cxd56xx: Add SCU register definitions 
Add SCU register definitions.
 2021-05-20 07:23:48 +02:00
SPRESENSE
09cc6b780b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20175
 2021-05-20 07:23:48 +02:00
SPRESENSE
a276de741f arch: cxd56xx: Fix SPI setmode function 
When SSP mode is changed, SSE bit of SSPCR1 register must be disabled.
 2021-05-20 07:23:48 +02:00
SPRESENSE
89fd987a1a arch: cxd56xx: Fix RTC alarm cancellation process 
There is an issue that the next alarm is expired immediately after
canceling a RTC alarm. Fixed alarm settings to be completely cleared
when canceling an RTC alarm.
 2021-05-20 07:23:48 +02:00
SPRESENSE
67a56410ee arch: cxd56xx: Prohibit clock change during SPI transfer 
If the system clock is changed during the SPI transfer, the SPI data can
be corrupted. So this commit prohibits the clock change during SPI transfer,
and keep the clock until the transfer is completed.
 2021-05-20 07:23:48 +02:00
SPRESENSE
db340a8941 arch: cxd56xx: Support for suppresion of clock change 
Introduce PM_CPUFREQLOCK_FLAG_HOLD into the frequency lock mechanism in
power manager, which is used to keep the current frequency without clock
change, for example, during the transfer of a periphral.
 2021-05-20 07:23:48 +02:00
SPRESENSE
9b3a80cc37 arch: cxd56xx: Fix uart getting stuck during a clock change 
UART driver is stopped and re-started during a clock change. When a UART
interrupt is generated in each process, the unexpected behavior will
occur and a console will get stuck with UART driver. This commit fixed
each process is performed atomically.
 2021-05-20 07:23:48 +02:00
jordi
ccc8c078f9 xtensa/esp32: Fix warning "is not defined" 
Detected with "-Werror" flag
 2021-05-19 20:03:03 +01:00
Anthony Merlino
e37ce7677b Try to address CI build error and a few macro fixes. 2021-05-19 10:41:18 -07:00
Anthony Merlino
b54a4c7788 Replace more ATIM_/BTIM_ macros with GTIM_ macros 2021-05-19 10:41:18 -07:00
Anthony Merlino
58c92be39c stm32 timers: Make some register operations more readable. 2021-05-19 10:41:18 -07:00
chenwen
9a99d813fa risc-v/esp32c3: Support ESP32-C3 auto-sleep 2021-05-19 07:00:40 -03:00
Chen Wen
e44ec9e48e xtensa/esp32: Fix code nxstyle issue 2021-05-19 06:45:42 -03:00
chenwen
f7db743152 xtensa/esp32: Support auto-sleep 2021-05-19 06:45:42 -03:00
chenwen
f50160f0e1 xtensa/esp32: Support tick-less OS 2021-05-19 06:45:42 -03:00
Abdelatif Guettouche
65e9ff5a48 xtensa/esp32/esp32_start.c: Remove an old and unnecessary piece of code. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-19 03:05:52 -05:00
Dong Heng
f12de4f7d9 riscv/esp32c3: Add ESP32-C3 ADC driver 2021-05-18 09:20:46 -03:00
Gustavo Henrique Nihei
26a5cb2094 risc-v/esp32c3: Add support for DMA transfers on SPI driver 2021-05-17 13:21:12 +01:00
Gustavo Henrique Nihei
132ffdd28d risc-v/esp32c3: Add burst transfer support for GDMA 2021-05-17 13:21:12 +01:00
Dong Heng
4a7f998c33 riscv/esp32c3: Fix RT timer issues 
1. Enable alarm if there is timer active
2. Wake up main thread to delete timer
3. Wake up main thread when timer is timeout in ISR
 2021-05-16 13:23:43 -05:00
Anthony Merlino
fa2b9ca43b stm32/stm32f7 tickless: Fix up_timer_getmask to be correct for the width of the timer. 2021-05-16 13:04:31 -05:00
Anthony Merlino
99a9d75cdd stm32f7: Remove references to BOARD_ENABLE_USBOTG_HSULPI. Prefer Kconfig option instead. 2021-05-16 01:02:51 -07:00
Jiuzhu Dong
73cc1f8884 driver/rtc: add config CONFIG_RTC_RPMSG_SERVER to 
N/A
select rtc rpmsg role.

Change-Id: I7f9053b070593573caa5d988c6a2e13593da6bc5
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
f082893b9a driver/rtc: add config RTC_RPMSG_SERVER_NAME to 
specified the name of remote proc(rpmsg server)

Change-Id: I0086bb43727a2bbb5e68f88907b5e4608182ef9c
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 14:33:52 -03:00
Jiuzhu Dong
ff567124d3 driver/syslog: add config SYSLOG_RPMSG_SERVER_NAME to 
N/A

specified the name of remote proc(rpmsg server)

Change-Id: Ie270d651071e87a40a80ab489597ae18db9814f0
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-05-15 09:39:57 -03:00
Dong Heng
beed26b6bf riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver 2021-05-15 08:38:37 -03:00
chenwen
16667930cb risc-v/esp32c3: Support ESP32-C3 PM standby and sleep 2021-05-12 10:15:06 -03:00
Juha Niskanen
abcb67a292 Remove final remaining CONFIG_DISABLE_SIGNALS and CONFIG_DISABLE_SIGNAL 2021-05-10 17:04:38 -03:00
Nathan Hartman
8af9d39667 Documentation, comments: Minor improvements and typos fixed 2021-05-09 19:12:13 -07:00
David Sidrane
17b786399c stm32:SDIO:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
3e49d49cd9 stm32h7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
David Sidrane
c45e03b75f stm32f7:SDMMC:Use 250 Ms Data path timeout, regardless of Card Clock frequency 2021-05-07 17:39:08 -04:00
Gustavo Henrique Nihei
90a4e8d718 risc-v/esp32c3: Fix DMA channels' interrupt IDs 2021-05-07 16:46:41 -03:00
Dong Heng
bd8e37bb4b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing 2021-05-07 16:46:41 -03:00
Harri Luhtala
e5f1069654 arch/arm/src/stm32l4/hardware/stm32l4xrxx: pinmap alternative function for SPI2 2021-05-07 05:08:05 -07:00
Raman Gopalan
9044594545 at32uc3_gpioirq.c: Fix typo: contex -> context 2021-05-06 11:25:38 -03:00
Gustavo Henrique Nihei
534c058d93 spi: Adopt CPHA as the abbreviation for clock phase 2021-05-05 16:56:07 -03:00
David Sidrane
92dba32c8c stm32h7:Allow for reuse of the OTG_ID GPIO 
Currently Nuttx doesn't seem to be any real support for OTG.
    In the future when OTG is supported. This Knob can be removed
    and drivers can enable their pin sets based on CONFIG_OTG.
    (Adding CONFIG_OTG at this time would be misleading.)
 2021-05-05 12:22:11 -04:00
David Sidrane
cd603af958 stm32f7:Allow for reuse of the OTG_ID GPIO 2021-05-05 12:22:11 -04:00
David Sidrane
8624f9a444 s32k1xx:flexcan Use inttypes in printing macro 2021-05-05 06:07:50 -07:00
David Sidrane
7fb59e4f36 kinetis:flexcan Use inttypes in printing macro 2021-05-05 06:07:50 -07:00
David Sidrane
e5ceb062f9 stm32f7:Use inttypes in printing macro 
stm32f7:SDMMC Use inttypes in printing macro

stm32f7:CAN Use inttypes in printing macro

stm32f7:DMA Use inttypes in printing macro

stm32f7:serial fix compile error from UNUSED() change
 2021-05-05 06:07:50 -07:00
David Sidrane
cbe3e120d5 stm32h7:Use inttypes in printing macros 2021-05-05 06:07:50 -07:00
raiden00pl
b721ba05aa stm32_pwm.c: fix compilation warnings 2021-05-05 09:32:58 -03:00
raiden00pl
7cb7fe3f38 stm32_pwm: fixes for PULSECOUNT support 
1. generate an indefinite number of pulses when info->count = 0
2. timers that don't support pulse-count shouldn't use pulse-count logic
 2021-05-05 09:32:58 -03:00
Sara Souza
873293cc3f xtensa/esp32: Applies REG_MASK to extract a field value 2021-05-05 01:30:03 -07:00
Sara Souza
50daf24242 esp32/esp32-c3: Adds two helpers to extract and include a field value 2021-05-05 01:30:03 -07:00
Sara Souza
cce42d5f74 xtensa/esp32: Reorganize the pins initialization and adds showprogress in __start 2021-05-05 01:30:03 -07:00
Sara Souza
afd6b26232 xtensa/esp32: Replace serialout/in and fixes the fifo counter issue 2021-05-05 01:30:03 -07:00
Abdelatif Guettouche
f3a6d80c95 esp32c3/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
Abdelatif Guettouche
e24af207f8 esp32/hardware: Include files of the same level by their names only and 
remove unnecessary includes.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-05-05 01:28:22 -07:00
raiden00pl
7b53a5fe1c stm32_adc.c: rename a struct member in struct adccmn_data_s from 'initialized' to 'refcount' 2021-05-05 01:27:56 -07:00
Sara Souza
b01ddef61b risc-v/esp32-c3: Adds freerun wrapper 2021-05-04 15:22:26 -03:00
Gustavo Henrique Nihei
7ded22fb1a risc-v/k210: Fix SMP interrupt stack size calculation 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
e0da0bf6bd arch/risc-v: Fix interrupt stack alignment 2021-04-29 19:39:17 -07:00
Gustavo Henrique Nihei
f8a36f10c3 arch: Uniformize optimization flag setting across architectures 2021-04-29 19:17:16 -07:00
Gustavo Henrique Nihei
abf039b744 risc-v/rv32im: Set MAXOPTIMIZATION regardless of any debug options 2021-04-29 19:17:16 -07:00
Alan C. Assis
0a0a034a3f esp32: replace EPS32 typo with ESP32 2021-04-29 18:03:05 -03:00
Juha Niskanen
07cde736bd arch: fix some printf format errors 2021-04-29 19:16:56 +01:00
Alexander Vasiljev
940c5b69c3 stm32h7: serial: use dma tx semaphore as resource holder 2021-04-29 03:19:44 -07:00