Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
arch/arm/src/stm32/Kconfig:
* In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY:
Fix typos in help text.
arch/arm/src/stm32h7/Kconfig:
* In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY,
STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY,
and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text.
arch/arm/src/stm32l5/Kconfig:
* In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix
typos in help text.
arch/arm/src/stm32/hardware/stm32_exti.h:
* Change STM32_EXTI2_OFFSET (offset to EXTI2 registers) from 0x18
to 0x20. This symbol is defined when CONFIG_STM32_STM32F30XX or
CONFIG_STM32_STM32F33XX. According to the current reference
manuals for STM32F334xx (RM0364 rev 4) and STM32F302xx (RM0365
rev 8), EXTI_IMR1 is at offset 0x00 and EXTI_IMR2 is at offset
0x20, i.e., 0x20 apart. The same offset applies to the rest of
the registers: EMR1/EMR2, RTSR1/RTSR2, etc.
Cleaning during `clean_context` had the issue of remaking everything
when `menuconfig` was issued. That's because `menuconfig` has a
`clean_context` on its way.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
It seems to be caused by the corrupted or wrong CPSR restored on return
from exception. NuttX restores the context using code like this:
msr spsr, r1
GCC translates this to:
msr spsr_fc, r1
As a result, not all SPSR fields are updated on exception return. This
should be:
msr spsr_fsxc, r1
This bug has been fixed by Heesub Shin in:
343243c7c0
Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e
use the same condition check in declaration and reference
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b
it's more simple to make mm_heap_s opaque outside of mm
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
It is no longer necessary to define CONFIG_ARCH_MATH_H when we would
like to link libm.a other than nuttx math library. So, this commit
removes the error condition.
Summary:
- This commit introduces setintstack macro to rp2040
which is used for SMP with interrupt stack
Impact:
- SMP with interrupt stack
Testing:
- Tested with raspberrypi-pico:smp
- NOTE: seed to set CONFIG_ARCH_INTERRUPTSTACK=2048
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit introduces setintstack macro which can be
overridden for SMP with interrupt stack
Impact:
- SMP only
Testing:
- Tested with raspberrypi-pico:smp
- NOTE: more commits will be added later
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
For the case when the watchdog is triggering a timeout we did not
correctly reset the GPIO_SDIO_D0.
Without this fix, the SD card can become inaccessible.
It turns out there is no difference in these two files as well as the
reference manual for the registers between the two parts, so it probably
makes sense to unify them
since kernel component should use UTC instead local time
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icf939e1ab0af8e577105f539d2553bc67b3b3d10
corrected setting SDMMC_DCTRL.DTMODE field for block data transfers ending on block count
and for block data transfers ending with STOP_TRANSMISSION command;
stm32_sdio: added more debug messages
instead calling kmm_heapmember or umm_heapmember because:
1.The stack supplied by caller may allocate from heap too
2.It's hard to implement these two function in ASan case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I196377822b7c4643ab4f29b7c1dc41dcd7c4dab1
* port didn't know about data-register fifo
* port didn't handle overrun condition
* driver could get stuck if interrupts were skipped due to saturation
Summary:
- Add Raspberry Pi Pico (RP2040) USB device controller support.
- Confirmed that CDC/ACM, MSC and these composite device are working.
- The current implementation have an unresolved issue and some workaround
for USB MSC SCSI driver is required.
See the comment in the patch "usbmsc: Add USBMSC_NOT_STALL_BULKEP for RP2040 workaround".
Impact:
- RP2040 only
Testing:
- Tested with Windows 10 and Ubuntu-18.04/20.04 as the USB host.
- Tested configurations:
- raspberrypi-pico:usbnsh
- raspberrypi-pico:usbmsc
- raspberrypi-pico:composite
All modern desgin support stack pointer and it's also an
important information, so let's standardize this interface.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- I noticed that DEBUGASSERTION() happens when executing
an ELF application
- This commit fixes this issue by re-mapping the address
to SYSBUS in up_module_text_free()
Impact:
- None
Testing:
- Tested with spresense (both DEBUG_ASSERTIONS=n and y)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- In cxd56xx, ldrex/strex behavior is slightly different from
other Arm architectures. Dummy strex must be issued to release
the exclusive load & store unit.
Impact:
- SMP only
Testing:
- Tested with spresense:smp
- Tested with spresese:wifi_smp, spresense:rndis_smp
- NOTE: CONFIG_CXD56_TESTSET=y must be removed from defconfigs
Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit converts data to the physical address for DMA transfer.
Impact:
- cxd56_dmac.c, cxd56_sdhci.c, cxd56_usbdev.c
- cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c
Testing:
- Tested with following configurations
- spresense:wifi, spresense:wifi_smp, spresense_rndis, spresense_rndis_smp
- NOTE: additional commits are needed for the test
- NOTE: cxd56_cisif.c, cxd56_emmc.c, cxd56_ge2d.c, cxd56_udmac.c are not tested
Signed-off-by: Kazuya Hioki <Kazuya.Hioki@sony.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit introduces cxd56_modtext.c to allocate a separate
text memory for ELF
Impact:
- None
Testing:
- Tested with spresense:elf
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Sebastien Lorquet has submitted the CLA
Uros Platise has submitted the CLA
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.
* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
If the subcore configuration, which is mainly used in the Spresense
Arduino environment, is enabled, the serial console has been already
initialized by maincore. Then, don't need to re-initialize the UART1
serial driver.
ADC driver does not support multiple open and close. It causes the memory
corruption by multiple free. This commit fixes this problem by introducing
the reference counter.
If the system clock is changed during loading gnssfw, gnss open may be
failed. So this commit prohibits clock change until loading gnssfw is
completed.
There is an issue that the next alarm is expired immediately after
canceling a RTC alarm. Fixed alarm settings to be completely cleared
when canceling an RTC alarm.
If the system clock is changed during the SPI transfer, the SPI data can
be corrupted. So this commit prohibits the clock change during SPI transfer,
and keep the clock until the transfer is completed.
Introduce PM_CPUFREQLOCK_FLAG_HOLD into the frequency lock mechanism in
power manager, which is used to keep the current frequency without clock
change, for example, during the transfer of a periphral.
UART driver is stopped and re-started during a clock change. When a UART
interrupt is generated in each process, the unexpected behavior will
occur and a console will get stuck with UART driver. This commit fixed
each process is performed atomically.
Currently Nuttx doesn't seem to be any real support for OTG.
In the future when OTG is supported. This Knob can be removed
and drivers can enable their pin sets based on CONFIG_OTG.
(Adding CONFIG_OTG at this time would be misleading.)
stm32f7:SDMMC Use inttypes in printing macro
stm32f7:CAN Use inttypes in printing macro
stm32f7:DMA Use inttypes in printing macro
stm32f7:serial fix compile error from UNUSED() change
Summary:
- This commit adds stack coloration for the idle task
Impact:
- rp2040 with CONFIG_STACK_COLORATION=y
Testing:
- Tested with nsh, nshsram and smp configurations
- NOTE: CONFIG_STACK_COLORATION=y needs to be added
Summary:
- The NuttX for raspberrypi-pico boots via the boot_stage2 provided
by the pico-sdk which sets the MSP at the end of the SRAM.
- However, the NuttX expects the MSP is set to the top of the idle stack.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with nsh, nshsram and smp configrations
Summary:
- SP_SECTION was introduced to allocate spinlock in non-cachable
region mainly for Cortex-A to stabilize the NuttX SMP kernel
- However, all spinlocks are now allocated in cachable area and
works without any problems
- So SP_SECTION should be removed to simplify the kernel code
Impact:
- None
Testing:
- Build test only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The CONFIG_SMP_IDLETHREAD_STACKSIZE was introduced to optimize
the idle stack size for other than CPU0
- However, there are no big differences between the idle stacks.
- This commit removes the config to simplify the kernel code
Impact:
- All SMP configurations
Testing:
- Tested with ostest with the following configs
- spresense:smp, spresense:rndis_smp
- esp32-devkitc:smp (QEMU), maix-bit:smp (QEMU)
- sabre-6quad:smp (QEMU), sabre-6quad:netnsh_smp (QEMU)
- raspberrypi-pico:smp, sim:smp (x86_64)
Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
stm32h7:Serial Use Idel to poll RX DMA
stm32h7:Serial Do not loop in an ISR!
stm32h7:Serial signal txdma completion with semaphore
stm32h7:Serial Apply formatting suggestions from code review
Co-authored-by: Mateusz Szafoni <raiden00pl@gmail.com>
stm32h7: Serail Add Power Managment (Untested)
arch: Allocate the space from the beginning in up_stack_frame
and modify the affected portion:
1.Correct the stack dump and check
2.Allocate tls_info_s by up_stack_frame too
3.Move the stack fork allocation from arch to sched
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
For unknown reasons this message may interferre with the calibration
procedure and result in invalid calibariton data.
We leave only a message informing about the end of the the calibration.
The problem was observed for STM32G4 + IHM16M1.
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
allocation; use the previous calculation directly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
That field is never used and, in most cases, is never initialized correctly.
This should have no impact to anything with the possible exception of free-running drivers.
Verified using CI builds only.
The comments at the top of the file say this:
```
This will be automatically registered
* - AXI SRAM is a 512kb memory area. This will be automatically registered
* with the system heap in up_allocate_heap, all the other memory
* regions will be registered in arm_addregion().
```
but the implementation was using SRAM123 instead. Furthermore, arm_addregion then re-adds SRAM123 again.
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Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This change makes it so that the timeout is set as part of the SDIO_WAITENABLE call instead of the SDIO_EVENTWAIT call. By doing so, you eliminate all opportunity for a race condition.
stm32h7:sdmmc Check if busy ended early
1.To support the different MCU in series(e.g. cortex-m0+)
2.It's redundant since we already specify in compliler option
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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Normally, statically allocated data goes in .bss, followed by the
initial stack, followed by HEAP. However, any data that is statically
allocated in SRAM4 with __attribute__ ((section (".sram4"))) will
clobber, and be clobbered by, the HEAP.
On STM32H7, BDMA can only access SRAM4. Therefore any BDMA buffers (or
any other data) placed in SRAM4 will expose this problem. In one case,
this manifested as a failure of NSH to start, because the SPI6 BDMA
buffers clobbered the /dev/console inode structs, which the OS
allocated earlier.
This PR ensures that only the rest of SRAM4, after any static data, is
added to the heap. This PR also allows SRAM4 to be completely excluded
from the heap by a new Kconfig, CONFIG_STM32H7_SRAM4EXCLUDE, similar
to what CONFIG_STM32H7_DTCMEXCLUDE does for the DTCM region.
Change required in linker scripts:
Every STM32H7 linker script must replace this:
.sram4 :
{
} > sram4
with this:
.sram4_reserve (NOLOAD) :
{
*(.sram4)
. = ALIGN(4);
_sram4_heap_start = ABSOLUTE(.);
} > sram4
or link will fail with: undefined reference to '_sram4_heap_start'.
The Release Notes should document this for users with out-of-tree
boards.
arch/arm/src/stm32h7/Kconfig:
* Add config STM32H7_SRAM4EXCLUDE to allow excluding all of SRAM4
from the HEAP.
arch/arm/src/stm32h7/stm32_allocateheap.c:
* Only when including SRAM4 in the heap, define HAVE_SRAM4,
SRAM4_START, SRAM4_END, and SRAM4_HEAP_START.
* Add "Private Data" section.
* Add extern for_sram4_heap_start, which must be defined in the
board's linker script.
* arm_addregion(): Only add SRAM4 to the heap when configured to
do so, i.e., unless CONFIG_STM32H7_SRAM4EXCLUDE is defined, and
only add the portion of SRAM4 that is past any static data.
boards/arm/stm32h7/nucleo-h743zi/scripts/flash.ld:
boards/arm/stm32h7/nucleo-h743zi/scripts/kernel.space.ld:
boards/arm/stm32h7/nucleo-h743zi2/scripts/flash.ld:
boards/arm/stm32h7/stm32h747i-disco/scripts/flash.ld:
boards/arm/stm32h7/stm32h747i-disco/scripts/kernel.space.ld:
* Update all in-tree STM32H7 board linker scripts as described in
"Change required in linker scripts" above.
Testing:
* Successfully built all of the following configurations:
nucleo-h743zi2:jumbo
nucleo-h743zi2:nsh
nucleo-h743zi:nxlines_oled
nucleo-h743zi:elf
nucleo-h743zi:otg_fs_host
nucleo-h743zi:nsh
nucleo-h743zi:netnsh
nucleo-h743zi:pwm
stm32h747i-disco:nsh
* Tested with custom board.
* nxstyle.
References:
[1] See the dev@nuttx.a.o mailing list discussion started 2021/03/25:
"How to ensure HEAP will not overlap static DMA buffer?"
https://lists.apache.org/thread.html/recf2bb9043f8c9f53c10917e2adb2ec64fe35dc5e6f9a695a7ac6ecc%40%3Cdev.nuttx.apache.org%3E
[2] See arm_addregion() in arch/arm/src/stm32h7/stm32_allocateheap.c
Thanks to Gregory Nutt and David Sidrane for suggestions and reviews.
The maximum number of samples which can be handled without overrun depends on various factors.
This is the user's responsibility to correctly select this value.
Since the interfece to update the sampling time is available for all supported devices,
the user can change the default vaules in the board initialization logic and avoid ADC overrun.
arch/arm/src/stm32h7/stm32_dma.c:
* Include <inttypes.h> explicitly for format specifiers.
* In functions stm32_mdma_capable(), stm32_mdma_dump(),
stm32_sdma_setup(), stm32_sdma_capable(), stm32_sdma_dump(),
stm32_bdma_setup(), stm32_bdma_capable(), stm32_bdma_dump(),
stm32_dmamux_dump(), stm32_dmachannel(), stm32_dmafree(), and
stm32_dmadump():
Where appropriate, use format specifiers from <inttypes.h> in
calls to dmainfo(). This removes numerous compiler warnings
like:
warning: format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'uint32_t {aka long unsigned int}'
[-Wformat=]
* In function stm32_mdma_disable():
Remove wrong redefinition of 'dmachan' parameter as a local
variable. This fixes the following compiler error that occurs
when building with CONFIG_STM32H7_MDMA:
chip/stm32_dma.c:930:17: error: 'dmachan' redeclared as
different kind of symbol
DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
^~~~~~~
chip/stm32_dma.c:928:44: note: previous definition of 'dmachan'
was here
static void stm32_mdma_disable(DMA_CHANNEL dmachan)
^~~~~~~
chip/stm32_dma.c:930:43: error: 'handle' undeclared (first use
in this function); did you mean 'random'?
DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
^~~~~~
random
For example Windows RNDIS driver issues SETUP requests that are 76 bytes
long. Previously NuttX would read them all, but only if they arrive at
the same time. If host transfer scheduling causes a pause between the
two DATA packets, stm32_ep0out_receive() would proceed with an incomplete
transfer. The rest of the data could either be skipped by the error handler
branch, or be left in NAK state forever, stopping any further communication
on the endpoint.
This commit changes it so that the whole transfer has to be received before
SETUP handler is called. Depending on CONFIG_USBDEV_SETUP_MAXDATASIZE any
excess bytes will be discarded, but doing this in a controlled way ensures
deterministic behavior. In the specific case of RNDIS, the trailing bytes
are unused padding bytes and can be safely discarded.
arch/arm/src/stm32/Kconfig:
* configs ARCH_CHIP_STM32G431K, ARCH_CHIP_STM32G431C,
ARCH_CHIP_STM32G431R, ARCH_CHIP_STM32G431M, and
ARCH_CHIP_STM32G431V: Fix copy/paste of incorrect
names shown in the Kconfig menu.
nxstyle is complaining that the headers are defines outside
Included Files section and we have to duplicate the definitions
to the imported files to avoid build errors.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Sebastien Lorquet has submitted the ICL and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Alan Carvalho de Assis has submitted the ICL and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
David Sidrane has submitted the ICL and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
David S. Alessio has submitted the ICL and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
