SAMDL DMA fixes and experimental SPI support
* SAMDL: Fix DMA controller support
* SAMDL: Added experimental DMA support to SPI driver. spi_exchange() uses a pair of DMA channels for TX and RX
Approved-by: Gregory Nutt <gnutt@nuttx.org>
disable LPC17 FDR when not used (second fix)
if a boot loader sets the fractional divider (FDR) the baud rate in
nuttx will be wrong (multiplied by this fraction).
This also has to be added to lpc17_lowputc.c
Unfortunately the constant used for shifting the bits was wrong in the header file, so it took some time to realize this...
Approved-by: Gregory Nutt <gnutt@nuttx.org>
configs/flipnclick-pic32mz: Add an nxlines configuration for use in testing the custom HiletGo Click board.
arch/mips/src/pic32mz: Correct some SPI-related typos. configs/flipnclick-pic32mz: Finishes integration of HiletGo OLED. drivers/lcd: Finish support for HiletGo OLED.
drivers/lcd: Add configuration support for HiletGo OLED. configs/flipnclick-pic32mz: Add board support for HiletGo OLED.
arch/mips/src/pic32mz: Fix some typos in debug instrumentation in pic32mz-gpio.c; fix some types releated to UART5 configuration in pic32mz-serial.c.
configs/flipnclick-pic32mz/nsh: Switch serial console to UART3. There is some problem with the UART4 RX pin documentation or configuration.
disable LPC17 FDR when not used
* disable LPC17 FDR when not used
if a boot loader set the fractional divider (FDR) the baud rate in
nuttx will be wrong (multiplied by this fraction).
So if it is not used, it should be disabled.
LPC176x docs say:
"
DIVADDVAL Baud-rate generation pre-scaler divisor value.
If this field is 0, fractional baud-rate generator will
not impact the UARTn baudrate.
MULVAL Baud-rate pre-scaler multiplier value.
This field must be greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is used or not.
"
So DIVADDVAL is set to 0 and MULVAL is set to 1.
* symbols found and added
Approved-by: Gregory Nutt <gnutt@nuttx.org>
binfmt/, configs/, grahics/, libc/, mm/, net/, sched/: OS references to the errno variable should always use the set_errno(), get_errno() macros
arch/arm/src/stm32 and stm32f7: Architecture-specific code is not permitted to modify the errno variable. drivers/ and libc/: OS references to the errno variable should always use the set_errno(), get_errno() macros
sched/sched: Correct some build issues introduced by last set of changes.
sched/sched: Add new internal OS function nxsched_setaffinity() that is identical to sched_isetaffinity() except that it does not modify the errno value. All usage of sched_setaffinity() within the OS is replaced with nxsched_setaffinity().
sched/sched: Internal functions sched_reprioritize() and sched_setpriority() no longer movidify the errno value. Also renamed to nxsched_reprioritize() and sched_setpriority().
sched/sched: Add new internal OS function nxsched_getscheduler() that is identical to sched_getscheduler() except that it does not modify the errno value. All usage of sched_getscheduler() within the OS is replaced with nxsched_getscheduler().
sched/sched: Add new internal OS function nxsched_setparam() that is identical to sched_setparam() except that it does not modify the errno value. All usage of sched_setparam() within the OS is replaced with nxsched_setparam().
sched/sched: Add new internal OS function nxsched_getparam() that is identical to sched_getparam() except that it does not modify the errno value (actually, the previous value erroneously neglected to set the errno value to begin with, but this fixes both issues). All usage of sched_getparam() within the OS is replaced with nxsched_getparam().
SAMDL: Added SAMD DAC header file. Fixed SAMD EVSYS header. Added SAMD TC header file. Fixed some minor typos
* SAMD External Interrupt Controller (EIC) support
* removed comment
* SAMDL: SPI must be disabled before changing the mode bits in CTRLA register
* arch/arm/src/lc823450: Assign I2S IRQ handling to CPU0
Previous commit assumed that the caller is running on CPU0.
However, the caller sometimes runs at CPU1. This patch will
assign the caller to CPU0 explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Change irqwarn() to ASSERT() in up_ack_irq()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt and defconfigs
Update comments on SMP in README.txt
Enable SYSTEM_TIME64 in defconfigs.
Enable INSTRUMENTATION in rndis configuration.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configst/stm3240g-eval: Remove only bogus logic to start the NX server. That was there only to support the knxwm configuration and was implemented priorit to boardctl(BOARCIOC_NX_START).
* drivers/input/ft5x06.c: Remove cool logic to disable polling when there there is no client waiting for read data. That was a great idea to save CPU cycles when there is nothing reading from the touchscrren but, unfortunately, does not work with readers that open the driver in non-blocking mode. So I think we just have to eat the CPUs even when there is nothing waiting for touchscreen input.
* configs/lpcxpresso-lpc54628/lvgl: Add LittlevGL graphics demo configuration.
* configs/lpcxpresso-lpc54628: Update README
* include/termios.h: Update comments; fix long lines.
* sched/semaphore: Add ASSERT(false) in nxsem_post() if no waiting task is found.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* sched/sched/sched_sporadic.c: fix compiler error when priority inheritance is enabled. Noted by eunb.song@samsung.com
* Change ASSERT(false) to DEBUGPANIC().
* Documentation: Fix copy/paste error in NX graphics document. Noted by Henjiu Kang.
* sched/sched: Fix some priority inheritance related issues noted during review of logic. Also add some REVISIT comments for some issues noted in the design.
* Update README and some comments
* Issue #85: /dev/userleds is not working for nucleo-l432kc fixed
* configs/nucleo-l432kc: Fix numerous cloning errors/typos.
* Update TODO list
* NUCLEO F432KC typo fixed, correct name is L432KC
Just README.txt and comments affected, no changes in the code
* Merged in raiden00/nuttx (pull request #579)
Master
* stm32_hritm: add interface to get timer clock frequency
stm32_hrtim: fix timer freq calculation
stm32_hrtim: add compar/capture registers significant bits checking
stm32_hrtim: minor changes
* stm32f334-disco: add buck converter and boost converter logic
Approved-by: Gregory Nutt <gnutt@nuttx.org>
* fs/userfs: use correct req type in userfs_truncate, remove use of undeclared buf
* Merged in david_alessio/nuttx/refactor-pll-setup (pull request #581)
Refactor pll setup
* fix typo in #def
* refactor PLL setup code...
* refactored PLL/CLK config, easier, checks for correctness
* call go_os_start if STACK_COLORIZED
* smarter config of EXTCLK output freq
* cosmetic
Approved-by: Gregory Nutt <gnutt@nuttx.org>
* The existence of the network driver ioctl() method should depend on CONFIG_NETDEV_IOCTL rather than CONFIG_NETDEV_PHY_IOCTL. The former enables the method, the later enables a subset of possible driver IOCTLs. This change should be basically a no-operation. The affected ioctl methods only support those subset of driver IOCTLs selected by CONFIG_NETDEV_PHY_IOCTL and the network logic will tolerate a nul ioctl method.
* net/tcp: Write buffering logic should not wait for a free buffer if the socket was opened non-blocking. Also, rename the TCP write buffering macros from WRB_* to TCPWB_* to make room in the namespace for write buffering with other protocols.
* net/udp: Remove some conditional logic that was true if there is only a single network device, but not true in the multi-device context.
* This commit adds an as-of-yet untested implemented of UDP write buffering.
Squashed commit of the following:
net/udp: Address most of the issues with UDP write buffering. There is a remaining issue with handling one network going down in a multi-network environment. None of this has been test but it is certainly ready for test. Hence, the feature is marked EXPERIMENTAL.
net/udp: Some baby steps toward a corrected write buffering design.
net/udp: Remove pesky write buffer macros.
Eliminate trailing space at the end of lines.
net/udp: A little more UDP write buffering logic. Still at least on big gaping hole in the design.
net/udp: Undefined CONFIG_NET_SENDTO_TIMEOUT.
net/udp: Crude, naive port of the TCP write buffering logic into UDP. This commit is certainly non-functional and is simply a starting point for the implementatin of UDP write buffering.
net/udp: Rename udp/udp_psock_sendto.c udp/udp_psock_sendto_unbuffered.c.
* net/udp: In sendto(), return EHOSTUNREACH if if the network is down.
* net/udp: Resolves final design issues with UDP write buffering. 100% code complete but also 100% untested.
* net/udp and tcp: Yet another (cosmetic) change to UDP and TCP write buffer macro naming.
* net/udp: UDP write buffering is basically functional but needs a lot more verification.
* net/udp: Fix memory leak with UDP + write buffer is closed. Also update TODO and comments and refresh a configuration.
* Update some comments.
* drivers/mtd/at24xx.c: Correct page size for AT24C02 part.
* arch/arm/src/stm32: Make STM32 usable with an external RTC. drivers/timers/ds3231.c: Correct some debug statments.
* arch/arm/src/stm32/stm32_spi.c: Removed unnecessary (and incorrect) speed limitation
* arch/arm/src/stm32/stm32f40xxx_i2c.c: Correct some recent changes to STM32F4 I2C that broke poll mode of operation.
* configs/flipnclick-sam3x: Using JTAG (vs. Bossac) I was finally able to load code and verify the basic NSH configuration. Updated READMEs. Also switched to USART0 (vs UART0) for the serial console because I was not getting bi-directional communication on the VCOM.
* SAMDL: Added SAMD DAC header file. Fixed SAMD EVSYS header. Added SAMD TC header file. Fixed some minor typos
* fix typo
* added missing EVCTRL register bits in TC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
SAMDL: SPI must be disabled before changing the mode bits in CTRLA register
* SAMD External Interrupt Controller (EIC) support
* removed comment
* SAMDL: SPI must be disabled before changing the mode bits in CTRLA register
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Previous commit assumed that the caller is running on CPU0.
However, the caller sometimes runs at CPU1. This patch will
assign the caller to CPU0 explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
configs/flipnclick-pic32mz: Switch the serial console to UART4. Clean up some minor issues the LED options.
configs/flipnclick-pic32mz: Add support for two on-board buttons: T1 and T2.
configs/flipnclick-pic32mz: Adds basic board support for the Mikroe Flip&Click PIC32MZ board. Initial commit is just the configs/pic32mz-starterkit with some name chanages.
arch/mips/src/pic32mz: Commits the basic architecture port for the PIC32MZEF.
arch/mips/src/pic32mz: Begin adding PIC32MZEF files. Initial commit are simply PIC32MZEC files with name changes.
arch/mips/include/pic32mz: Add support for the PIC32MZEF family.
lpc43/54 SDMMC: Wading through bits trying to make sense out of what is a event want interrupt which deal mostly with commands+responses and what is a data transfer event. DTO is the only wildcard. I think this clear now but DMA transfers will fail with CRC error.
lpc43/54 SDMMC: DTO is a wait event, not a transfer event.
lpc43/54 SDMMC: Significant simplication to previous design. More debug output.
lpc43/54 SDMMC: Don't allow duplicate events in waitmask and xfrmask.
lpc43/54 SDMMC: Not all interrupts were being disabled at the end of a transfer.
lpc43/54 SDMMC: Defer enabling DMA transfer interrupts until after command has been sent.
Squashed commit of the following:
arch/arm/src/lpc43xx: SDMMC driver now builds for the LPC43 (provided that the proper definitions appear in the board.h file).
arch/arm/src/lpc43xx: Update basic changes to the ported lpc54xx driver for lpc43xx clocking and GPIOs.
arch/arm/src/lpc43xx: Brings in the LPC54xx SD/MMC driver with absolutely no changes other than changing all occurences of 54 to 43.
arm/arm/src/lpc43xx: Add build support for the lpc54 SDMMC driver.
lpc54 SDMMC: Check for successful data transfer last. Checking first means that we miss errors.
Squashed commit of the following:
arch/arm/src/lpc54xx: SDMMC fixes.. DMA should not be enabled on non-DMA transfers, the burst setting in FIFOTH is supposed to match the burst setting in the BMOD reseters, Add DMA error interrupt support.
arch/arm/src/lpc54xx: Mostly costmetic changes to the SDMMC driver.
In lc823450, ldrex and strex are not supported. So we implemented
up_testset() with H/W Mutex. However, there was a bug in memory
access order. This change ensures correct memory access order in
up_testset() for lc823450.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
lc823450 http streaming
* arch/arm/src/lc823450: Use spinlock APIs in lc823450_gpio.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a warning message in up_ack_irq()
In SMP mode, H/W interrupts should be handled on CPU0 to avoid deadlocks.
Other changes:
Fix a potential race condition in up_enable_irq()
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Enable HRT_TIMER in lc823450_timerisr.c
Other changes:
Fix style violations and call up_enable_irq() to assign CPU0 for IRQ handling.
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix race conditions in dma/usbdev.
In SMP mode, critical data must be protected explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt
Add notes on .gdbinit and networking. Update comments on SMP.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update defconfigs
Enable HRT_TIMER, LC823450_MTM0_TICK, SPINLOCK_IRQ
Enable NET_TCP_RWND_CONTROL, NXPLAYER_HTTP_STREAMING_SUPPORT (rndis only)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/lpc54xx: Adds the LPC54-specific clock configuration logic to the leveraged SD/MMC driver.
arch/arm/src/lpc54xx: Leveraged SD/MMC driver builds without error but is still missing clock configuration logic.
arch/arm/src/lpc54xx: Bring in LPC43xx SD/MMC driver from https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx
arch/arm/src/lpc54xx: LCD.. Fix some miconceptions about how the video address lines are used.
arch/arm/src/lpc54xx: Fix some LCD BPP and BRG vs RGB settings.
lc823450 smp improvement
* arch/arm/src/common: Apply irq_spin APIs to modifyregXX
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.
Please see 6150299f54 as well.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Do not use modifyreg32() to enable Mutex.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Modify IRQ control for i2s
Interrupt will be handled on CPU0 with this change.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Apply irq_spin APIs to dma/syscontrol/usbdev.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Assign CPU1 to lpwork
This change will improve load balancing for networking with RNDIS.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* drivers/audio/wm8776.c: Improve stability in SMP mode
Apply irq_spin APIs to improbe performance.
Repeat to process a message to avoid deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable SPINLOCK_IRQ and NXPLAYER in rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/lpc54xx: Finish off some missing logic. Complete now execpt for GPIO and LED support.
arch/arm/src/lpc54xx: Add lpc54_clrpend.c
arch/arm/src/lpc54xx: Serial driver is complete and compiles.
arch/arm/src/lpc54xx: Add beginning of a serial driver (still missing some logic)
arch/arm/src/lpc54xx: Fleshes out low level USART intialization.
arch/arm/src/lpc546xx/Kconfig: Add hooks to integrate with common seril upper half.
arch/arm/src/lpc54xx: Beginning of USART console support.
arch/arm/src/lpc54xx: Completes very basic clock configuration.
arch/arm/src/lpc54xx: Add clocking logic (still not complete)
arch/arm/src/lpc54xx: Beginning of PLL configuration logic.
arch/arm/src/lpc54xx: Fix a few things from first compile attempt. Compilation cannot work until I at least finish the clock configuration logic.
arch/arm/src/lpc54xx: Addes some SysTick logic.
arch/arm/src/lpc54xx: Completes basic startup logic (sans clock configuration) and interrupt configuration.
arch/arm/src/lpc54xx: Add generic ARMv7-M start-up logic (needs LPC54628 customizations); add emtpy file that will eventually hold the clock configuration logic.
arch/arm/src/lpc54xx: Add (incomplete) SYSCON register definition header file.
arch/arm/src/lpc54xx: Add FLEXCOMM header file.
arch/arm/src/lpc54xx: Bring in tickless clock logic from LPC43; configs/lpcxpresso-lpc54628: mount procfs if enabled.
arch/arm/src/lpc54xx: Add RIT clock definitions; add SysTick initialization (not finished)
LPC54xx and LPCXpresso-LPC54628: add more boilerplate files and stubbed out files.
arch/arm/src/lpc54xx: Add (incomplete) USART header file.
Add another condition to a Kconfig; refresh a defconfig.
arch/arm/src/lpc54xx/chip: Add LPC54628 memory map header files.
configs/lpcxpresso-lpc54628: Add basic build files for the LPCXpresso-LPC54628
arch/: Basic build directory structure for the LPC54628
arch/arm/src/xmc4/Kconfig: Define user friend I2C alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend LIN alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend I2S alias to follow other arch names
lc823450 smp audio
* arch/arm/src/lc823450: Remove a workaround in up_cpu_paused()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Introduce g_gpio_lock to improve write performance in SMP mode.
NOTE: This is a tentative solution and should be replaced with more generic one.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a workaround in up_txready() to avoid data corruption.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable CONFIG_SMP for audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt regarding SMP audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled.
2) The second allows changing voltage output scaling setting and prevents enabling over-drive mode for low frequencies (STM32 F74xx, 75xx, 76xx, 77xx)
STM32, STM32 L4, and STM32 M4: USB OTGFS DMA trace output fix
STM32: Add dump buffer feature to stm32 F4 series
STM32 and STM32 L4: Fix bad USB OTGFS register address
STM32 L4: Fix typo in USB OTGFS register usage
STM32 L4: Add check in USB OTGFS driver to assure that SYSCFG is enabled
Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB
lc823450 auto LED support
* arch/arm/src/lc823450: Add auto LED for CPU activity
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Add auto LED support
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
configs/stm32f429i-disco/ltdc: This configuration has been deleted because it violated the portable POSIX OS interface. It used apps/examples/ltdc and include ltdc.h and dma2d.h which were also removed for the same reason.
fs/userfs: This completes coding of the UserFS client and of the UserFS feature in general. This feature is being merged to main now because I believe it is innocuous. It is, however, untesed. The next step will be to develop a test case to verify the feature.
fs/userfs: Completes the request logic for the UserFS client. Still need the logic that receives the responses.
fs/userfs: Completes coding for most of the server side of the user filesystem logic.
fs/userfs: Big design changes, simplications. Use Unix domain local sockets instead of message queues. Easier to transfer big data in local sockets than message queues. Remove character drvier 'factory' it is not necessary.
fs/userfs: Minor reparitioning; volume private info does not need to be held on the OS client side.
libc/userfs: Add some of the server side logic.
fs/userfs: Add some UserFS initialization logic.
fs/userfs: Add frame work for the UserFS proxy. Remove all references to a block driver. There is no block dricer... what was I thinking?
fs/userfs: Add some initialization of the character driver, 'factory' device.
fs/userfs: Rename from fusefs to userfs to that we don't stomp on someone else's cool name.
Add a header file describing the fusefs interface.
Fix stm32 dmacapable on f20xx
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Port STM32F7 I2C driver to STM32L4
* arch/stm32l4: port STM32F7 I2C driver to STM32L4
STM32L4 I2C driver is in work-in-progress state (plentiful of
TODOs and #warnings) and lags many features found in more
up-to-date STM32 I2C drivers. The peripheral on STM32F7 and
STM32L4 are identical except for L4's 'wakeup from stop mode'
flag and STM32F7's I2C driver is in more 'ready to use' state.
Patch ports the STM32F7 I2C driver to STM32L4. The I2C clock
configuration is kept the same as before (I2CCLK = PCLK1 80 Mhz)
instead of switching to STM32F7 arch default that is I2CCLK=HSI.
Further work would be to add configuration option for choosing
I2C clock source instead of current hard-coded default.
* arch/arm/stm32f7: i2c: restore bus frequency after I2C reset
Copy frequency restoration fix from STM32L4 I2C driver to STM32F7 I2C driver.
* arch/arm/stm32f7: i2c: remove unused Kconfig option
* configs/nucleo-l496zg/nsh: enable I2C4 bus with i2ctool
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32_hrtim: fix warnings related with RCC
* stm32f33xxx_adc: add some publicly visable interfaces and some code to support injected channels
* stm32f33xxx_dma: add public interface to handle with DMA interrupts
* stm32_hrtim: change some names and add some coments
* chip/stm32f33xxx_adc.h: cosmetics
* nucleo-f334r8: add logic for zero latency high priority interrupts example
* stm32: update some ADC-related configuration in Kconfig
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L1, STM32L4 RTC: add periodic interrupts, update L1 RTC implementation
* STM32L4 RTC: add support experimental CONFIG_RTC_PERIODIC
* STM32 RTC: separate STM32L1 RTC into a separate file
STM32L1 RTC is very close to F4 or L4 versions, with two alarms
and periodic wakeup support so backported L4 peripheral to L1.
* RTC: add periodic alarms to upper and lower halves
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32f33xxx_adc.c: fix some warnings and compilation error when extsel not in use
* nucleo-f334r8/adc: change serial console to USART2 (STLINK COM)
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number).
This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild).
Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug.
I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox.
