kinetis:i2c ensure timeout on bus error
The code had a dead wait on I2C_S_BUSY. Noise on the
bus would cause the driver to hang.
Add timeout on invalid states of I2C_S_BUSY to allow
the upper layers do deal with restart or abort.
Approved-by: GregoryN <gnutt@nuttx.org>
include/nuttx/arch.h: Add prototype for an architecture-specific up_trigger_irq function
arch/, include/nuttx, sched/sched: Add the garbage collection hook so each architecture can do custom memory cleanup if necesary.
arch/Kconfig: Add configureation CONFIG_ARCH_GNU_NO_WEAKFUNCTIONS to suppress use of weak functions. Some gnu derived toolchains do not support weak symbols
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kinetis: Cosmetic changes from review of coding standard.
Author: David Sidrane <david_s5@nscdg.com>
Merged in david_s5/nuttx/master_kinetis (pull request #710)
kinetis:Add DMA and use it as RX FIFOs on Serial
* Add initial implementation of the DMA
* Add across Kxx family support [WIP]
* Incorporate the DMA into the serial
Add polling to serial
do DMA initialisation at UART startup and fix DMA mux setting.
Fix circular DMA handling in the serial driver.
* Adapt defconfig to enable UART1,4 RXDMA
* [WIP] - refactor this with new CONFIG DMA settings
* kinetis/Kconfig:Bring inline with upstream stucture
1. Use the Serial console configuration from drivers/serial/Kconfig
and friends.
2. Prefix arch specific featurs as such
UARTx_RXDMA->KINETIS_UARTx_RXDMA
* Kinetis:Serial formatting and clean up
* kinetis:DMA Formating and Cleanup
* kinetis:serial Use cleaner DMA API
* kinetis:Make.defs fix duplicate/errant kinetis_dma.o
* kinetis:serial Fix warning/error on only one uart using DMA
The driver can support no DMA on any UART, DMA on some
UARTs or DMA on all UARTs.
In the case of no DMA we disable the DMA based variables
and logic. In the case of all DMA we disable the non
DMA variables and logic, and in the mixed case both
DMA and non DMA variable and logic are enabled.
* kinetis:dma config fix formatting
* kinetis:chip/dma fix formatting
* kinetis:DMA config assume Unknown
Assume KINETIS_DMA_VERSION_UKN for all SoC not versioned
This is as the code was in nuttx prior to this commit
* kinetis:DMAMUX contain versioning- use HAS pattern define Unknown
The pattern for chip versioning is to define 'HAS' constants.
Define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG to contain the
version numbers to the include soc header and use that define
in the chip headers.
Define the KINETIS_DMAMUX_VERSION_UKN for the default as prior
this commit addressing was by default monotonic for CHCFG
* freedom-k66f:Disable Serial RXDMA
The application has to add calling of the kinetis
serial dma poll as it is application specific.
Approved-by: GregoryN <gnutt@nuttx.org>
* kinetis:PIT add Liftime and Chaining
* kinetis:flexcan fix dup line and ordering
* kinetis:kinetis_lowput.c LPUART data format with parity fix
The 9-bit data mode is typically used with parity to allow
eight bits of data plus the parity
* kinetis:pindma fix warning
* kinetis:lowputc LPUART_BAUD_INIT has to be defined
build fails with test case enable LPUART0 and make
UART1 console
if HAVE_LPUART_DEVICE is defined then LPUART_BAUD_INIT
has to be defined even if the lpuart is not the console
* kinetis:lpserial fix warning
While this is a good idea and a proper thing to do, it also creates a circular dependency and errors during configuration. RTC depends on STM32_RTC which depends on RTC_EXTERNAL with depends on RTC. No can do.
This reverts commit 714e8c1f9e.
Fix http streaming with lc823450
* arch/arm/src/lc823450: Change C-Buffer under-level control
The under-level setting was changed from 1KB to 55KB.
In previous implementation, the setting can ben changed
by the tx threshold but it is fixed at startup.
Also, check write size and adjust alignment if needed.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Change IOB related params for rndis.
Since TCP flow control scheme was changed, HTTP audio streaming
has not been working. These IOB params are not optimized but
HTTP audio streaming now works.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
configs/olimex-stm32-p407: Various changes as necessary to get the new kelf configuration working.
configs/olimex-stm32-p407: Add kernel ELF (kelf) configuration.
This update is required to be serialized to the instruction stream meaning that after this update completes, it takes effect immediately and no exceptions of lower priority than the new boosted priority can pre-empt execution. Because of this erratum, the priority boosting does not take place immediately, allowing the instruction after the MSR to be interrupted by an exception of lower priority than the new boosted priority. This effect is only limited to the next instruction. Subsequent instructions are guaranteed to see the new boosted priority.
This was raised in Bitbucket issue 113 from Vadzim Dambrouski.
Squashed commit of the following:
arch/arm/src/samd5e5/sam_usb.c: USB driver now compiles with some issues.
arch/arm/src/samd5e5/chip/sam_fuses.h: Add fuse definition header file.
arch/arm/src/samd5e5: Bring USB driver in from SAMD2L2.
arch/arm/src/samd5e5/sam_clockconfig.c: Implement DFLL support. This completes coding the the re-architected clock configuration logic.
arch/arm/src/samd5e5/sam_clockconfig.c: Add data structures and definitions to support the FDLL and the DFPLL0/1.
arch/arm/src/samd5e5: Completes GCLK configuration logic. Still FDPLL and FDLL support.
arch/arm/src/samd5e5: A little more GCLK configuratino logic. Still incomplete.
arch/arm/src/smad5e5: Beginning of GCLK configuration logic.
arch/arm/src/samd5e5: Add MCLK configuration logic.
arch/arm/src/samd5e5: Add XOSC0/1 configuration logic.
arch/arm/src/samd5e5: Add XOSC32 configuration logic.
arch/arm/src/samd5e5: Rip out all of the leveraged clock configuration logic and start from scratch.
Squashed commit of the following:
arch/arm/src/samd5e5: Clean-up EIC logic.
arch/arm/src/samd5e5: Fix some compilation issues; Still issues with the EIC logic from samd2x.
arch/arm/src/samd5e5: Fix some compilation issues; bring in some EIC logic from samd2x.
arch/arm/src/samd5e5: Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
configs/metro-m4: Add LED support.
arch/arm/src/samd5e5: Bring in SAML21 clock configuration. This is a WIP; it cannot possible even compile yet.
arch/arm/src/samd5e5: Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
arch/arm/src/samd5e5: Add SERCOM utility function.
arch/arm/src/samd5e5: Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5. This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
arch/arm/src/samd5e5: Add sam_config.h header file
arch/arm/src/samd5e5/: Add Generic Clock (GCLK) utility functions.
arch/arm/src/samd5e5: Add EVSYS register definition file
arch/arm/src/samd5e5 and configs/metro-m4: Use SERCOM3 for the Arduino serial shield as console.
arch/arm/src/samd5e5/chip: Add SERCOM USART, SPI, I2C master, and slave register defintions header files
arch/arm/src/samd5e5/chip: Add AES, PM, TRNG, and WDT header files.
arch/arm/src/samd5e5/chip: Add pin multiplexing header files.
Various fixes to configuration system; fix metro-m4/nsh defconfig file.
configs/metro-m4: Add initial support for the Adafruit Metro M4 board.
arch/arm/src/samd5e5: Add peripheral clock helpers.
arch/arm/src/samd5e5/chip: Add PAC register definition header file. Fix some errors in the memory map header file.
arch/arm/src/samd5e5: Add chip.h headerf file.
arch/arm/src/samd5e5: Add PORT register definitions and support from SAML21.
arch/arm/include/samd5e5: Add interrupt vector definitions.
arch/arm/src/samd5e5: Add some boilerplate files. Correct some typos.
arch/arm/src/samd5e5/chip/sam_eic.h: Add EIC register definitions.
arch/arm/src/samd5e5/chip: Add OSC32KCTRL and OSCCTRL register definitions.
arch/arm/src/samd5e5/chip: Add GCLK, MCLK, and RSTC header files.
arch/arm/src/samd5e5/chip/sam_cmcc.h: Add CMCC register definitions
arch/arm/src/samd5e5/chip/sam_supc.h: Add SUPC header file.
arch/arm/src/samd5e5: Add start-up logic.
arch/arm/src/samd5e5: Add Make.defs file
arch/arm/src/samd5e5/chip: Add memory map header file.
arch/arm/include/samd5e5: Add chip.h header file.
arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig: Add configuration logic for the SAMD5x/Ex family.
- Added CRC32 functions for multicast address filtering.
- Do not reset PHY settings when doing an ifup
- Use chip's unique id as the device MAC
- Enable discard enet frames with errors at PHY layer
kinetis:sdhc fix SDIO driver so that DMA works
There were 2 problems. The first was that the interrupt did
test DINT and raise a completion events. But since DINT is
just an indication of DMA completion, TC is a valid way to
determine that the transfer is complete.
The second problem is that Software Reset For DAT Line
SDHC_SYSCTL[RSTD] clears the bits 24-0 in SDHC_PROTO
this looses the wide bus setting DTW
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
Change all remaining occurrences of SAMDL to SAMD2L2.
configs/: Change all remaining occurrences of SAMDL to SAMD2L2
configs/: Change all occurrences of CONFIG_SAMDL_* to CONFIG_SAMD2L2_*
arch/arm/src and include: Rename all directories from samdl to samd2l2. Change all configuration variable names and other usage from SAMDL to SAMD2L2.
kinetis:USB0 fix interrupt storm on error
The ERROR bit of USBx_ISTAT needed to be cleared once an
error occured.
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
configs/viewtool-stm32f107: Clean up some compilation errors. Now all builds correctly and is ready for test.
arch/arm/src/stm32: Do not condition building STM32 USB host logic on CONFIG_USBHOST. That then precludes building STM32 platforms with external USB host chips like the MAX3421E. Add an new, STM32-internal variable CONFIG_STM32_USBHOST that does the same job without such side-effects.
configs/viewtool-stm32f107: Add support for MAX3421E USB host.
stm32h7: fix some definitions for uart, add serial driver with FIFO enabled
* stm32h7: stm32_irq.c: extend irqinfo to support H7 family
* stm32h7: fix some definitions for uart, add serial driver with FIFO enabled
Approved-by: GregoryN <gnutt@nuttx.org>
stm32h7
stm32h7: compile with stm32_rcc.c
stm32h7: some PWR definitions
stm32h7: add some RCC defs and change some code style to be more like in other STM ports
stm32h7: basic clocks configuration
Approved-by: GregoryN <gnutt@nuttx.org>
stm32h7x3xx: add flash definitions
* libdsp: initial commit
* libdsp: cosmetics
* stm32f334-disco/buckboost: use a PID controller from libdsp
* stm32_adc.h: fix typo
* stm32_dac.c: set OUTEN bit for DAC1CH2 and DAC2CH1
* stm32_hrtim: cosmetic changes
* power/motor: direction parameter is now int8 + add overload fault
* libdsp: all floats with f-sufix
libdsp: add precision option for library
libdsp: add debug option for library and assertions in functions
libdsp: add current samples correction for SVM3
libds: add some motor control specific functions
libdsp: add basic speed observer
libdsp: fix phase shift in SMO observer
libdsp: add more logic to FOC
config/sim/dsptest: add dsptest configuration
* libdsp/lib_motor.c: remove unused comparation
* libdsp/lib_observer.c: update some comments
* stm32h7x3xx: add flash definitions
Approved-by: GregoryN <gnutt@nuttx.org>
Master
* libdsp: initial commit
* libdsp: cosmetics
* stm32f334-disco/buckboost: use a PID controller from libdsp
* stm32_adc.h: fix typo
* stm32_dac.c: set OUTEN bit for DAC1CH2 and DAC2CH1
* stm32_hrtim: cosmetic changes
* power/motor: direction parameter is now int8 + add overload fault
* libdsp: all floats with f-sufix
libdsp: add precision option for library
libdsp: add debug option for library and assertions in functions
libdsp: add current samples correction for SVM3
libds: add some motor control specific functions
libdsp: add basic speed observer
libdsp: fix phase shift in SMO observer
libdsp: add more logic to FOC
config/sim/dsptest: add dsptest configuration
* libdsp/lib_motor.c: remove unused comparation
* libdsp/lib_observer.c: update some comments
Approved-by: GregoryN <gnutt@nuttx.org>
This makes the user interface a little hostile. People thing of an MTU of 1500 bytes, but the corresponding packet is really 1514 bytes (including the 14 byte Ethernet header). A more friendly solution would configure the MTU (as before), but then derive the packet buffer size by adding the MAC header length. Instead, we define the packet buffer size then derive the MTU.
The MTU is not common currency in networking. On the wire, the only real issue is the MSS which is derived from MTU by subtracting the IP header and TCP header sizes (for the case of TCP). Now it is derived for the PKTSIZE by subtracting the IP header, the TCP header, and the MAC header sizes. So we should be all good and without the recurring 14 byte error in MTU's and MSS's.
Squashed commit of the following:
Trivial update to fix some spacing issues.
net/: Rename several macros containing _MTU to _PKTSIZE.
net/: Rename CONFIG_NET_SLIP_MTU to CONFIG_NET_SLIP_PKTSIZE and similarly for CONFIG_NET_TUN_MTU. These are not the MTU which does not include the size of the link layer header. These are the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename CONFIG_NET_6LOWPAN_MTU to CONFIG_NET_6LOWPAN_PKTSIZE and similarly for CONFIG_NET_TUN_MTU. These are not the MTU which does not include the size of the link layer header. These are the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename CONFIG_NET_ETH_MTU to CONFIG_NET_ETH_PKTSIZE. This is not the MTU which does not include the size of the link layer header. This is the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename the file d_mtu in the network driver structure to d_pktsize. That value saved there is not the MTU. The packetsize is the memory large enough to hold the maximum packet PLUS the size of the link layer header. The MTU does not include the link layer header.
Add support for STM32F746G-disco board SDRAM
* add support for STM32F746G-disco board SDRAM
* changed fb config to use SDRAM and fixed compilation
Approved-by: GregoryN <gnutt@nuttx.org>
lpc17: Removed duplicate configuration variable definitions from Kconfig: CONFIG_USBHOST_BULK_DISABLE, CONFIG_USBHOST_INT_DISABLE, and USBHOST_ISOC_DISABLE. These are global USBHOST configurations and are all defined in drivers/usbhost/Kconfig.
lpc17: Correct scope of naming of configuration variables: CONFIG_USBHOST_TDBUFFERS->CONFIG_LPC17_USBHOST_TDBUFFERS, CONFIG_USBHOST_TDBUFSIZE->CONFIG_LPC17_USBHOST_TDBUFSIZE, and CONFIG_USBHOST_IOBUFSIZE->CONFIG_LPC17_USBHOST_IOBUFSIZE
lpc17: Correct scope of naming of configuration variables: CONFIG_USBHOST_NEDS->CONFIG_LPC17_USBHOST_NEDS and CONFIG_USBHOST_NTDS->CONFIG_LPC17_USBHOST_NTDS
lpc17: Correct scope of naming of configuration variable: CONFIG_USBHOST_OHCIRAM_SIZE->CONFIG_LPC17_OHCIRAM_SIZE
stm32f7:I2C reset Configure I2C pins as GPIO output
Pins were reset to inputs in the deinit. This resets
them to outputs.
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/imxrt: Fix some first time compile issues.
arch/arm/src/imxrt: This brings the RTC implement to code complete but still untested.
arch/arm/src/imxrt: Add some RTC initialization logic.
arch/arm/src/imxrt: Flesh out most of the RTC driver lower half and LPSRTC support.
arch/arm/src/imxrt: Some inital, partial implementation of the HPRTC and LPSRTC.
arch/arm/src/imxrt: Add HPSRTC/HPRTC file framework (no logic, just skeleton files).
arch/arm/src/imxrt: Add HPRTC header file.
Some initial configuration logic for SNVS LPRTC and HP RTC.
are not allocated just after g_instack_alloc but these values show the addresses for interrupt stack of each CPU. So to set the stack
pointer based on these variables, temporal register has to be used.
stm32f7: Fix compile error caused by intentional use of fall through
Approved-by: Sebastien Lorquet <sebastien@lorquet.fr>
Approved-by: GregoryN <gnutt@nuttx.org>
A few bugfixes in initial testing on the i.MX6. Behavior seems a little more stable, but there are still memory corruption issues. Also print CPU number on assertion.
Add a file missed in the last big commit.
arch/arm/src/armv7a and imx6: Add support for per-CPU IRQ and FIQ interrupt stacks (bugfix). Add support so that up_assert will print the correct interrupt stack on an assertion (FIQ stack is still not printed).
arch/arm/src/lc823450: Combine the content of smp_macros.h into chip.h. Add support so that up_assert will print the correct interrupt stack on an assertion.
arch/arm: Remove support for CONFIG_ARMV7M_CMNVECTOR. It is now the only vector support available. Also remove CONFIG_HAVE_CMNVECTOR. That no longer signifies anything."
arch/arm/src/stm32: This commit removes support for the dedicated vector handling from the STM32 architecture support. Only common vectors are now supported.
arch/arm/src/lpc17xx: This commit removes support for the dedicated vector handling from the LPC17xx architectures. Only common vectors are now supported.
arch/arm/src/kinetis: This commit removes support for the dedicated vector handling from the Kinetis architectures. Only common vectors are now supported.
Squashed commit of the following:
sched: Rename all use of system_t to clock_t.
syscall: Rename all use of system_t to clock_t.
net: Rename all use of system_t to clock_t.
libs: Rename all use of system_t to clock_t.
fs: Rename all use of system_t to clock_t.
drivers: Rename all use of system_t to clock_t.
arch: Rename all use of system_t to clock_t.
include: Remove definition of systime_t; rename all use of system_t to clock_t.
Squashed commit of the following:
arch/arm/src/stm32f7: Some minor changes for clean compilation of LTDC.
arch/arm/src/stm32f7: Add overly support for LTDC driver header file.
arch/arm/src/stm32f7: Add overly support for LTDC driver file.
arch/arm/src/stm32f7: Add overly support for DMA2D driver header file.
arch/arm/src/stm32f7: Finishes overly support for DMA2D driver.
arch/arm/src/stm32f7: Partial overly support in DMA2D driver (a lot more to be donw)
arch/arm/src/stm32f7/chip: Clone overlay DMA2D register definitions from F4
arch/arm/src/stm32f7: Clone overlay configuration from stm32 F4
stm32f7: serial: Fix ioctl TIOCSSINGLEWIRE
The TRM notes that UE must be disabled in order to write HDSEL in
USART_CR3. This was not being done, so calls to TIOCSSINGLEWIRE were
silently failing.
This change checks the state of UE in USART_CR1, clears the UE bit
before writing HDSEL, then re-enables it if neccesary.
Approved-by: GregoryN <gnutt@nuttx.org>
LTDC fixes
* stm32_ltdc: Allows to use ltdc without overlay support
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32: Removes overlay dependency when LTDC is enabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32: Allows to configure initial chromakey for LTDC layer
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Fixes another compiler warning when dma2d is disabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Checks for register reload is done before continued
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Fixes eliminated register control by compiler optimization
When reading 1 byte from the SPI device the clock must be enabled and
immediately disabled. This section has been optimized by the compiler (-O2) to a
missing active spi clock. A subsequently block read failed because of missing
response from the spi device. This has been lead to a broken display
initializing.
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Fixes compiler errors when using LTDC and DMA2D
* stm32: ltdc and dma2d are are depends on FB_OVERLAY support
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_dma2d.h: Makes interface available when FB_OVERLAY is enabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32_ltdc: Fixes compiler error when blit support is disabled
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Updates lvgl board example
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
* stm32f429i-disco: Updates nxwm board example
Still nxwm_main is missing.
Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Signal handlers maybe run with interrupts enabled or disabled, depending on how the task the received the signal was blocked. (i.e.: If sem_wait() is called, then we disable interrupts, then block the currently running task). This could be dangerous, because user code would be running with interrupts disabled.
This change forces interrupts to be enabled in up_sigdeliver() before executing the signal handler calling up_irq_enable() explicitly. This is safe because, when we return to normal execution, interrupts will be restored to their previous state when the signal handler returns.
Squashed commit of the following:
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Re-implemented Dmitriy Linikov's change to support multi-banked FLASH on the STM32 F1 parts AFTER separating the FLASH support by architecture and implementing more standard base+offset register addressing. Now the change goes in rather cleanly.
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Use base + offset address to simplify implementation of dual bank flash.
Squashed commit of the following:
arch/arm/src/stm32/stm32f10xxf30xx_flash.c: Be consistent in file naming.
arch/arm/src/stm32l10xxf30xxx_flash.c: Separate STM32F10xx and STM32F30xx FLASH logic into a separate file.
arch/arm/src/stm32l20xx40xxx_flash.c: Separate STM32F20xx and STM32F40xxFLASH logic into a separate file.
arch/arm/src/stm32l15xx_flash.c: Separate STM32L15xx FLASH logic into a separate file.
Kinetis UART must be placed in 9 bit mode (M=1) with when 8 bit
data with parity is required. If left in 8 bit mode (M=0) with
parity then D7 of the TX/RX register becomes parity bit. Hence
what is called 9-bit or 8-bit Mode Select is a misnomer.
8 bit mode when parity is enabled is realy 7 bit with parity.
Previous BRFA was not cleared and or-ed into new BRFA, hence
buadrate was wrong. Where Baud Rate Fractional Divisor (BRFD)
UART baud rate = clock / (16 * (SBR + BRFD))
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt: Add cache operations to permit the Ethernet driver to work with the D-Cache enabled, at least in write-through mode.
Author: Jake Choy <jakearcx@gmail.com>
arch/arm/src/imxrt: The Ethernet driver is now functional, at least with the D-Cache off. The final fix was for the reference clock that needs to be forced to provide and input (SION).
Author: Gregory Nutt <gnutt@nuttx.org>
Fix trivial coding standard issue.
configs/imxrt1050-evk: Correct CONFIG_RAM_SIZE in all configurations (5Kb not 5Mb). I don't believe that CONFIG_RAM_SIZE is used at all in the i.MX RT so this is as grievous an error as it seems. Also enabled built-in applications in all NSH configurations.
arch/arm/src/imxrt/imxrt_enet.c: Trivial and cosmetic.
Cosmetic update to comments.
arch/arm/src/imxrt/imxrt_enet.c: Oops.. put the PHY interrupt init hooks in the wrong place. That is a one-time initialization but imxrt_initphy() is called on each ifup.
arch/arm/src/imxrt/imxrt_enet.c: Add hooks for board-specific PHY initialization (not yet needed, but there when needed).
Remove dangling white space at the end of lines
arch/arm/src/imxrt/Kconfig: Add option for board-specific PHY initialization.
configs/imxrt1050-evk/src: Add basic logic to support PHY interrupts. Incomplete.. needs additional support in imxrt_enet.c to 1. call to initialize PHY interrupt features, and 2. IOCTL commands to access PHY registers.
configs/imxrt1050-evk/README.txt: Trivial update.
configs/imxrt1050-evk/netnsh/defconfig: Disable LED support because pins conflict with PHY. Enable device statists. Enable NSH ifup and ifdown commmands
arch/arm/src/imxrt: Use macros in imxrt_periphclks.h vs. direct CCM CCGR accesses in Ethernet driver.
arch/arm/src/imxrt: Misc changes for a clean compilation of Ethernet deriver. configs/imxrt1050-evk/netnsh: Add an NSH configuration for testing Ethernet.
Author: Jake Choy <jakearcx@gmail.com>
arch/arm/src/imxrt: Initial WIP Ethernet driver.
arch/arm/src/imxrt: May eDMA channel linking a configuration option. Add support to select the DMA channel priority and pre-emption controls.
arch/arm/src/imxrt: Update some HowTo comments in the eDMA header file.
arch/arm/src/imxrt: Fix a logic error in parmater passing. Caller does not know actual channel number when setting up linked channel, only the channel handler.
arch/arm/src/imxrt: Fixes for clean eDMA driver build with Scatter/Gather enabled.
arch/arm/src/imxrt: Fixes for clean eDMA driver build with Scatter/Gather disabled.
arch/arm/src/imxrt: Add flags to DMA configuration to control transfer setup. Remove some user interfaces that are inconsistent with modular design.
arch/arm/src/imxrt: Update DMA channel interrupt handler.
arch/arm/src/imxrt: Add implementation of eDMA imxrt_dmach_start().
arch/arm/src/imxrt: Add implementation of eDMA imxrt_dmach_setup().
arch/arm/src/imxrt: Add eDMA imxrt_tcd_chanlink().
arch/arm/src/imxrt: Add eDMA imxrt_dmach_getcount; free allocated TCDs automatically when the DMA completes or is aborted.
arch/arm/src/imxrt: Add structures to support list of TCDs for Scatter/Gather DMA.
arch/arm/src/imxrt: Add eDMA imxrt_dmach_initconfig().
arch/arm/src/imxrt: Add eDMA imxrt_tcd_instantiate().
arch/arm/src/imxrt: Replacing some of the logic cloned from SAMv7 XDMAC with eDMA logic from NXP sample code. I am thinking that the eDMA is too complex to force into the same pattern as for other MCUs.
arch/arms/src/imxrt/imxrt_edma.c: Add support for in-memory TCDs.
arch/arm/src/imxrt/chip: Add an in-memory representation of the TCD in imxrt_edma.h
configs/stm32f4discovery/include/board.h: Add SPI DMA pins definitions to get CS43L22 audio DAC working
configs/stm32f4discovery/audio: Add board configuration for CS43L22 audio example
configs/stm32f4discovery: Update README
As with the MCU temperature and VREFINT measurement, this patch requires user to enable the corresponding channel first. For Vbat channel the ioctl cmd is IO_ENABLE_DISABLE_VBAT_CH, and its arg should be a pointer to bool which must be true to enable and false to disable the Vbat channel.
Moreover, since Vbat input contains a built-in voltage divider, it is highly suggested to disable Vbat input channel after measurement is done in order to prevent battery drain through the divider.
commit 7fd1f0d78546fa0315f4077b779efdd884e5bd53
Author: William Douglas <william@rocklandscientific.com>
Date: Tue May 15 13:19:31 2018 -0700
Add support for the second SDMMC device.
The second SDMMC device was already supported but
the clock was never enabled. This fixes that.
