nuttx

Author	SHA1	Message	Date
Abdelatif Guettouche	e424241d09	arch/risc-v/esp32c3: Remove the bignum test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	91cb9dafaf	arch/risc-v/esp32c3: Remove the RSA test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	652d77efd2	arch/risc-v/esp32c3: Remove the SHA test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	5d1c01aea7	arch/risc-v/esp32c3: Remove the AES test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	8288a04a0b	arch/xtensa/esp32: Remove the AES test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
zhuyanlin	b5134565fa	arch:xtens:mpu: modify acc and memtype to uint32_t The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-10-19 00:24:31 -05:00
Xiang Xiao	91398e73eb	arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-10-19 00:33:51 +02:00
Michal Lenc	3e1ce5f770	arch/arm/src/imxrt/hardware: add header file for ADC_ETC module This commit adds header file imxrt_adc_etc.h for external ADC trigger module. This contains only definitions of ADC_ETC registers and separate bits, implementation of ADC_ETC driver is yet to be done. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-10-17 16:50:59 +02:00
Abdelatif Guettouche	7549de49b4	arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock. If we repeatedly call up_cpu_pause and up_cpu_resume, there would be cases where the next call to up_cpu_pause happens while the other CPU is still responding to the previous resume request. In this case the DEBUGASSERT will trigger. We should allow the first CPU to wait until the other CPU has finished responding to the resume request. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-17 21:10:23 +09:00
Abdelatif Guettouche	7b43d11435	esp32_spiflash.c: Allocate only one variable to hold the cache state in single CPU mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	f54a929001	esp32_spiflash.c: Keep the index of the other CPU between SPI Flash operations. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	eeb68bda3d	xtensa_testset.c: Simplify the test-set function and remove some old comments. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	dfe1637864	esp32_spiflash.c: Pause the other CPU during flash operation. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	f2c2323642	esp32_intercpu_interrupt.c: Force the functions to internal SRAM. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	d2bc011719	arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait spinlock. If we repeatedly call up_cpu_pause and up_cpu_resume, there would be cases where the next call to up_cpu_pause happens while the other CPU is still responding to the previous resume request. In this case the DEBUGASSERT will trigger. We should allow the first CPU to wait until the other CPU has finished responding to the resume request. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 09:46:23 -07:00
Abdelatif Guettouche	591c1563b8	esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the code base. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	9e1d2ca95e	esp32_rt_timer.c: Group static variables into a struct and fix naming standard Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0dff3f2762	esp32_wifi_adapter.c: Use the specified spin lock when enabling/disabling interrupts. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	a50d673df7	esp32_wifi_adapter.c: Don't hold another spinlock when calling enter_critical_section, we already hold the global IRQ spinlock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	11216257cf	esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device specific spinlock, this will lead to deadlocks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	e847c61801	esp32_wifi_adapter.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	32f7471f9e	esp32_wlan.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	4ae1285124	esp32_emac.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	e64390d5e9	esp32_rt_timer.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	c61009c2cf	esp32/esp32_spi_slave.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	2273684cb1	esp32/esp32_spi.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0123243f9a	esp32/esp32_i2c.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0af9a49d9c	esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	698af43d78	esp32/esp32_freerun.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	04bd27400a	xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	19a096cdfe	arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei	ff705586bb	xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	4d5e0f8fe1	xtensa/esp32: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	99ac065d0a	risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	cc78541966	risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	ae25ebce4c	risc-v/esp32c3: Fix wrong arch in the path to chip folder Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Abdelatif Guettouche	a7d8d9dd98	esp32s2/tie.h: Run the file though detab. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	6d246eb18f	esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to ESP32-S2. This commit gets the correct S2 tie.h file Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	217fd97fd3	xtensa_coproc.S: Correctly save/restore coprocessor0 state. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	7420f245bc	xtensa_context.S: Save and restore SCOMPARE1 when necessary. SCOMPARE1 is used by some atomic instructions and need to be preserved during a context switch. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 06:32:17 -03:00
Alin Jerpelea	b9986ca016	arch: arm: update licenses to Apache Gregory Nutt is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-10-11 10:13:07 +02:00
jsun	c58fddb915	Open ble controller adaptation code N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-10-08 02:30:27 -07:00
Jari van Ewijk	e4752fbaee	S32K1xx arch: Add (optional) support for SPI native/hardware chip select	2021-10-05 06:07:18 -07:00
Gustavo Henrique Nihei	47e804b167	risc-v/esp32c3: Make BLE adapter code compliant to nxstyle Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-05 08:45:40 -03:00
Alan C. Assis	867c6d0636	esp32: Add initial support to Bluetooth Low Energy Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com> Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>	2021-10-04 15:10:37 -03:00
Abdelatif Guettouche	d22b4ec539	espxx_rng.c: Add "/" at the beginning of paths for consistency. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	c811cefa2d	esp32c3_rng.c: Remove unused functions. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	5c6a30c00b	esp32_rng.c: Remove the initialization guard. The init function is called only once during startup. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	6a262c5203	esp32_rng.c: Remove unused functions. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
liuhuan	ee6138e9ba	power: Open CONFIG_PM compilation failed include debug.h Signed-off-by: liuhuan <liuhuan16@xiaomi.com>	2021-09-30 07:16:07 -07:00
Jari van Ewijk	cf6dcbc6fd	S32K1XX arch: gpioread may also be used for output pins	2021-09-30 04:30:50 -07:00
Xiang Xiao	77bc1d1bdf	power/battery: Move the enumurate to the common place so the userspace program can handle the different battery driver equally Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-30 14:58:42 +09:00
P.Brier	b9d1fcb232	Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this)	2021-09-29 20:45:14 -07:00
Sara Souza	8a142f474e	xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it	2021-09-28 21:02:57 -03:00
Sara Souza	33f2d46bff	risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it	2021-09-28 21:02:57 -03:00
Alin Jerpelea	15a37c5a5a	arch: Omni Hoverboards: update licenses to Apache Gregory Nutt has submitted the SGA Omni Hoverboards has submitted the SGA David Sidrane has submitted the ICLA Mateusz Szafoni has submitted the ICLA Sebastien Lorquet has submitted the ICLA Paul Alexander Patience has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei	20341e6f17	risc-v/esp32c3: Enable support for "make bootloader" target This enables the provisioning of the bootloader binaries through the build system. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei	3c63cb522c	risc-v/esp32c3: Enable booting from MCUboot bootloader Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei	a5f9e29d78	xtensa/esp32s2: Enable support for "make bootloader" target This enables the provisioning of the bootloader binaries through the build system. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei	800678ca78	xtensa/esp32s2: Enable booting from MCUboot bootloader Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:21:53 -07:00
Jari van Ewijk	62c41a723b	s32k1xx_eeeprom.c - fix compiler warnings	2021-09-27 06:02:59 -07:00
Abdelatif Guettouche	5336704c77	esp32_start.c: Initialize the SPI RAM before enabling its cache. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei	c23986ec63	xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei	86518bdf25	tools: Trigger clean_bootloader on distclean for supported chips Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei	4ac3044cc3	xtensa/esp32: Enable build system to download or build bins from source Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-23 20:52:25 -07:00
Sara Souza	9c2c5d3919	risc-v/esp32-c3: fix pid initiatialization on esp32c3_rt_timer.c pid variable was initialized to -EINVAL to prevent rt_timer_deinit from delete an invalid kthread. But priv->pid was being overwritten in the rt_timer_init, so in case of failure to create a kthread, it would call rt_timer_deinit with a non expected initialization value.	2021-09-23 19:01:27 -07:00
Sara Souza	d0e7d7b77f	risc-v/esp32-c3: Remove _s of non static variables from esp32c3_rt_timer.c	2021-09-23 19:01:27 -07:00
Abdelatif Guettouche	f2f2040c44	esp32_spiram/psram/himem: Add and fix the files' sections. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Abdelatif Guettouche	3d8a6fb676	esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c file. This function is already defined in esp_himem and is used only when that file is built. We don't need another weak function. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Abdelatif Guettouche	2834d2a46f	esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Xiang Xiao	47c60b2de8	arch/arm: Remove -march and -mtune since -mcpu is enough https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-23 11:48:11 +02:00
Jari van Ewijk	bbb2f1f8c7	S32K1XX: Add LPI2C slave support	2021-09-22 19:36:34 -07:00
Sara Souza	962059f843	xtensa/esp32-s2: Adds oneshot device driver support	2021-09-22 22:53:54 -03:00
David Sidrane	6d299ce802	stm32h7:DMA_TRBUFF is DMA_SCR_TRBUFF	2021-09-22 22:48:10 -03:00
Sara Souza	fba6fa2dc1	xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2.	2021-09-22 17:18:24 -03:00
Sara Souza	2cd4f4af79	xtensa/esp32-s2: Adds freerun timer wrapper	2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei	e651ef0969	arch/risc-v: Remove CODE qualifier for RISC-V-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	06f4ee850a	arch/risc-v: Remove FAR qualifier for RISC-V-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	e9c17c9332	risc-v/rv32m1: Fix wrong position for ++ operator on serial driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	eca1f86294	arch/xtensa: Remove CODE qualifier for Xtensa-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	e13dd7dab9	arch/xtensa: Remove FAR qualifier for Xtensa-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	58f87ef443	xtensa/esp32: Fix wrong position for ++ operator on I2C driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Jari van Ewijk	e5f17f6604	S32K1XX: Add FlexIO registers	2021-09-22 03:15:42 -07:00
David Sidrane	a9ff808dd1	stm32xx:sdmmc/sdio remove redundant GPIO config The stm32_gpiosetevent calls stm32_configgpio. So the pin is infact restored to the SDMMC/SDIO D0. The seconday init, dropped interrupts in a debug build with HW stack checking on after the GPIO glich fixes and that was how it was detected.	2021-09-21 18:25:16 -07:00
David Sidrane	a8d5f21f81	stm32H7:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.	2021-09-21 18:25:16 -07:00
David Sidrane	5e19ebb818	stm32F7:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.	2021-09-21 18:25:16 -07:00
David Sidrane	d5e306e6f3	stm32:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source. This produced a 430 nS glich on a F4 @168 Mhz. It was a enough to corrupt an I2C device with a bus monitor.	2021-09-21 18:25:16 -07:00
Sara Souza	fc12d6888b	risc-v/esp32-c3: Group static variables into a struct and prevent an unitialized thread to be deleted	2021-09-21 15:45:59 +02:00
P.Brier	35824b449a	Added CONFIG_ETH0_PHY_DP83825I to imxrt_enet: make driver compile for teensy 4.1 (link detection needs more checks to see if it works as expected)	2021-09-21 10:27:33 -03:00
P.Brier	f9850cf433	Fixed imxrt flexcan driver compilation error due to incorrect scope of variable	2021-09-21 10:00:12 -03:00
Abdelatif Guettouche	9f4d7e4767	xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the backtrace. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-21 09:22:28 -03:00
Eero Nurkkala	812f504c16	mpfs: emmcsd: add Kconfig/Makefile and board files Add necessary Kconfig, Make.defs, Makefile and board file changes. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-09-18 12:18:09 -03:00
Eero Nurkkala	772432e7c3	mpfs: add emmcsd driver This adds the emmcsd driver for the Polarfire Icicle kit. The driver has been tested with several SD-cards, such as: - Kingston 32 GB SDS2 Canvas Select Plus - Kingston MicroSD Canvas Select Plus - Sandisk Extreme PRO 32 GB - Transcend 8 GB MicroSD The internal eMMC hasn't been tested comprehensively. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-09-18 12:18:09 -03:00
Xiang Xiao	75a119ac1c	arch: Compile up_puts in all Make.defs Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	71c61b11d9	arch/riscv: Rename riscv_puts to up_puts since it's a common API defined in include/nuttx/arch.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	0625f9888c	arch/z16: Implement up_puts function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	5b75df2203	arch/sim: Implement up_puts function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
jsun	f4b6bb281c	Update bl602 MTU_SIZE and TX_BUF_SIZE N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-09-17 22:11:30 -05:00
jsun	d489392d08	Add bl602 os adapter layer N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-09-17 22:11:30 -05:00
Abdelatif Guettouche	15b68b9abb	esp32_spiflash.c: Correctly disable APP's CPU cache. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-17 17:43:45 -03:00
Masayuki Ishikawa	204d88bcf3	arch: cxd56xx: Replace the critical section with spinlock in cxd56_serial.c Summary: - This commit replaces the critical section with spinlock in cxd56_serial.c Impact: - None Testing: - Tested with spresense:rndis_smp, spresense:rndis and spresense:rndis_wifi Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-09-16 21:56:40 -05:00
Alin Jerpelea	48f92e6f1d	author: Bill Gatliff : update licenses to Apache Gregory Nutt has submitted the SGA Bill Gatliff has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-16 21:56:08 -05:00
Gustavo Henrique Nihei	52cea558af	risc-v/esp32c3: Make the semaphore timeout on I2C configurable Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-16 14:07:26 -03:00
Gustavo Henrique Nihei	b33ccd01cf	xtensa/esp32: Make the semaphore timeout on I2C configurable Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-16 14:07:26 -03:00
zhuyanlin	7947e50f06	xtensa:backtrace: flush to stack when in interrupt The registers may be in window during interrupt. Flush window stack to stack first. And fix warning in build. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:53:35 -05:00
Peter Bee	2a8b076b38	risc-v/esp32c3: fix pwm driver bug Wrong offset sign and pwm multichan fix Signed-off-by: Peter Bee <bijunda1@xiaomi.com>	2021-09-16 08:38:49 -03:00
zhuyanlin	cdb441cc3f	arch:xtensa:dumpstate: use sched_dumpstack Use sched_dumpstack instead. The backtrace infomation like xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello xtensa_registerdump: PC: 202b32b8 PS: 00060030 xtensa_registerdump: A0: a02acb87 A1: 20998d10 A2: ffffaaaa A3: 12345678 xtensa_registerdump: A4: a02ba26c A5: 209949c0 A6: 20990994 A7: 00000258 xtensa_registerdump: A8: a02b32af A9: 20998cb0 A10: 0000000f A11: 209949a0 xtensa_registerdump: A12: a02be95c A13: 20994980 A14: 00000003 A15: 209949d0 xtensa_registerdump: SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa xtensa_registerdump: LBEG: 00000000 LEND: 00000000 LCNT: 00000000 xtensa_registerdump: TMP0: 202b1512 TMP1: 20998af0 sched_dumpstack: [BackTrace\| 3\|0]: 0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f 0x40023 0x202b32b0 sched_dumpstack: [BackTrace\| 3\|1]: 0x202acb87 0x202a86a4 Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	6e0f84dc88	arch:xtensa: add up_backtrace support Up_backtrace can be backtrace from task or interrupt. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	3acdbef60d	xtensa:arch: force up_getsp to inline Up_getsp may be not inline in gcc, thus get the sp is up_getsp function's sp, not the caller function. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	583dce0b98	arch:xtensa: remove WSBITS/WBBITS to core.h Remove WSBITS/WBBITS macro to core.h as may be used by arch common code. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
Cis van Mierlo	b316c679c1	S32K1xx: added PM support	2021-09-15 12:20:23 -03:00
SPRESENSE	74df4b70b3	drivers: video: Rearchitect video driver Rearchitect video driver: - Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s), and support them. - CISIF driver supports new video I/F struct imgdata_ops_s. - ISX012 driver supports new video I/F struct imgsensor_ops_s. - Move ISX012 driver to general driver directory.	2021-09-15 07:06:35 +02:00
Juha Niskanen	4487b352c0	arch/arm/src/stm32l4: fix baud rate setting for LPUART Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-14 08:57:25 -07:00
Harri Luhtala	7e3c813346	arch/arm/src/stm32l4: LPUART1 support Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>	2021-09-14 08:57:25 -07:00
Abdelatif Guettouche	198c30eaa6	stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-14 22:50:43 +08:00
chao.an	ba9b829372	arch/arm: correct the function name from arm_getsp() to up_getsp() Signed-off-by: chao.an <anchao@xiaomi.com>	2021-09-14 22:48:47 +08:00
Cis van Mierlo	91c945a2e8	s32k1xx: added way to get the reset cause in proc fs	2021-09-14 08:35:41 +02:00
Sara Souza	83a9c2b24b	xtensa/irq.h: Fixes the routine that clears the processor interrupt	2021-09-13 17:01:49 -03:00
Alin Jerpelea	bb54ed4227	author: OffCode Ltd : update licenses to Apache OffCode Ltd has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-13 22:43:36 +08:00
zhuyanlin	8e6fbe700e	xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-13 14:38:57 +08:00
Xiang Xiao	850367d5bb	arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-12 09:09:42 -03:00
Jukka Laitinen	3654db3517	mpfs: Modify IRQ handling to support also HART0 on PF Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-09-11 23:33:01 +08:00
Janne Rosberg	8b560e7894	mpfs/i2c: fix bus initialize for i2c1	2021-09-11 23:33:01 +08:00
Janne Rosberg	1e3919e55a	mpfs/corepwm: remove wrong header include	2021-09-11 23:33:01 +08:00
Janne Rosberg	7db3456824	risc-v/mpfs: serial: add termios support and init device clocks	2021-09-11 23:33:01 +08:00
Janne Rosberg	aa057e25f2	mpfs/i2c: adapt to sysreg define changes	2021-09-11 23:33:01 +08:00
Janne Rosberg	dc54ba924e	mpfs/spi: adapt to sysreg define changes	2021-09-11 23:33:01 +08:00
Janne Rosberg	3e6b19dfc5	risc-v/mpfs: add more sysreg defines and fix clock and reset defines	2021-09-11 23:33:01 +08:00
Abdelatif Guettouche	31aa616bf2	stm32_serial.c: Don't fake a TX interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-10 15:15:44 -07:00
David Sidrane	41e1696b27	stm32f4:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
David Sidrane	e488f0047d	stm32h7:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
David Sidrane	21f049b43a	stm32f7:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
Sara Souza	acf18bd82d	risc-v/esp32-c3: refactor the Wi-Fi board logic. This commit moves the Wi-Fi initialization to Wi-Fi specific file and to spiflash initialization. It also reserves one partition for Wi-Fi use and for general use, and makes it possible to me mounted by several FS.	2021-09-09 20:14:04 +08:00
Sara Souza	11068fad1b	risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions	2021-09-09 20:14:04 +08:00
Harri Luhtala	d4e59b7e8d	arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>	2021-09-09 08:26:08 -03:00
Abdelatif Guettouche	4ef859924b	esp32_serial.c: Release the spinlock before calling uart_xmitchars, this functions will call esp32_txint again which leads to deadlock since esp32_txint has already locked the spinlock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-09 19:35:17 +09:00
Abdelatif Guettouche	b5bb1fb8a3	esp32_serial.c: Replace critical section by a device specific spin lock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-09 19:35:17 +09:00
Abdelatif Guettouche	f47d28c108	esp32_serial.c: Don't fake an interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-08 09:27:08 -03:00
zhuyanlin	26b4bb3075	xtensa:cache: fix typo error use addr instead of add	2021-09-08 11:19:02 +02:00
YAMAMOTO Takashi	4f7226ac4a	arch/avr: Remove -nostartfiles -nodefaultlibs from LDFLAGS These options are not ld options. The recent versions of ld complain on them. https://sourceware.org/pipermail/binutils/2021-June/116826.html	2021-09-08 09:40:48 +08:00
YAMAMOTO Takashi	58bdcbab9b	Revert "Make: use gcc as LD" This reverts commit `45672c269d`. Because: * It's very confusing to have cc as LD. * I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are supposed to do when we use LD directly. It would be simpler to remove them from our LDFLAGS.	2021-09-08 09:40:48 +08:00
Jari van Ewijk	5f63fa391f	Fix error in s32k118_pinmux.h	2021-09-07 17:34:19 -07:00
zhuyanlin	7b5c39a9d3	arch:xtensa: add xtensa_cache code support Add xtensa_cache code support	2021-09-07 13:33:31 +08:00
zhuyanlin	d6fe0f18f5	arch:xtensa: add XTENSA_CACHE config support Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE	2021-09-07 13:33:31 +08:00
YAMAMOTO Takashi	5ad1cba338	Revert "arch: Replace ar and nm with gcc-ar and gcc-nm" This reverts commit `b05737d78f`. Because it broke clang-based builds.	2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos	eb48a0dbe0	Fix in STM32_UART8 Kconfig.	2021-09-07 10:52:44 +08:00
Jukka Laitinen	1b75b5d5aa	Fix compilation of arm protected build Correct typos in include/nuttx/arch.h and suppress "'noreturn' function does return" warning coming from arm_pthread_exit.c Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-09-07 00:31:47 +08:00
Juha Niskanen	b70ae9ae82	arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access This is currently only used on STM32L4+ devices. Page erase in flash_erase() function supports only dual-bank mode so it makes little sense to configure this for unsupported single-bank mode. Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-04 14:31:16 +08:00
Sara Souza	26397c6695	xtensa/esp32: Wi-Fi board logic refactoring. This commit removes the initialization of the Wi-Fi partition from the Wi-Fi board logic and moves it to the SPI Flash board code. It creates 2 different partition (one for Wi-Fi and one for general use). It also allows these partitions to be mounted over several FSs.	2021-09-04 14:30:02 +08:00
Juha Niskanen	508215581f	arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-03 09:55:54 -03:00
liucheng5	fdb9576d7a	feature: driver: Add a Linux SPI into simulator. When SIM_SPI is valid, a specified Linux SPI device ‘spidevN.P’(N is bus number and P is CS number) is attached to nuttx simulator, shown as 'spi0' under /dev. One may type spi command (need SPITOOL valid) in NSH to control the Linux SPI and exchange data, other devices such sensors can use it to debug in simulator on a Ubuntu PC. Note that a USB<>SPI module (e.g. CH341A/B) should be plugged in to achieve Linux SPI ports. Change-Id: I275b2c2bbf6d14bcdf514c89efb9a2264d69e9a3 Signed-off-by: liucheng5 <liucheng5@xiaomi.com>	2021-09-03 18:15:25 +08:00
Alin Jerpelea	a20d4ac4ec	author: Aleksandr Vyhovanec: update licenses to Apache Aleksandr Vyhovanec has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-03 17:38:33 +08:00
Xiang Xiao	b05737d78f	arch: Replace ar and nm with gcc-ar and gcc-nm to make enable LTO easily Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-02 10:02:14 -03:00
zhuyanlin	fd9ce0137e	arch:xtensa: add xtensa mpu support Add support for Xtensa Memory Protect Unit. Change-Id: I27e2f05daae24429ef7513d843b4f217daeefa0d	2021-09-02 09:17:26 -03:00
Sara Souza	8081228556	xtensa/esp32-s2: Adds support to the timer driver Only one more support for ESP32-S2 chip.	2021-09-01 14:10:01 -03:00
Gustavo Henrique Nihei	2071aadc0e	sim: Inhibit stack protector on stack coloration function Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-01 23:11:03 +08:00
Michal Lenc	1ec0258407	arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs CAN_ESR2 register was having problems of havng the correct values when the bus was busy (with 3 and more nods). The register bit fields were incorrectly indicating that there is no free MB and would not updated itself from this state which was causing the applications to freeze on write. This change relies only on a software control which should avoid the problems described above. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-08-31 14:47:41 -03:00
Masayuki Ishikawa	24697e8f67	arch: x86_64: Fix idle stack allocation Summary: - I noticed that qemu-intel64:nsh does not work - And I found that commit `6e6eecaa73` affected this issue - This commit changes idle stack allocation to fix the issue Impact: - None Testing: - Tested with qemu-intel64:nsh and qemu-intel64:ostest Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-08-31 17:06:59 +08:00
Oleg	e95f23ef8b	arch/arm/stm32f7/stm32_irq: Fix format strings	2021-08-31 16:56:55 +08:00
Alin Jerpelea	da92258333	arch: k210: remove extra license information the Apache license header uses a standard format and the extra information should be removed. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-31 08:20:18 +09:00
Xiang Xiao	b0c782255c	libxx: Change CXX_LIBSUPCXX to LIBSUPCXX align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX) Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-28 17:14:48 -03:00
zhuyanlin	9ea7676731	arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS The name used in Tensilica support file core-isa.h for all vendors is `XCHAL_NUM_INTLEVELS`. Use a new name may be confused by newer porting xtensa arch. Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de	2021-08-28 21:51:45 +02:00
zhuyanlin	cd18d1f050	arch:riscv: remove arch atomic, use libc atomic when need It is more common for implement in libc/machine Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e	2021-08-28 13:17:30 -03:00
Xiang Xiao	f0001574ed	arch/armv8-m: Update per the latest architecture reference manual https://developer.arm.com/documentation/ddi0553/latest Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-27 11:39:27 +02:00
Abdelatif Guettouche	1385ea7673	arch/esp32: Properly handle GPIO interrupt in SMP. The PRO CPU and APP CPU have different peripherals for GPIO interrupts. Each CPU needs to allocate an interrupt and attach it to its GPIO peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-27 13:24:00 +09:00
chao.an	bcce3314e5	arch/arm/cortex-m: add up_backtrace support add up_backtrace support based on push/branch instruction Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 18:31:51 +08:00
chao.an	d5d6297ca1	arch/arm/assert: enhance the assert dump show the all tasks info including backtrace and registers Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 13:31:08 +08:00
chao.an	f14bd44001	arch/armv7: add up_backtrace support based on frame pointer This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory This feature can not be used in THUMB2 mode if you are using GCC toolchain, More details please refer: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172 Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 13:30:08 +08:00
Kapil Gupta	ec99e11f5e	esp32/softap: Enable the WPA2 by default to ask user password Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com> Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>	2021-08-26 13:26:57 +08:00
ligd	f1aec38ffa	arm: add ARM_HAVE_NEON to Kconfig Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-08-26 13:25:43 +08:00
Abdelatif Guettouche	fc594c5d25	esp32_irq.c: Extend the CPU interrupt/peripheral map to include the status of the interrupt (enabled/disabled). Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	810ed19b8f	arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt Matrix. This allows manipulating interrupts from both CPUs. Internal interrupts however, still need to be disabled/enabled by each CPU. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	a7abd56448	arch/xtensa: Move the Xtensa specific part of interrupts to xtensa/include/irq.h Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	470799b0b3	arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used only inside this file. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	04cd520293	arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	79cc12c034	arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. They do the same thing (manipulate interrupts) keeping them separated was making things harder. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	237aebb7e1	arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register address of a peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	02c17c3169	arch/esp32: Simplify the interrupt allocation process. Allocating and attaching interrupts were both exported outside, however these two move hand in hand and we don't have to expose these details. Also, the parameters passed are saved and will be used to retrieve information about the interrupt and the attached peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	eefe7ebe5f	xtensa/esp32_cpuint: export only one function to allocate a CPU interrupt. That function will have a parameter to decide whether to allocate a level sensitive interrupt or an edge sensitive interrupt. All the drivers are also updated with this API change. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	dbdec45049	arch/xtensa/src/common: Use irq_spin APIs in modifyregXX Replace enter_critical_section with spin_lock_irqsave. Replace leave_critical_section with spin_unlock_irqrestore. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-25 23:32:40 +08:00
Abdelatif Guettouche	5ff703d5d0	arch/*_testset: Fix few typos. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-25 00:20:20 +08:00
Alin Jerpelea	07d528fd8d	license: Ken Pettit: update licenses to Apache Ken Pettit is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-23 11:41:41 +08:00
chao.an	6cfb132232	arch/cortex-m: replace arm_switchcontext to c-style Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-22 14:44:01 +08:00
chao.an	68d6dbf86f	arch/riscv/assert: enhance the assert dump enhance the assert dump to show the all tasks info including backtrace and registers [ 7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init [ 7.617000] [ EMERG] riscv_dumpstate: Call Trace: [ 7.617000] [ INFO] [BackTrace\| 3\|0]: 0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894 [ 7.617000] [ INFO] [BackTrace\| 3\|1]: 0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56 [ 7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0 [ 7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074 ... ... [ 7.617000] [ EMERG] riscv_showtasks: Tasks status: [ 7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0 [ 7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976 [ 7.617000] [ INFO] [BackTrace\| 0\|0]: 0x4200787e 0x3fc94ff0 [ 7.617000] [ EMERG] riscv_registerdump: EPC:4200787e [ 7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074 ... [ 7.617000] [ EMERG] riscv_taskdump: [ 7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1 [ 7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016 [ 7.617000] [ INFO] [BackTrace\| 1\|0]: 0x420082a6 0x4200328c 0x42001ab4 0x42001a42 [ 7.617000] [ EMERG] riscv_registerdump: EPC:420082a6 [ 7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000 ... Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-21 14:58:21 +08:00
chao.an	333191becd	riscv/backtrace: add up_backtrace support Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-21 14:56:34 +08:00
Abdelatif Guettouche	2925d4956b	xtensa/esp32: Use up_cpu_index instead of this_cpu. this_cpu requires sched.h to be included.	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	5d626f7267	xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs are do not go through the regular process where we attache the CPU interrupt to a peripheral and update our map, also, they are fixed and a have reserved CPU interrupt, thus hard code their values at startup. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	56a7f3b651	arch/xtensa/esp32: Update the drivers regarding the API change in IRQ handling. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	5be9f24fe5	arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. At this point we are in a critical section and have all the necessary information to disable the interrupt properly (CPU, and CPU interrupt). Leaving it to the drivers will complicate things as converting from IRQs to CPU interrupts could be tricky in SMP mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	97dca8fe10	arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and irq.c Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	633cdf8e27	arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. This map also keeps track of the CPU that attached the IRQ. This will be used to properly disable the interrupt in the correct CPU in SMP mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Sara Souza	e092c457e6	xtensa/lx7: Fix the CROSSDEV variable	2021-08-20 16:48:20 +02:00
Xiang Xiao	af72376773	fs: Remove magic field from partition_info_s since it is wrong and impossible to return file system magic number from the block or mtd layer. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-20 09:19:52 -03:00
Antti Vähälummukka	6eb73ced51	arch/risc-v/src/mpfs: Add CorePWM driver Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals	2021-08-20 08:56:30 -03:00
Xiang Xiao	4b41579ccf	arch/armv8-m: Add SAU support Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-20 10:22:43 +09:00
raiden00pl	78962165d8	arch/stm32: add 3-phase Hall effect sensor lower half	2021-08-19 08:19:38 -07:00
chao.an	1060953567	sched/backtrace: add sched_backtrace support Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-19 01:30:50 -07:00
chao.an	0a8d951837	arch/arm: correct the frame pointer register declare In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code. In AArch64, the frame pointer is stored in register X29. Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-19 01:26:07 -07:00
Abdelatif Guettouche	cd0f64d779	xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-18 10:49:58 -03:00
raiden00pl	532ec126e9	stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y. Fix for https://github.com/apache/incubator-nuttx/issues/4353	2021-08-18 04:43:32 -07:00
Abdelatif Guettouche	a220766d57	xtensa.h: Remove unused function prototype. ESP32 uses a different function to start the app CPU and no other xtensa CPU uses this __cpu1_start function. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-18 04:41:40 -07:00
chao.an	e37d8da074	riscv/common: add CURRENT_REGS declare in RV32 Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-18 04:40:38 -07:00
Juha Niskanen	e02e1c25f6	arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Change-Id: I74050913643db23b4d03abaf516989ff3cdac142	2021-08-17 06:27:18 -07:00
Alin Jerpelea	4b20cf30c0	arch: misoc: update licenses to Apache Gregory Nutt is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-16 07:11:32 -07:00
Alin Jerpelea	351091ed75	author: Pierre-noel Bouteville: update licenses to Apache Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-16 07:11:32 -07:00
Xiang Xiao	71269811ca	mtd: Implement BIOC_PARTINFO for all drivers Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-16 10:08:26 -03:00
Virus.V	5a1de89370	riscv/bl602: Fix that AP cannot be start when STA have been started.	2021-08-16 02:06:59 -07:00
Xiang Xiao	f63d1cfbbb	arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-15 10:50:52 +02:00
Xiang Xiao	fad0c3b38b	arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-14 11:41:59 -07:00
Xiang Xiao	33666832c5	arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-14 11:41:59 -07:00
Abdelatif Guettouche	5b350f3a0f	arch/*_reprioritizertr.c: Fix typos in comments. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei	1dfcc6ab49	xtensa/esp32: Enable boot from Espressif's port of MCUboot Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-08-13 08:44:20 -03:00
zhuyanlin	1a1b1cc2b4	arch:xtensa: replace include file from src/chip_xxx to chip.h Use chip.h as a standard include file, replace chip_xxx in src dir	2021-08-12 16:18:35 +02:00
zhuyanlin	30a2338e92	arch:esp: create chip.h header for chip src code. Create chip.h header for esp src code.	2021-08-12 16:18:35 +02:00
zhuyanlin	6d592256fb	arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h Those header contain syntax not be recognize by gnu assembler.	2021-08-12 16:18:35 +02:00
Alexander Vasiljev	4229099944	arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart.	2021-08-12 08:07:18 -03:00
Xiang Xiao	6b6c11f0ad	mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-12 08:01:29 -03:00
Xiang Xiao	d1687418db	mtd: Remove the empty MTDIOC_XIPBASE implmentation Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-11 09:50:51 -03:00
zhuyanlin	e333733053	xtensa:coproc: fix XTENSA_CP_ALLSET error in some case Consider follow coprocessor configuration case: \#define XCHAL_CP_NUM 1 /* number of coprocessors / \#define XCHAL_CP_MAX 2 / max CP ID + 1 (0 if none) / \#define XCHAL_CP_MASK 0x02 / bitmask of all CPs by ID / \#define XCHAL_CP_PORT_MASK 0x00 / bitmask of only port CPs / \ \#define XCHAL_CP1_NAME "AudioEngineLX" \#define XCHAL_CP1_IDENT AudioEngineLX \#define XCHAL_CP1_SA_SIZE 208 / size of state save area / \#define XCHAL_CP1_SA_ALIGN 8 / min alignment of save area / \#define XCHAL_CP_ID_AUDIOENGINELX 1 / coprocessor ID (0..7) */ In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all vaild coprocs. Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f	2021-08-10 19:44:55 -07:00
Abdelatif Guettouche	054e284785	*_cpustart.c: Fix typos in function description. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos	5b7ff03f40	lpc17_40: Fixed I2C port sanity check.	2021-08-10 09:04:33 -07:00
raiden00pl	2b3106fb47	Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX	2021-08-10 11:19:05 -03:00
raiden00pl	51b24c4bad	stm32/qenco: add support for QEIOC_SETPOSMAX	2021-08-10 11:19:05 -03:00
raiden00pl	092a0c8453	stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit Previous implementation has always expanded the width of the timer to 32-bit. This feature is not always needed and should be configurable from Kconfig.	2021-08-10 11:18:40 -03:00
raiden00pl	b0c9a6133e	stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit STM32F3 has timers of the same length as in STM32F4.	2021-08-10 11:18:40 -03:00
raiden00pl	3dd385ac0c	stm32/qenco: add support for STM32G4 This required generalization of RCC definitions that are not compatible with previous chips	2021-08-10 11:18:40 -03:00
raiden00pl	21f59c874f	stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1	2021-08-10 11:18:40 -03:00
Sara Souza	af6c311fd1	risc-v/esp32-c3: Complete the support for RWDT	2021-08-10 11:17:15 -03:00
Sara Souza	61ab4f9f14	xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk	2021-08-10 11:15:51 -03:00
Sara Souza	67d29e7537	xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is.	2021-08-10 11:15:51 -03:00
zhuyanlin	5820972727	arch:xtensa: add arch stdarg.h include file for xtensa Add arch/include/stdarg.h for xtensa. Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56	2021-08-09 17:58:25 -03:00
Xiang Xiao	776458143c	fs/hostfs: Support fchstat and chstat callback Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-09 17:55:44 -03:00
Xiang Xiao	7e0db977cc	arch/arm: Add CONTROL register bit field definition and replace all hardcode value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-07 09:20:10 -03:00
Daniel P. Carvalho	a7be1c9a2e	stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop.	2021-08-05 14:48:44 -03:00
Michal Lenc	a3986eeba3	arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in Master Control Register are set at once after all channels are configured. Setting LDOK bit enables the driver to load prescaler, modulus and PWM values of corresponging submodule and start PWM output. Setting all bits at once instead of doing it separately can help avoiding the channels to be out of sync with each other. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-08-05 09:57:49 -07:00
zhuyanlin	ec17cad69d	arch:xtensa:include chip/irq.h instead of depend on chip config. Many duplicate code when more chips add-in, follow arch/arm/include/irq.h method, use chip/irq.h instead. Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e	2021-08-05 10:08:48 +02:00
zhuyanlin	cec6aeb059	arch:xtensa:vector: fix typo error in level4_ventor Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3	2021-08-04 20:16:41 -07:00
zhuyanlin	51d13df317	arch: xtensa: save current SP before overwrting in dispatch_c_isr. In levelx(2,3,4,5)_handler, first need to save sp in a12, then after dispatch_c_isr we can restore sp from a12. Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3	2021-08-04 20:16:41 -07:00
Daniel P. Carvalho	2593089f84	stm32_dac: add support for DAC3	2021-08-04 20:22:58 +02:00
zhuyanlin	4fc5b62ec3	arch:xtensa: use letter 'i' in inline assemble constraint instead of I Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I', letter 'i' is more common in GNU assembler. Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f	2021-08-04 18:23:40 +02:00
zhuyanlin	9a34705b80	arch:xtensa_testset: remove include arch/spinlock.h In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to build error as multi definition with spinlock_t. Nuttx/spinlock.h will include arch/spinlock.h when needed. Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c	2021-08-04 18:18:11 +02:00
zhuyanlin	355133f218	arch:xtensa: add new GNU toolchain for xtensa. Add support xcc,xclang GUN toolchin in xtensa, ESP toolchain is default. Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c	2021-08-04 18:16:14 +02:00
Xiang Xiao	6a396eb224	Fix the printf warning after off_t change Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764	2021-08-04 06:48:30 -07:00
Abdelatif Guettouche	238a96e7de	arch/esp32_cpuint.c: Simplify up_disable/enable_irq. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-03 19:52:12 -07:00
Abdelatif Guettouche	4f2f2ef9fb	arch/xtensa: Get the cpu member out of the read only structure. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-03 19:52:12 -07:00
Abdelatif Guettouche	239f0e257b	arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. This is used when dettaching. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-03 19:52:12 -07:00
Abdelatif Guettouche	0ca5fb4edc	arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP mode. up_cpu_index already does that. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-03 19:52:12 -07:00
Abdelatif Guettouche	3e44c347fd	arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an interrupt. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-03 19:52:12 -07:00
licheng	431df45e97	EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE	2021-08-02 23:20:34 -07:00
Alexander Lunev	95abf562f4	boards: added a basic support for chipKIT Wi-FIRE board; added Sourcery CodeBench Lite for MIPS ELF Toolchain option; corrected inaccuracies in Photon board and EMW3162 board README.txt files.	2021-08-01 08:45:02 -07:00
buyuer	ae3709819c	Use exit func iml host_abort. When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM. Signed-off-by: buyuer <dingddding@163.com>	2021-07-31 08:02:10 -07:00
Xiang Xiao	5d1a444812	Replace __attribute__ ((unused)) with unused_code Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	69df58c2e8	Replace __attribute__((no_instrument_function)) with noinstrument_function; Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	7bcd29dae0	Replace __attribute__((naked, no_instrument_function)) with naked_function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	919f8a9a72	Define __ramfunc__ to "locate_code(".ramfunc") farcall_function noinline_function" instead of "__attribute__ ((section(".ramfunc"),long_call,noinline))" Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	21b69cfd5d	Replace all __attribute__((weak)) with weak_data/weak_function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	007adc7736	Replace all __attribute__((section(x)) with locate_data(x) Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Xiang Xiao	b3f9ffbe72	Replace all __attribute__((aligned(x)) with aligned_data(x) Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei	a7a922611b	xtensa/esp32: Enable the allocation of multiple SPI Flash partitions Currently the "esp32_spiflash_alloc_mtdpart" allocates a statically-defined partition from "offset" and "size" set via Kconfig. This commit changes the function interface to receive those information as arguments, enabling the creation of multiple MTD partitions with different offsets and sizes. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-07-29 20:17:13 +02:00
Alexander Lunev	98e7776714	pic32mz: added support for PIC32MZ2048EFG MCU	2021-07-29 07:46:26 -07:00
raiden00pl	f9937b28cc	stm32g4: add CORDIC driver	2021-07-28 14:23:13 -03:00
raiden00pl	6128b298ee	stm32g4: add CORDIC definitions	2021-07-28 14:23:13 -03:00
Sara Souza	cdbfacc1fe	risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it	2021-07-27 20:43:34 -07:00
Sara Souza	857414e95d	xtensa/esp32: expose SPI2 as a char driver	2021-07-27 09:55:49 -07:00
Michal Lenc	9fc806984c	adc: add ioctl command to get the number of configured channels Number of configured ADC channels is currently only defined in board level section, typically in xxx_adc.c file. This commit introduces ioctl command ANIOC_GET_NCHANNELS that returns the number of configured channels which is determined by the driver code. The change can allow the applications to be more flexible when it comes to multiple ADC devices with different number of configured channels. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-07-26 19:45:47 -07:00
Sara Souza	400d927011	xtensa/esp32s2: Disable wdt and wrap it.	2021-07-26 19:44:30 -07:00
Sara Souza	0794991a07	risc-v/esp32-c3: Disable wdt in the start function.	2021-07-26 19:44:30 -07:00
Sara Souza	5baeb7430b	xtensa/esp32: Wrap wdt deinitialization in a function	2021-07-26 19:44:30 -07:00
Jiuzhu Dong	7e393762a7	sim/rptun: optimize multi-core startup and don't need to wait each other. Change-Id: I6172823c84a96e4082fa5f33bdb05d7bd1d3b056 Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-07-26 19:38:07 -07:00
Gustavo Henrique Nihei	2d676f5e46	xtensa/esp32: Enable configuration of GPIO pad's drive strength Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-07-26 19:37:06 -07:00
Jiuzhu Dong	e98220c81a	sim/cmdline: save boot cmdline to g_argc g_argv Change-Id: I989850a09528e3868957284c9f419d0992ae8d1f Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-07-26 19:35:58 -07:00
Xiang Xiao	5e01fe050a	arch/sim: Copy include/nuttx/config.h to the local folder so the source code compiled by host environment can include config.h directly and then avoid pass Kconfig option through Makefile manually Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf	2021-07-27 07:44:33 +09:00
Xiang Xiao	3488a98bd7	sim: Correct the typedef in nuttx/hostfs.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: I5fbfd519417c5686325822549c068b1d42f83946	2021-07-27 07:44:33 +09:00
Jiuzhu Dong	5029712283	renesas/rx65n: add long type for all PRI*PTR Error: wqueue/kwork_thread.c:202:3: error: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format=] snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue); Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-07-26 08:44:05 -07:00
Michal Lenc	7354ab187e	pwm: add option to break the loops when using multiple PWM channels PWM drivers currently use channel number 0 for the channels that are not used by the application. This commit adds number -1 which indicates that all following channels are not configured and that the loop can be broken. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-07-26 10:34:16 -03:00
Nathan Hartman	b92aeb8209	Fix various typos arch/arm/src/eoss3/eoss3_serial.c: arch/arm/src/imxrt/hardware/imxrt_flexcan.h: arch/arm/src/imxrt/imxrt_flexcan.c: arch/arm/src/imxrt/imxrt_flexpwm.c: arch/arm/src/imxrt/imxrt_lpi2c.c: arch/arm/src/kinetis/kinetis_flexcan.c: arch/arm/src/nrf52/hardware/nrf52_rtc.h: arch/arm/src/nrf52/nrf52_clockconfig.c: arch/arm/src/nrf52/nrf52_radio.c: arch/arm/src/nrf52/nrf52_tim.c: arch/arm/src/rtl8720c/amebaz_depend.c: arch/arm/src/s32k1xx/Kconfig: arch/arm/src/s32k1xx/s32k1xx_flexcan.c: arch/arm/src/s32k1xx/s32k1xx_lpi2c.c: arch/arm/src/sama5/hardware/sam_sdmmc.h: arch/arm/src/sama5/sam_gmac.c: arch/arm/src/samd5e5/sam_wdt.c: arch/avr/src/avr32/up_exceptions.S: arch/avr/src/avr32/up_fullcontextrestore.S: arch/renesas/src/rx65n/rx65n_dtc.c: arch/renesas/src/rx65n/rx65n_usbhost.c: arch/risc-v/src/esp32c3/esp32c3_tickless.c: boards/arm/stm32h7/stm32h747i-disco/include/board.h: include/nuttx/lcd/ili9225.h: libs/libc/stdio/lib_fgetpos.c: libs/libc/stdio/lib_fseek.c: libs/libc/stdio/lib_fsetpos.c: * Fix typos.	2021-07-25 18:36:53 -07:00
hartmannathan	c475a71d1c	Update arch/arm/src/stm32/Kconfig Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>	2021-07-25 14:16:22 -03:00
hartmannathan	bb5f302361	Update arch/arm/src/stm32l5/stm32l5_serial.c Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>	2021-07-25 14:16:22 -03:00
Nathan Hartman	f617c27a8c	arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos. arch/arm/src/stm32/stm32_foc.c, arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h, arch/arm/src/stm32h7/stm32_allocateheap.c, arch/arm/src/stm32h7/stm32_fmc.c, arch/arm/src/stm32h7/stm32_pmstandby.c, arch/arm/src/stm32h7/stm32_spi.h, arch/arm/src/stm32h7/stm32_spi_slave.c, arch/arm/src/stm32h7/stm32_wwdg.c, arch/arm/src/stm32l4/stm32l4_adc.h, arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h, arch/arm/src/stm32l5/stm32l5_gpio.c, arch/arm/src/stm32l5/stm32l5_gpio.h, arch/arm/src/stm32l5/stm32l5_irq.c, arch/arm/src/stm32l5/stm32l5_rcc.c, arch/arm/src/stm32l5/stm32l5_rcc.h, arch/arm/src/stm32l5/stm32l5_serial.c, and arch/arm/src/stm32l5/stm32l5_spi.c: * Fix typos in comments. No functional changes.	2021-07-25 14:16:22 -03:00
Nathan Hartman	3346ba304b	arch: arm: stm32, stm32h7, stm32l5: Fix typos in KConfig help texts arch/arm/src/stm32/Kconfig: * In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY: Fix typos in help text. arch/arm/src/stm32h7/Kconfig: * In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY, STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY, and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text. arch/arm/src/stm32l5/Kconfig: * In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix typos in help text.	2021-07-25 14:16:22 -03:00
Nathan Hartman	d178ff8a02	arch: arm: stm: Fix STM32_EXTI2_OFFSET arch/arm/src/stm32/hardware/stm32_exti.h: * Change STM32_EXTI2_OFFSET (offset to EXTI2 registers) from 0x18 to 0x20. This symbol is defined when CONFIG_STM32_STM32F30XX or CONFIG_STM32_STM32F33XX. According to the current reference manuals for STM32F334xx (RM0364 rev 4) and STM32F302xx (RM0365 rev 8), EXTI_IMR1 is at offset 0x00 and EXTI_IMR2 is at offset 0x20, i.e., 0x20 apart. The same offset applies to the rest of the registers: EMR1/EMR2, RTSR1/RTSR2, etc.	2021-07-24 16:53:14 +02:00
Michal Lenc	4985f47155	arch/arm/src/stm32/stm32_qencoder.c: print uint32_t by using standard format PRIx32 Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-07-24 04:22:11 -07:00
jordi	b87333bae8	Kconfig: remove empty help sections To avoid the setconfig warning: "has 'help' but empty help text"	2021-07-23 02:32:19 -07:00
jordi	1e44270558	Kconfig: add quotes in default string value To avoid the setconfig warning: "style: quotes recommended around default value for string symbol"	2021-07-23 02:32:19 -07:00
jordi	f3af6edf93	Kconfig: add quotes in source to clean warnings from setconfig To avoid the setconfig warning "style: quotes recommended around xxx in source xxx"	2021-07-23 02:32:19 -07:00
Masayuki Ishikawa	6d65e9f38e	arch: sim: Add NuttX symbols to make SMP work correctly Summary: - I noticed that sim:smp does not work correctly on macOS due to the recent changes - Actually, it can not receive the IPI host signal, so if a new task is scheduled on CPU1/2/3, it hangs. - Finally, I found that sim_cpu_start() calls pthread_attr_init() which locates not on the host OS but on the NuttX - This commit fixes this issue by adding the symbol names to nuttx-names.in Impact: - sim in SMP mode - NOTE: stack usage for CPU1/2/3 IDLE is still incorrect on macOS Testing: - Tested with ostest on Ubuntu 18.04 (x86_64) and macOS 11.4 (x86_64) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-07-22 09:03:30 -07:00
Masayuki Ishikawa	4f1e63f939	Revert "arch: sim: Workaround to make the IPI work on macOS" This reverts commit `b68fc9eb1d`.	2021-07-22 09:03:30 -07:00
Xiang Xiao	2ef6428aa8	arch/sim: Don't need pass CONFIG_SCHED_INSTRUMENTATION to host side since this macro isn't check from host side after: commit `cee43ce280` Author: Xiang Xiao <xiaoxiang@xiaomi.com> Date: Fri Jul 16 02:23:59 2021 +0800 arch/sim: Initialize the idle thread stack info correctly and change the default value of IDLETHREAD_STACKSIZE to 65536 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-22 07:59:58 -07:00
ligd	4919d9b7df	arm: add up_secure_irq support Change-Id: Ibc9402dcef4045ca122da400940d57de6b508308 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-22 10:50:53 -03:00
ligd	29d6a6dcd3	arch: add depends to trigger_irq Change-Id: I334f625f8f1a6ebaa4fa5ea292de142a93120f51 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-22 10:50:53 -03:00
Masayuki Ishikawa	b68fc9eb1d	arch: sim: Workaround to make the IPI work on macOS Summary: - I noticed that sim:smp does not work correctly on macOS due to the recent changes - Actually, it can not receive the IPI host signal, so if a new task is scheduled on CPU1/2/3, it hangs. - Finally, I found the issue depends on pthread stack settings and perhaps it might affect the host signal handling. - This commit fixes this issue by just reverting the pthread stack setting only for macOS. Impact: - sim:smp on macOS - Stack usage for CPU1/2/3 IDLE will be incorrect Testing: - Tested with ostest on macOS 11.4 (x86_64) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-07-22 09:47:19 +02:00
Abdelatif Guettouche	e85b119363	arch/: Clean what was made during `context` in distclean. Cleaning during `clean_context` had the issue of remaking everything when `menuconfig` was issued. That's because `menuconfig` has a `clean_context` on its way. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-07-21 16:52:36 -03:00
Abdelatif Guettouche	315ba8c77f	esp32_allocateheap.c: Remove the amount reserved to himem from the heap. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-07-21 08:58:18 -07:00
Alan C. Assis	011c938116	Remove xtensa_backtrace.S reference from esp32s2 as well	2021-07-20 19:30:09 -07:00
Alan C. Assis	d2eeeee262	Fix xtensa_btdump() to look at the exception frame Remove xtensa_backtrace_start() since it is not used anymore	2021-07-20 19:30:09 -07:00
David Sidrane	19fddc451c	Kintis:LPUART add RX DMA	2021-07-20 19:28:51 -07:00
David Sidrane	34eb918665	kinetis:LPUART Add IOCTL for invert	2021-07-20 19:28:51 -07:00
Nathan Hartman	609ee6b54b	Fix typos in comments and identifiers	2021-07-19 22:55:30 -03:00
ligd	aac0db368c	ARM: fix CPSR corruption after exception handling It seems to be caused by the corrupted or wrong CPSR restored on return from exception. NuttX restores the context using code like this: msr spsr, r1 GCC translates this to: msr spsr_fc, r1 As a result, not all SPSR fields are updated on exception return. This should be: msr spsr_fsxc, r1 This bug has been fixed by Heesub Shin in: `343243c7c0` Change-Id: Ibc64db7bceecd0fb6ef39284fb5bc467f5603e2e	2021-07-19 08:41:06 -03:00
Gustavo Henrique Nihei	c05feda208	risc-v/esp32c3: Implement MTDIOC_ERASESTATE for SPI Flash driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei	50ea22314e	arm/lpc43xx: Implement MTDIOC_ERASESTATE for SPIFI Flash driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-07-17 09:00:41 -07:00
Gustavo Henrique Nihei	df2e890cfc	xtensa/esp32: Implement MTDIOC_ERASESTATE for SPI Flash driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-07-17 09:00:41 -07:00
Xiang Xiao	4444c13c14	arch/sim: The second CPU shouldn't call up_irqinitialize since the signal handler the process concept Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-17 07:48:27 +09:00
Xiang Xiao	98b5724b59	arch: Fix rtcb can't found error use the same condition check in declaration and reference Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: I7b05316e914708fceeddac394d784ee3720a3c1b	2021-07-16 12:48:09 -03:00
Xiang Xiao	3204c75c1d	arch/sim: Remove the unused sim_host_timer_handler Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Icacbe74308580b7fc2449cdf9e41f85fce43d5a4	2021-07-16 17:41:00 +09:00
ChenWen	2abb75fee7	risc-v/esp32c3: Fix some ESP32-C3 Wi-Fi driver issues	2021-07-15 23:20:29 -07:00
Roberto Bucher	fc810e3db4	Restored previous files	2021-07-15 23:19:59 -07:00
Xiang Xiao	cee43ce280	arch/sim: Initialize the idle thread stack info correctly and change the default value of IDLETHREAD_STACKSIZE to 65536 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Ia54efbbca4b69706150bc4178844b316688a104e	2021-07-16 08:37:53 +09:00
David Sidrane	da01a39e39	Revert "Kinetis:Serial No DMA Poll needed" This reverts commit `e659ae83b0`. It turns out the DMA polling is needed. The IDLE INT will not happen on repetitive signals.	2021-07-15 12:28:04 -07:00
Daniel P. Carvalho	3ca46ea8e2	Change DAC driver to support STM32G4.	2021-07-15 14:33:15 -03:00
Fotis Panagiotopoulos	7f361daf60	lpc17_40: style fix in WDT definitions.	2021-07-13 08:32:42 -07:00
Michal Lenc	3d26c3efb6	fix nxstyle errors and warnings Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-07-13 09:55:29 -03:00
Michal Lenc	b2a9f853e8	arch/arm/src/imxrt: added support for Tickless OS Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-07-13 09:55:29 -03:00
Virus.V	063e1d6b74	risc-v/bl602: update wifi firmware and some fixup. 1. Added check for repeated connection wifi operations. 2. Invoke the carrier on/off operation in the wrong place. 3. The RTC initialization time is incorrect. 4. Reserve 32K I-Cache space in the linker script. 5. Increase the size of the wifi firmware receiving buffer. Signed-off-by: Virus.V <virusv@live.com>	2021-07-13 05:12:12 -07:00
Sara Souza	48f2b10ee3	risc-v/esp32-c3: Use systimer 0 to RTOS TICK	2021-07-12 21:03:27 -07:00
Sara Souza	c7bf5c7a1d	xtensa/esp32: Make UART TX DMA depends on EXPERIMENTAL and adds caveats regarding its use	2021-07-12 21:03:06 -07:00
Sara Souza	2abeba041d	xtensa/esp32: Fixes termios issue.	2021-07-12 21:02:26 -07:00
Dong Heng	f5eaf82c93	risc-v/esp32c3: Use onexit to free thread private semaphore	2021-07-12 09:38:21 -03:00
Jiuzhu Dong	9b1f554429	sched: Dynamically extend the pid hash table Change-Id: I3a719bc575cd408cd530a39efa203f507b44fa9c Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-07-11 19:42:30 -07:00
Xiang Xiao	5fe51b923a	mm: Simplify the semaphore handling 1.Move all special process to mm_takesemaphore 2.Remove the support of recurive lock 3.Remove mm_trysemaphore function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Ie216a6294ab67c5d427f31b089beb15c532f08fe	2021-07-10 16:10:32 -03:00
ligd	f5279f8583	sim: fix loop add delaylist when mm_free in IDLE thread Change-Id: I1827c663275f47c9dc30d63e17e3d016b0000166 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-10 16:10:32 -03:00
Fotis Panagiotopoulos	61cb524fa2	lpc17_40: Fixed progmem driver.	2021-07-09 21:49:16 -07:00
Jerry_tang	1e3a985155	AmebaZ2: Add soc src code Add soc src code for rtl8720c Signed-off-by: Jerry_tang <jerry_tang@realsil.com.cn>	2021-07-09 14:29:06 -03:00
guowei15	95b5dc523e	arm/setjmp.h:add c++ support N/A Change-Id: I619cc15570adeff10f3a9b69bf9a3cff83e625c1 Signed-off-by: guowei15 <guowei15@xiaomi.com>	2021-07-09 14:06:10 -03:00
David Sidrane	282ab797bf	stm32h7:Ethernet Add some delays so that ifup() does not hog the CPU.	2021-07-08 21:14:29 -05:00
David Sidrane	70c9cd1508	stm32h7:ethernet add timeout on MAC reset	2021-07-08 21:14:29 -05:00
David Sidrane	bf4e97177a	stm32h7:Ethernet fix formating	2021-07-08 21:14:29 -05:00
Xiang Xiao	e97ffb1f79	arch/armv7-a: Remove the special SMP SGI process Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: Iaf7fe77a3ab7cbf145d907dafb0b7ca54cc4a012	2021-07-09 07:53:05 +09:00
Daniel P. Carvalho	2692b61a72	Fix newline at end of file.	2021-07-07 21:34:58 -03:00
Daniel P. Carvalho	ea701a84f2	Fix comments.	2021-07-07 21:34:58 -03:00
Daniel P. Carvalho	2a21c45e0a	Add STM32G43XX Analog Comparator driver.	2021-07-07 21:34:58 -03:00
Xiang Xiao	76cdd5c329	mm: Remove mm_heap_impl_s struct it's more simple to make mm_heap_s opaque outside of mm Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2	2021-07-07 04:25:15 -07:00
cgeng	d656417917	Fix compilation error when CONFIG_DEBUG_PWM_INFO on stm32h7	2021-07-07 03:46:31 -05:00
Alexander Lunev	8fd64854f5	stm32,stm32f7,stm32h7: supported ETH MAC promiscuous mode	2021-07-06 19:11:56 -03:00
Fotis Panagiotopoulos	9976635390	lpc17_40: fixed compiler warnings.	2021-07-06 06:17:59 -05:00
Sara Souza	a5bf47b93e	xtensa/esp32: Fixes issue with UART 2	2021-07-05 23:20:26 -05:00
Sara Souza	d67852da4b	xtensa/esp32: Change default pins of UART2	2021-07-05 23:20:26 -05:00
Dong Heng	475becac37	risc-v/esp32c3: Add board_ioctl and board_uniqueid	2021-07-05 23:12:17 -05:00
Fotis Panagiotopoulos	2f0b4eb363	lpc17xx: Added WDT driver.	2021-07-05 11:25:51 -05:00
Xiang Xiao	75bfa4584c	mm: Add kmm_malloc_size and mm_malloc_size make malloc_size implementation align with malloc Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Change-Id: I8d7781925f06e58a880437a16569dccbfd2ea035	2021-07-05 14:23:24 +09:00
Xiang Xiao	ddaa3e42b9	mm: Move the real implementation of mm_sbrk to sbrk and remove mm_sbrk and kmm_sbrk since it's wrong to expose sbrk to other heaps except the default userspace heap. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-05 08:02:08 +09:00
Xiang Xiao	b3f568c216	boards/sim: Add asan config to test the custom heap Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:53:44 -03:00
Xiang Xiao	4589c369be	arch/sim: Implement mm_mallinfo for the custom heap Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:53:44 -03:00
Xiang Xiao	8ebf9c92cf	arch/sim: Implement malloc_size for the custom heap Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:53:44 -03:00
Xiang Xiao	f240b2e631	arch/sim: Remove host_malloc and host_calloc use host_realloc instead Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:53:44 -03:00
Xiang Xiao	97216c220b	mm: Support malloc_size function and rename malloc_usable_size to malloc_size Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:53:44 -03:00
Xiang Xiao	0941bad877	note: Move up_schednote.c to drivers/note folder since it is general enough to work on other target Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 18:52:32 -03:00
Nathan Hartman	ce20211357	Fix various typos in comments and documentation Fix typos in these files: * Documentation/components/drivers/character/foc.rst * Documentation/guides/cpp_cmake.rst * Kconfig * arch/arm/src/imxrt/imxrt_lpspi.c * arch/arm/src/kinetis/kinetis_spi.c * arch/arm/src/kl/kl_spi.c * arch/arm/src/lpc31xx/lpc31_spi.c * arch/arm/src/nrf52/nrf52_radio.h * arch/arm/src/s32k1xx/s32k1xx_lpspi.c * arch/arm/src/stm32/Kconfig * arch/arm/src/stm32/stm32_adc.c * arch/arm/src/stm32/stm32_foc.c * arch/arm/src/stm32/stm32_foc.h * arch/arm/src/stm32/stm32_pwm.c * arch/arm/src/stm32/stm32_spi.c * arch/arm/src/stm32f0l0g0/stm32_spi.c * arch/arm/src/stm32f7/Kconfig * arch/arm/src/stm32f7/stm32_spi.c * arch/arm/src/stm32h7/Kconfig * arch/arm/src/stm32h7/stm32_allocateheap.c * arch/arm/src/stm32h7/stm32_fmc.c * arch/arm/src/stm32h7/stm32_fmc.h * arch/arm/src/stm32h7/stm32_pwm.c * arch/arm/src/stm32h7/stm32_qspi.c * arch/arm/src/stm32h7/stm32_spi.c * arch/arm/src/stm32l4/stm32l4_pwm.c * arch/arm/src/stm32l4/stm32l4_spi.c * arch/arm/src/stm32l5/Kconfig * arch/arm/src/stm32l5/stm32l5_spi.c * arch/renesas/src/rx65n/rx65n_dtc.c * arch/renesas/src/rx65n/rx65n_usbdev.c * arch/risc-v/src/rv32m1/rv32m1_serial.c * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c * boards/arm/stm32h7/nucleo-h743zi2/README.txt * boards/risc-v/rv32m1/rv32m1-vega/README.txt * boards/sim/sim/sim/scripts/Make.defs * drivers/1wire/1wire.c * drivers/1wire/1wire_internal.h * drivers/lcd/Kconfig * drivers/syslog/ramlog.c * fs/fat/Kconfig * libs/libc/debug/Kconfig * libs/libc/machine/Kconfig * libs/libc/stdio/lib_libvsprintf.c * libs/libc/stdlib/lib_div.c * libs/libc/stdlib/lib_ldiv.c * libs/libc/stdlib/lib_lldiv.c * libs/libdsp/lib_observer.c	2021-07-04 11:23:26 -05:00
SPRESENSE	b3389cf751	arch: cxd56x: Add support for power management debug output Add support for power management debug output.	2021-07-04 00:36:07 -05:00
SPRESENSE	7af6b394de	arch: cxd56x: Add Kconfig for power management debug output Add configurations for power management debug output to Kconfig.	2021-07-04 00:36:07 -05:00
SPRESENSE	4738f69569	arch: cxd56x: pmic: Fix a compile error Replace undefined logerr to _err function.	2021-07-04 00:36:07 -05:00
SPRESENSE	5c26d68f31	arch: cxd56x: Add a configuration for PMIC interrupts Add a configuration for PMIC interrupts to Kconfig.	2021-07-04 00:36:07 -05:00
SPRESENSE	618661df93	arch: cxd56xx: Fix compile error when CONFIG_LIBM is disabled It is no longer necessary to define CONFIG_ARCH_MATH_H when we would like to link libm.a other than nuttx math library. So, this commit removes the error condition.	2021-07-04 00:36:07 -05:00
SPRESENSE	d29db87bdc	arch: cxd56xx: Add eMMC configuration for vendor-specific commands The eMMC driver for cxd56xx has been implemented a vendor-specific command for Toshiba eMMC device, and so add a new configuration to enable the code.	2021-07-04 00:36:07 -05:00
SPRESENSE	cd06fc9761	arch: cxd56x: sdhci: Minor fix configuration name Modify the referenced CONFIG to CONFIG_DEBUG_MEMCARD_INFO.	2021-07-04 00:36:07 -05:00
SPRESENSE	6a2733dd05	arch: cxd56x: emmc: Minor fix undefined configuration name Replace obsolete CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_FS_INFO.	2021-07-04 00:36:07 -05:00
SPRESENSE	fa12fe9df1	arch: cxd56x: scu: Fix some printf format warnings Fix some printf format warnings by -Wformat.	2021-07-04 00:36:07 -05:00
SPRESENSE	845da344fd	arch: cxd56xx: Fix compile warning Fix warning by -Wimplicit-function-declaration	2021-07-04 00:36:07 -05:00
SPRESENSE	75b6a260e0	arch: cxd56xx: Rename to nxsem_set_protocol nxsem_setprotocol function name was changed to nxsem_set_protocol. Replace and fix hostif compile error.	2021-07-04 00:36:07 -05:00
SPRESENSE	4364a291f0	arch: cxd56xx: Use arm_arch.h instead of up_arch.h Use arm_arch.h instead of up_arch.h and fix hostif compile error.	2021-07-04 00:36:07 -05:00
SPRESENSE	cb6ad9dfbd	arch: cxd56xx: Fix getting stuck by nested spinlock in serial Fix an issue the serial console gets stuck in SMP caused by nested spin_lock_irqsave.	2021-07-04 00:36:07 -05:00
Xiang Xiao	a18b807fa9	arch/sim: Fix bt and audio simulation stop work in SMP mode by removing the SMP up_idle and sim_timer_handler Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-04 10:16:12 +09:00
Xiang Xiao	b1f711f790	mm: Move procfs_register_meminfo into common place to avoid the code duplication and ensure the consistent behaviour Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-07-03 09:39:32 -07:00
Masanari Iida	707404d415	rx65n: Add missing parameters in printf Printf format string requires 2 parameters, but 0 parameter was given. Add these missing parameters. Signed-off-by: Masanari Iida <standby24x7@gmail.com>	2021-07-03 09:25:57 -05:00
Dong Heng	4f2df0311d	risc-v/esp32c3: Fix some BLE driver issues 1. remove SMP functions because ESP32-C3 is singal core 2. disable phy_printf in ble adapter when enable Wi-Fi 3. fix BLE character device macro	2021-07-03 07:28:30 -05:00
Masayuki Ishikawa	6370c820ea	arch: rp2040: Introduce setintstack macro for SMP Summary: - This commit introduces setintstack macro to rp2040 which is used for SMP with interrupt stack Impact: - SMP with interrupt stack Testing: - Tested with raspberrypi-pico:smp - NOTE: seed to set CONFIG_ARCH_INTERRUPTSTACK=2048 Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-07-03 04:13:13 -05:00
Masayuki Ishikawa	9f206f2bb6	arch: armv6-m: Introduce setintstack macro Summary: - This commit introduces setintstack macro which can be overridden for SMP with interrupt stack Impact: - SMP only Testing: - Tested with raspberrypi-pico:smp - NOTE: more commits will be added later Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-07-03 04:13:13 -05:00
Virus.V	5f67d65e9e	risc-v/bl602: add efuse driver Signed-off-by: Virus.V <virusv@live.com>	2021-07-02 13:17:39 -05:00
ligd	f479ca9096	sim/smp: fix smp can't start, caused by signal too busy Change-Id: Ia9cad04759a869f9bed871fa0acd002115eefb0a Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-02 23:19:15 +09:00
ligd	2ab1dcf763	sim: add setitimer to nuttx-names.in Change-Id: Id6d91d81b3d67cbe9215eb94f4ef394d61156fe8	2021-07-02 05:02:36 -05:00
ligd	a7a8c20083	sim: fix host_sleep unit error Change-Id: Iaddd6381eb9870b709147d33b36482ae2e37c04d Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-02 05:02:36 -05:00
ligd	36c1bba88c	sim/up_oneshot.c: take host time as current Change-Id: I34625f3d3f9557a103017124388dba6104aba7cc Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-02 05:02:36 -05:00
ligd	92cd7628e0	sim: remove CONFIG_SIM_WALLTIME fast timing maybe harmful for IOs Change-Id: Ic4ff5ec0aa99d2d229a07c4d1a9a4dae738d3cd9 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-02 05:02:36 -05:00
ligd	aa43a0215d	mm: fix memory corruption when loop create/exit thread in SMP mode Root casue: when do thread exit, need add free stack operation to mm_delaylist, but in SMP mode, CPU0 thread1 exit, at this time, CPU1 call malloc and free mm_delaylist. Fix: Divide mm_delaylist for per CPU in SMP mode. Change-Id: Ibf7d04614ea2f99fb5b506356b7346a0d94f0590 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-02 04:55:46 -05:00
ligd	50eee2f081	arm: fix enable interrupt too earlier caused system crash reason: msr cpsr, r2 /* Set the CPSR */ // interrupt hanppend, context switch pop {r0-r2, pc} resolve: use SPSR instead, and recover with ldmia ^ Change-Id: Id7cee6452997ec19919eeecf6e7616164b3a0ab3 Signed-off-by: ligd <liguiding1@xiaomi.com> (cherry picked from commit 6fa6c1676932d7babb7ff22ef556a17bb18f1c0d) Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-07-01 22:20:36 -05:00
Fotis Panagiotopoulos	de213401a7	lpc17_40_progmem: fixed compilation issues.	2021-07-01 09:11:12 -05:00
Masanari Iida	839414987c	efm32: Fix missing closing bracket This patch fixes missing closing bracket and semicolon. Signed-off-by: Masanari Iida <standby24x7@gmail.com>	2021-07-01 06:37:17 -07:00
Sara Souza	b45ccad6a0	xtensa/esp32: Adds support for SERIAL_TXDMA.	2021-07-01 01:50:13 -05:00
David Sidrane	e659ae83b0	Kinetis:Serial No DMA Poll needed	2021-07-01 01:44:46 -05:00
David Sidrane	78584b4569	kinetis:Serial use eDMA kinetis:serial mark priv->rxdma after use	2021-07-01 01:44:46 -05:00
David Sidrane	e5a1b2e797	kinetis:SPI use eDMA Kinetis:SPI only allocate DMA once	2021-07-01 01:44:46 -05:00
David Sidrane	78bf264af0	kinetis:Replace DMA Kinetis:DMAMUX use hex in mask	2021-07-01 01:44:46 -05:00
David Sidrane	3439c40044	stm32h7:SDMMC fix reset of do_gpio For the case when the watchdog is triggering a timeout we did not correctly reset the d0 GPIO. Without this fix, the SD card can become inaccessible.	2021-07-01 01:37:58 -05:00
Julian Oes	6d6ca8f0b6	stm32:sdio: fix wrong ifdefs This was wrong but presumably did not matter.	2021-07-01 01:37:58 -05:00
Julian Oes	2a86335055	stm32:sdio: fix reset of GPIO_SDIO_D0 For the case when the watchdog is triggering a timeout we did not correctly reset the GPIO_SDIO_D0. Without this fix, the SD card can become inaccessible.	2021-07-01 01:37:58 -05:00
Julian Oes	665f847760	stm32f7: fix reset of d0_gpio For the case when the watchdog is triggering a timeout we did not correctly reset the d0 GPIO. Without this fix, the SD card can become inaccessible.	2021-07-01 01:37:58 -05:00
Julian Oes	154795a247	stm32f7: Removed bit that is reserved for f7	2021-07-01 01:37:58 -05:00
Julian Oes	87fd8903a0	stm32f7: whitespace fix	2021-07-01 01:37:58 -05:00
Julian Oes	804445fc15	stm32f7: unify identical sdmmc.h header files It turns out there is no difference in these two files as well as the reference manual for the registers between the two parts, so it probably makes sense to unify them	2021-07-01 01:37:58 -05:00
chenwen	31a6da2343	risc-v/esp32c3: Notifies networking layer whether the carrier is available	2021-06-30 23:09:34 -05:00
McKay Ransom	863834057b	Renesas/RX: add RX setjmp, ARCH_RENESAS_RX, and RX65N ioctl	2021-06-30 23:01:57 -05:00
Sara Souza	87fabb2bc7	xtensa/esp32: Support to select different clock source for RTC controller and close TODOs.	2021-06-30 21:27:27 -05:00
Virus.V	84100128b2	risc-v/bl602: update wifi firmware version Signed-off-by: Virus.V <virusv@live.com>	2021-06-30 01:08:10 -05:00
xiewenxiang	5fd3eca9c9	riscv/esp32c3: Support BLE sleep mode	2021-06-28 23:14:30 -05:00
xiewenxiang	145d917587	riscv/esp32c3: Add Wi-Fi and BLE coexist	2021-06-28 23:14:30 -05:00
xiewenxiang	8b96edc3a5	riscv/esp32c3: Add esp32c3 BLE driver	2021-06-28 23:14:30 -05:00
Michal Lenc	b36171026e	arch/arm/src/imxrt/imxrt_flexpwm.c: fix mistake in submodules address offset Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-06-28 09:03:06 -05:00
Virus.V	8452c571ec	risc-v/bl602: BLE firmware adapts to the new framework Signed-off-by: Virus.V <virusv@live.com>	2021-06-28 07:03:04 -05:00
Virus.V	cd50650583	risc-v/bl602: Support AP and STA as independent network interface device Signed-off-by: Virus.V <virusv@live.com>	2021-06-28 07:03:04 -05:00
Michal Lenc	addfe182ae	arch/arm/src/imxrt: added support for FlexPWM driver Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-06-26 09:58:52 -05:00

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18571 Commits