Commit Graph

19289 Commits

Author SHA1 Message Date
Xiang Xiao
3c82094156 arch/or1k: Remove FAR from chip folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 18:42:38 +03:00
Xiang Xiao
0bd9a66305 arch/x86_64: Remove FAR from chip folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 18:42:38 +03:00
Xiang Xiao
af00e016e9 arch/sim: Remove FAR from chip and board folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 18:42:38 +03:00
Xiang Xiao
e923875c1b arch/ceva: Remove FAR from chip folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 18:42:38 +03:00
Xiang Xiao
6bc61b5752 arch/xtensa: Remove FAR from chip and board folder
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-17 18:42:38 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$)
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-17 00:58:34 +08:00
chao.an
aed21ba0bc arch/armv[7|8]m: enhance the clang support
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-17 00:58:34 +08:00
okayserh
3a015d56b0 Fixed a compile error, presumably caused by C&P error. 2022-04-16 19:21:10 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig.
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver.
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif.
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-15 19:41:31 +08:00
Petro Karashchenko
09b3fb25ab drivers: remove unimplemented open/close/ioctl interfaces
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-15 16:56:25 +08:00
Richard Tucker
1b13d1b440 arch/arm/src/sam34/Kconfig: fix typo in device name 2022-04-15 02:22:01 +08:00
Richard Tucker
de66e18d6f arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup 2022-04-15 02:22:01 +08:00
Richard Tucker
929556d750 arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips 2022-04-15 02:22:01 +08:00
Richard Tucker
be0bcac91b arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required 2022-04-15 02:22:01 +08:00
Richard Tucker
bc7f4b2375 arch/arm/src/sam34/sam_hsmci.c: delay required after sending command 2022-04-15 02:22:01 +08:00
chao.an
dc961baaea arm/armv7-[a|r]: move fpu save/restore to assembly handler
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-14 22:33:10 +08:00
Alan C. Assis
c232be541c Add SPIRAM to ESP32-S2 2022-04-14 22:10:23 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
Xiang Xiao
a94b7b9cca arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-14 16:35:52 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-14 16:48:19 +08:00
chao.an
0c79ad9d8d arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_*
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
2022-04-14 16:43:34 +08:00
Abdelatif Guettouche
a5c64adbe4 arch/Kconfig: Move the DUMP_ON_EXIT option out of the Bring-up group.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit.
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address
MTIMECMP0 was incorrect
2022-04-13 21:56:21 +08:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
2022-04-13 12:00:40 +02:00
chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-12 23:35:06 +03:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
2022-04-12 21:33:19 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-12 12:14:40 +03:00
Lingao Meng
a56199c7dd sim: bt: Add specific bluetooth HCI number id
Add option for attached the local bluetooth device use
specific bluetooth HCI number id.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
2022-04-12 15:15:25 +08:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver
Add critical section to scu one-shot sequencer.
2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning
Add necessary include header named debug.h for using ferr and
finfo.
2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version
Update loader and gnssfw to version 2.2.20585
2022-04-12 07:55:00 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
2022-04-12 01:59:35 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-11 10:59:18 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-10 08:27:10 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-10 00:52:04 +08:00
Xiang Xiao
c235c0fa43 boards/lx_cpu: Enable up_perf API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-08 21:02:13 -03:00
Xiang Xiao
1f7b49d700 boards/nucleo-h743zi2: Enable up_perf API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-08 21:02:13 -03:00
Huang Qi
c6942b68d5 arch/risc-v: Add handler for misaligned load/store
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-08 23:27:07 +08:00
chao.an
8d66dbc068 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-08 14:28:41 +09:00
Huang Qi
b6cf1ac662 arch/riscv: Minor style change and text correction
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-08 01:07:06 +08:00
Huang Qi
4ebc581c73 esp32c3: Simplify irq dispatch logic
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-07 18:16:35 +02:00
Ville Juven
d38b4965f8 MPFS: Prepare support for S-mode
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
2022-04-07 21:55:36 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-07 11:25:12 +03:00
Jiuzhu Dong
d87cf8d4ca fs/poll: change format for type pollevent_t
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-04-07 12:14:06 +08:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-06 22:48:46 +08:00
yinshengkai
db012687f9 arch/sim: support simulator keyboard devices 2022-04-06 15:26:57 +03:00
Alan C. Assis
1090e1a8ea xtensa/esp32: Add support to TWAI/CANBus controller 2022-04-06 15:09:46 +03:00
zhuyanlin
6a761ff087 arch:tcbinfo: update tcbinfo as xcpcontext update
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-04-05 13:33:00 +02:00
Ville Juven
6c22e2894c RISC-V: Fix usage of static_assert in riscv_percpu.c
There is no alias for struct riscv_percu_s
2022-04-04 22:44:25 +08:00
Ville Juven
7db356e720 RISC-V: Fix file name of riscv_dispatch_syscall 2022-04-04 22:44:18 +08:00
Petro Karashchenko
d08fbca679 nuttx: unify FAR attribute usage across the code
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-04 21:32:58 +08:00
Abdelatif Guettouche
f527abc324 arch/xtensa: Build the xtensa_tcbinfo.c file for S2 and S3.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-04 21:25:47 +08:00
Xiang Xiao
bf48c6d4a8 arch/riscv: Rename SCRATCH_HARTID_OFFSET to RISCV_PERCPU_HARTID_OFFSET
and fix the typo error

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-04 08:22:08 +03:00
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-04 12:05:53 +08:00
Michael Jung
e3926ecb16 stm32u5: stm32_stdclockconfig fixes
Fix stm32_stdclockconfig for stm32u585xx to the extend that the
B-U585I-IOT02A board's clock tree can be configured.  This board uses
the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.
2022-04-03 23:20:03 +03:00
zhanghongyu
451c53daa4 usrsock: Move event field to usrsock_message_common_s
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2022-04-03 11:38:50 +09:00
wangbowen6
bcb2530b18 arm/chip: add backtrace support for all chips that support thumb instruction set.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-04-03 00:22:57 +08:00
raiden00pl
b487101b87 stm32: add support for up_perf 2022-04-02 10:34:35 -03:00
Xiang Xiao
27c80f2586 arch/riscv: Rename g_scratch to g_percpu
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
e959775397 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
be2fee7d6e arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
since macro defined in this file is also used in the normal context

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
79aca28bd7 arch/riscv: Remove riscv_sbi.c since it doesn't exist
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
629d9969dd arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
follow other function naming(e.g. riscv_dispatch_irq)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Xiang Xiao
7a209e6ee8 arch/riscv: Align the macro definition in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-02 14:08:37 +03:00
Abdelatif Guettouche
11807abd4e arch/xtensa: Add xtensa_tcbinfo struct that contains helpful offsets.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-02 10:39:14 +08:00
Ville Juven
71ced1f1a9 RISC-V: Implement skeleton for a per CPU structure
It might be useful to store things in memory per CPU. The tricky part
is that all CPUs run the same code and see the same memory, so some
kind of centralized access is required.

For now, the structure contains the hart id.

Access to the structure elements is provided via sscratch, which is
unique for every hart!
2022-04-01 16:19:42 -03:00
Ville Juven
c15b6701ce RISC-V: Implement option to run NuttX in supervisor mode (S-mode)
- Add config "ARCH_USE_S_MODE" which controls whether the kernel
  runs in M-mode or S-mode
- Add more MSTATUS and most of the SSTATUS register definitions
- Add more MIP flags for interrupt delegation
- Add handling of interrupts from S-mode
- Add handling of FPU from S-mode
- Add new context handling functions that are not dependent on the trap
  handlers / ecall

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
      thus S-mode is not usable as is, yet.
2022-04-01 16:19:42 -03:00
Gustavo Henrique Nihei
c37474b5bd risc-v/esp32c3: Fix regression on IRQ handling for ECALL instruction
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-01 15:29:14 -03:00
Gustavo Henrique Nihei
35009c5d4d sim: Fix init of static C++ constructors when using glibc >= 2.34
glibc 2.34 changed the dynamic linker behavior during the startup
process, which makes the previous "__init_array_start" replacement trick
non-effective.
Now the dynamic linker parses the constructors/destructors information
from the DYNAMIC segment of the program.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-01 23:10:53 +08:00
chao.an
253562f11f arch/xtensa: add syscall note support in the flat build
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-01 21:04:51 +08:00
Jiuzhu Dong
0a111b7c96 fs/rpmsgfs: fix bug about using uninit variable "times"
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-04-01 21:02:08 +08:00
Petro Karashchenko
870ca12146 arch/risc-v: get wider visibility for arch instruction macros
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-04-01 10:31:24 +08:00
Ville Juven
e6d6734db2 ARCH_ADDRENV: Add guard against mis-configuration
When process a is switched to process b, the address environment is
swapped with a call to group_addrenv(). The stack upon entry will be
a's, and upon exit b's. This will fail, so a neutral stack is required,
either a kernel stack or an IRQ stack.

Infrastructure for an IRQ stack is already in place, so give a hint
that an interrupt stack should be provided if address environments
are enabled.
2022-04-01 02:02:10 +08:00
Petro Karashchenko
44ee76dcbd arch/risc-v: fix ARCH_RV32 offset for the stub lookup table calculation
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
36b0b95eb1 arch/risc-v: include csr.h indirectly through nuttx/irq.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Petro Karashchenko
5d856971db arch/risc-v: move REGLOAD/REGSTORE macro to riscv_internal.h
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-31 19:34:52 +08:00
Huang Qi
264e39e121 arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
f72ca3db5c arch/risc-v: Dont' disable/enable irq in riscv_doirq
Since these codes added to all chips but not fully tested,
so we should changd this behavior.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
32fe25278a arch/risc-v: Merge duplicated logic by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
a6c22b722f arch/risc-v: Remove deprecated logic from riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
692ffb60b4 arch/risc-v: Rename up_doirq to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 19:33:08 +08:00
Huang Qi
814c07c792 arch/risc-v: Store/Restore FPU register in exception_common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-31 11:49:36 +08:00
Huang Qi
379639a371 arch/risc-v/mpfs: Remove duplicated riscv_restorefpu
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 13:15:35 +03:00
Gustavo Henrique Nihei
e1f28c19c2 arch/arm: Make CXX exception and RTTI depend on Kconfig options
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
06d0a9f1ad xtensa|risc-v: Make CXX exception and RTTI depend on Kconfig options
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
c7311829e0 xtensa: Build OS-assisted atomic operations on ESP32-S2
ESP32-S2 lacks support for conditional load/store instructions.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
7926bce26b xtensa: Move XCHAL_SWINT_CALL definition into syscall header
This is required to avoid the interface header (syscall.h) depending on
the xtensa_swi.h header from the implementation

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Lee Lup Yuen
4456b13c19 riscv/bl602: Remove check for LCD driver
## Summary

`bl602_spi_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.

This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.

More details: https://github.com/apache/incubator-nuttx/pull/5898

## Impact

This change impacts LCD drivers that call `SPI_CMDDATA()`.

Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.

After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.

## Testing

We tested with LVGL and ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-30)
2022-03-29 23:09:42 -03:00
chao.an
a98a599cb9 arm/cortex-[a|r]: IRQ Switch return should with shadow SPSR
The SPSR is used to store the current value of the CPSR when an exception
is taken so that it can be restored after handling the exception.
Each exception handling mode can access its own SPSR.

User mode and System mode do not have an SPSR because they are not
exception handling modes.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-30 08:12:26 +09:00
Richard Tucker
6d8cd4ec92 arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/litesdcard
2022-03-30 02:35:27 +08:00
Richard Tucker
d557b87b25 arch/risc-v/litex: add cache_invalidate 2022-03-30 02:35:27 +08:00
Lee Lup Yuen
4f885fe6bf riscv/bl602: Implement SPI Cmd/Data
## Summary

To control the Data/Command Pin on ST7789 SPI Display, the SPI Driver flips the MISO Pin as though it was a GPIO.

To implement this on BL602, we reconfigure MISO from SPI Pin to GPIO Pin on the fly inside `bl602_spi_cmddata()`.

When the SPI Port is deselected (after the SPI operation), we revert MISO back from GPIO Pin to SPI Pin. We implement this inside `bl602_spi_select()`.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

## Impact

This change impacts 3 LCD drivers that call `SPI_CMDDATA()`: ST7735, ST7789, GC9A01.

Previously the BL602 SPI Driver would fail with "SPI cmddata not supported" when the above drivers are used.

After the change, the above drivers will set the LCD Data/Command Pin correctly.

## Testing

We tested this implementation of SPI Cmd/Data with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-   [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

We also tested LVGL with ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-29)
2022-03-30 02:01:29 +08:00
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Huang Qi
20c511fcf1 arch/risc-v: Rename up_fpuconfig to riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
ligd
ed8704d90e sim/rptun: rsc must set rpmsg_vdev.config_len
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 10:10:33 +08:00
zhuyanlin
d7391bf6bc xtensa: add xtensa arch oneshot ops
As xtensa timer is common in all xtensa chips,
Use oneshot ops, implement a common xtensa oneshot timer.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-28 22:55:00 +08:00
ligd
0f02791ae6 armv8-m: add wake_func arm_should_generate_nonsecure_busfault
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 22:52:28 +08:00
ligd
60fc933261 armv8-m: make the securefault handled by non-securefult
tee is secure cpu and ap is non-secure cpu.
The crash PC can get by IP (R12).

[ EMERG] [tee] arm_hardfault: Hard Fault escalation:
[ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault:
[ EMERG] [tee] arm_securefault:         IRQ: 3 regs: 0x2400ff00
[ EMERG] [tee] arm_securefault:         BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c
[ EMERG] [tee] arm_securefault:         CFSR: 00000000 HFSR: 40000000 DFSR: 00000000
[ EMERG] [tee] arm_securefault:         BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0
[ EMERG] [tee] arm_securefault: Secure Fault Reason:
[ EMERG] [tee] arm_securefault:         Attribution unit violation
[ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678
[ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault:
[ EMERG] [ap] arm_busfault:     IRQ: 5 regs: 0x3c475608
[ EMERG] [ap] arm_busfault:     BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004
[ EMERG] [ap] arm_busfault:     CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000
[ EMERG] [ap] arm_busfault: Bus Fault Reason:
[ EMERG] [ap] arm_busfault:     Instruction bus error
[ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main
[ EMERG] [ap] backtrace:
[ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168
[ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60
[ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324
[ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10
[ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c
[ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c
[ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c
[ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac
[ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4
[ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74
[ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8
[ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54
[ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48
[ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c
[ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34
[ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8
[ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98  R3: 00000000
[ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000  FP: 3c476aac
[ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c
[ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4  PC: 00000000
[ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004
[ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8
[ EMERG] [ap] arm_dump_stack: IRQ Stack:
[ EMERG] [ap] arm_dump_stack: sp:     3c41c900

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 22:52:28 +08:00
Ville Juven
43d5f60a74 MPFS: Fix issue with external interrupt detection
The bitmask overflow'd. Failing test is at mpfs_irq_dispatch / line 69
2022-03-28 22:40:11 +08:00
zhuyanlin
c0c0ffdf2f xtensa: add xtensa_spill_window declaration
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-28 12:33:07 +02:00
Huang Qi
ad1098d413 arch/armv7-a: Fix a typo in Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 12:42:43 +03:00
Xiang Xiao
3aaa7e8591 arch/sim: Remove "or 480" from Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-28 09:16:38 +03:00
Xiang Xiao
30e80f2394 arch/sim: Remove the unused SIM_TCNWAITERS from Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-28 09:16:38 +03:00
lishaoen
aa0c9fd788 nuttx: Add new config ARM_HAVE_MVE for MVE instruction
Signed-off-by: lishaoen <lishaoen@xiaomi.com>
2022-03-28 08:51:24 +03:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Huang Qi
35f9265483 arch/risc-v: Move fpu [re]store to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00
Lee Lup Yuen
c67272f9c8 riscv/bl602: Enable SPI Master in SPI Poll Send
## Summary

SPI Poll Send `bl602_spi_poll_send()` doesn't send any SPI Data because it doesn't enable SPI Master and it doesn't clear the SPI FIFO. Also it hangs because it loops forever waiting for the FIFO.

We fix this problem by moving the code that enables SPI Master and clears the FIFO, from SPI Poll Exchange `bl602_spi_poll_exchange()` to SPI Poll Send. (Note that SPI Poll Exchange calls SPI Poll Send)

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Impact

This problem affects all NuttX Drivers that call `SPI_SEND()` on BL602, including the ST7789 Display Driver.

Previously `SPI_SEND()` didn't send any SPI Data and never returns, because it loops forever waiting to receive data.

Now `SPI_SEND()` sends data and returns correctly.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

## Testing

We tested the modified SPI Poll Send with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-  [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#fix-spi-send)

We also tested LVGL with ST7789 on PineCone BL602:

-  [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for the modified SPI Poll Exchange, we tested with Semtech SX1262 SPI Transceiver on PineCone BL602:

-  [Testing SPI Poll Exchange](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-25)
2022-03-28 13:32:27 +08:00
Xiang Xiao
8c8c60f70a arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-27 23:01:47 +03:00
ligd
e87d262c7f arch/Toolchain.defs: add wildcard for EXTRA_LIBS
VELAPLATFO-1491

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-27 22:53:58 +03:00
Xiang Xiao
a2e079fdd2 arch/arm: Change arm_arch.h to arm_internal.h in arm_perf.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-27 22:31:43 +03:00
Anthony Merlino
baeb2e9af7 stm32h7: Addresses tickless PR review comments 2022-03-28 00:33:26 +08:00
Anthony Merlino
896435e7c9 Fixes formatting 2022-03-28 00:33:26 +08:00
Anthony Merlino
c3745c8441 Adjust up_timer_getmask to handle 16-bit timers correctly. 2022-03-28 00:33:26 +08:00
Anthony Merlino
30f6dbc613 Throw compile time error if tickless timer is set to TIM6/TIM7 2022-03-28 00:33:26 +08:00
Anthony Merlino
95199f4790 stm32h7 timer: Clean up some bit operations to make them more readable. 2022-03-28 00:33:26 +08:00
Anthony Merlino
e5c8bb9b34 stm32h7: Fix a bunch of tickless issues. 2022-03-28 00:33:26 +08:00
Anthony Merlino
2fad06008a stm32h7: Adds tickless support. 2022-03-28 00:33:26 +08:00
ligd
f623ac0f13 armv7-m/armv8-m: move up_pref* api to common place
Signed-off-by: ligd <liguiding1@xiaomi.com>
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-26 13:39:18 +02:00
Huang Qi
052c071867 arch/risc-v: Minor style change
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 16:52:13 +09:00
Huang Qi
494230a841 arch/risc-v: Improve performance of context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-26 07:19:09 +09:00
Petro Karashchenko
7afedda89e arch/risc-v: improve style consistency accross chip variants
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-25 10:26:15 -03:00
Abdelatif Guettouche
914e9588bb esp32/Make.defs: Organise common arch files and chip files
appropriately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-25 11:31:24 +08:00
Gustavo Henrique Nihei
c92c4af304 xtensa/esp32s2: Initialize instruction cache on startup
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-23 20:05:40 -03:00
Gustavo Henrique Nihei
bc071ec243 xtensa/esp32s2: Use functions defined in xtensa_counter for TimerISR
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-23 19:38:28 -03:00
Gustavo Henrique Nihei
04b80cc8d2 xtensa/esp32s2: Remove unused and not unsupported configs from Kconfig
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-23 19:38:28 -03:00
Ville Juven
44bec4cf8e RISC-V: Add missing code to dumpstate
Just add the kernel stack dumping for completeness
2022-03-24 00:15:28 +08:00
Ville Juven
77e90d9c87 RISC-V: Include support for kernel stack
Preparation for CONFIG_BUILD_KERNEL=y, which requires that a kernel
stack is allocated for each user process.
2022-03-24 00:15:28 +08:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 22:18:15 +08:00
Huang Qi
f09ea317c1 risc-v/qemu-rv: Restore FPU context after context switch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-23 19:30:04 +08:00
chao.an
7b73606300 arm/schedulesigaction: update the SP to signal context top
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-23 19:08:37 +09:00
chao.an
a770ff2017 arm/vfork: update the SP to stack top
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-23 19:08:37 +09:00
Xiang Xiao
9ae0dcd4a2 arch/arm: Remove the code copy register from xcpt to stack
since xcpt always point to the stack after the below change:
commit 7b9978883c
Author: chao.an <anchao@xiaomi.com>
Date:   Tue Mar 1 01:06:24 2022 +0800

    arch/arm: optimize context switch speed

    The current context save implementation saves registers of each task
    to xcp context, which is unnecessary because most of the arm registers are
    already saved in the task stack, this commit replace the xcp context with
    stack context to improve context switching performance and reduce the tcb
    space occupation of tcb instance.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-23 19:08:37 +09:00
Gustavo Henrique Nihei
024364ebbd xtensa/esp32s3: Add support for GPIO pin interrupts
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-23 07:23:51 +09:00
Gustavo Henrique Nihei
0e67dc8637 xtensa/esp32s3: Add support for GPIO read/write operations
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-23 07:23:51 +09:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-22 21:22:32 +08:00
Harri Luhtala
2ee12b2c5d arch/arm/src/stm32l4: peripheral voltage monitor support for vddio2
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
2022-03-22 21:08:29 +08:00
Petro Karashchenko
757d01d915 progmem: eliminate PROGMEM_ERASESTATE configuration option
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-22 10:01:41 -03:00
Abdelatif Guettouche
10f8f6c9e3 xtensa/esp32(s2)_user.c: For EXCCAUSE values, use macros defined in xtensa_corebits.h
instead of those defined in core.h as they are deprecated.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-22 10:20:27 +08:00
smartether
7fbadb5c16 fixed mpu9250 not work on i2c bus issue.
1,set rp2040 FIFO_MAX_SIZE to 16.ref: pico sdk ->
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
2022-03-21 12:07:03 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-19 17:41:33 +08:00
Huang Qi
00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common
And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 17:38:18 +08:00
Petro Karashchenko
20ac85860c config: finalize transition from USER_ENTRYPOINT to INIT_ENTRYPOINT
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-19 11:32:47 +08:00
Abdelatif Guettouche
aa84559566 xtensa_coproc.S: Replace spaces by tabs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-19 01:09:22 +02:00
Abdelatif Guettouche
ce8fae2842 xtensa_coproc.S: Adjust the save reserved for local variables when
restoring/saving coprocessor state.

These function don't use call8 or call12 and thus need to create just 16
bytes for the base save area, however they do use one variable so we
need a space for that.  The `entry` instruction works in unit of 8 bytes
so we add whole 8 bytes for one variable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-19 01:09:22 +02:00
Gustavo Henrique Nihei
9ae826e925 xtensa/esp32s3: Fix output handling for pins numbered from 32 to 48
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
f21a9f9578 xtensa/esp32s3: Enable UART pins to use IOMUX and bypass GPIO matrix
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
77944ceb42 xtensa/esp32s3: Clean up and improve GPIO driver interface
Also fix an inconsistenct regarding the ESP32S3_NGPIOS macro. Although
correctly defining the number of available GPIOs in ESP32-S3, it was
erroneously being used for verifying the pin range.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-19 01:08:27 +02:00
Gustavo Henrique Nihei
43b7d9b0da xtensa/esp32s3: Sync GPIO sigmap with IDF version
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-19 01:08:27 +02:00
Huang Qi
edef327655 arch/arm: Move ARCHCPUFLAGS to Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 02:24:00 +08:00
Petro Karashchenko
c1fb14ccaa boards/arm/samv7/same70-qmtech: add /dev/timer0 support
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-19 02:21:03 +08:00
Abdelatif Guettouche
2793e6f82d xtensa_releasepending.c: Remove commented out code.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-19 02:20:36 +08:00
Petro Karashchenko
6472a698b6 style/typo: fix few style and typo issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-18 17:05:10 +01:00
Janne Rosberg
d72a523c00 risc-v/mpfs: add support for ethernet 2022-03-18 17:22:27 +02:00
Janne Rosberg
07aeb12b30 risc-v/common: add call to riscv_netinitialize() 2022-03-18 17:22:27 +02:00
Eero Nurkkala
ec2352a4f9 risc-v/mpfs: usb: fix ep0 read done
USB EP0 reads data from the fifo but doesn't mark the read
done which adds significant delays. Fix this unnecessary
slowdown due to operation timeouts by finishing the read
properly.

Also add a missing function description to the function
mpfs_ep_set_fifo_size().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-18 22:47:29 +08:00
Ville Juven
15960f25a5 MPFS: Add board_memorymap.h
Move the target specific memory map to a separate file so there is no
need to copy&paste the __xxram_start etc linker symbols to each file
that needs them.

Also add MMU flags for I/O and kernel areas, they will be needed
when the kernel runs with virtual addresses also.
2022-03-18 09:35:00 -03:00
wangbowen6
7de7ba1b7e phy62xx_exception: using armv6-m exception_common code.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-03-18 20:01:00 +08:00
Ville Juven
ade848b60a MPFS: Use linker symbols for heap allocation 2022-03-18 18:20:12 +08:00
Ville Juven
75afe491ad RISC-V: Prepare for CONFIG_BUILD_KERNEL
- Thread context prior to system call needs to be preserved
- Allocate a kernel heap
2022-03-18 18:20:12 +08:00
Ville Juven
195705d11f MPFS: Create centralized module for PLIC address handling
Reduce complexity and copy-paste amount by implementing a module
to handle calculating PLIC offsets.
2022-03-18 18:20:12 +08:00
Ville Juven
745f00e77d MPFS: Use riscv_mhartid to obtain hartid
Preparation for S-mode, read mhartid via function call instead of
directly from the machine mode register
2022-03-18 18:20:12 +08:00
Ville Juven
f8ffcbbf36 MPFS: Remove definition and reference to MPFS_PLIC_CTRL
The register does not exist. c906 implementation has it, but MPFS does not.
2022-03-18 18:20:12 +08:00
Ville Juven
0f91eab626 MPFS: Protected mode, fix MMU mapping
The mapped vaddr was wrong, don't want to map the page tables, but
the user space area (start of .text) instead.
2022-03-18 18:20:12 +08:00
Ville Juven
9269a86d00 RISC-V: Add common data memory and instruction barriers 2022-03-18 18:20:12 +08:00
chao.an
19119a9c43 arch/arm: set the SP to stack top
fix the stack imbalance

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-18 07:56:51 +09:00
Abdelatif Guettouche
5085f854d0 esp32(s3)_start.c: In SMP mode, don't disable APP CPU at startup. It starts in a
disabled state and if OpenOCD is used this will clear OpenOCD configuration.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b98676f8be esp32(s3)_cpustart.c: Don't reset app CPU if it was already configured by
OpenOCD.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-17 14:33:32 -03:00
Abdelatif Guettouche
b10c8955cf arch/Kconfig: Don't depend on Xtensa for the SUPPRESS_CLOCK_CONFIG
option.  This config was probably added in the early bring up of the
ESP32 chip. At that point the clock config was suppressed and we relied
on the bootloader.  Now we can configure the clock from NuttX.

The option itself is still useful and can be used for any other
architecture or chip.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-17 14:33:12 -03:00
Xiang Xiao
c2a1d0f5ae procfs: Remove mallinfo from struct procfs_meminfo_entry_s
let's call mm_mallinfo directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-17 13:59:03 -03:00
Gustavo Henrique Nihei
baa09aa999 risc-v/esp32c3: Remove deprecated option for disabling atomics support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-17 23:40:29 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-17 15:43:30 +08:00
Petro Karashchenko
c3bae60c57 drivers/can: optimize can driver reader side
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-17 15:43:15 +08:00
Gustavo Henrique Nihei
39e9a17e60 xtensa/esp32s3: Apply style fixes throughout serial driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
0dc2930403 xtensa/esp32s3: Remove code for not yet supported USB-Serial Driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-16 19:06:39 -03:00
Gustavo Henrique Nihei
57273ad994 xtensa/esp32s3: Fix IRQ setup hardcoded to CPU 0
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-16 19:06:39 -03:00
Huang Qi
9cc0a609bd arch/risc-v: Correct stack coloration in riscv_cpu_boot
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-16 14:12:45 +02:00
SPRESENSE
c05ace557f arch: cxd56xx: Fix critical section in serial transmission
Fix an issue that the serial transmission buffers are corrupted because
serial transmission are not protected by critical section in non-smp mode.
2022-03-16 20:23:41 +09:00
Petro Karashchenko
985829190e arch/arm/samv7/sam_tc: implement timer driver support
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-16 03:19:57 +08:00
Eero Nurkkala
c38d547900 risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.

Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-16 00:59:25 +08:00
Ville Juven
e843c441de RISC-V: Fix nasty bug in PMP region test
The end address was not handled correctly, it is not a part of a mapped
region.
2022-03-15 18:59:20 +02:00
Matthew Trescott
8c471db932 Corrections to Tiva KConfig 2022-03-15 11:32:31 -04:00
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
chao.an
81130bc692 arch/arm: remove unused arm_copyfullstate/arm_copyarmstate
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
chao.an
7b9978883c arch/arm: optimize context switch speed
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 22:51:00 +02:00
chao.an
ea42981cc6 syscall/names: export the syscall name in STUB module
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 21:37:53 +02:00
chao.an
d398ffb930 arm/armv7-a/r: unified syscall registers dump
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 21:37:53 +02:00
chao.an
22e71e2d71 board/sim: add support of custom optimization level
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 23:25:26 +08:00
Abdelatif Guettouche
d21d02c65d xtensa_panic.S: Save exception cause and vaddr into the user frame.
This area is what's passed later to assert and be used to dump the
state.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 19:54:30 +08:00
Abdelatif Guettouche
a9e3b5ae37 xtensa_panic.S: A2 is already saved by the caller, no need to save it
here again.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 19:54:30 +08:00
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Abdelatif Guettouche
cff3d9df7b arch/xtensa: Fix some indentations. 2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
6fa4a42e34 xtensa/: Save A3 as part of the regular context saving.
It was separate because the syscal handler was using it before calling
_xtensa_context_save.  The order of operations has now changed and we
can save A3 with the rest of the context.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4d1bb20f8c xtensa_user_handler.S: In syscall handler store context before
continuing the rest of the syscall handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5305f76b1d xtensa_context.S: Use Zephyr's version of spilling the window register
file.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2445de173d xtensa_dumpstate.c: Don't dump temporary registers.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
4786963ee2 xtensa_context.S: No need to save A2 before calling
_xtensa_save_context.  It uses CALL0, in this case A1 is callee saved
and we can it directly.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
2dcbf28f15 xtensa_context.S: A1 should be restored by the caller not
xtensa_context_resotred. Here it was being restored twice.
Remove the one in xtensa_context_restore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
5bd2e97a27 xtensa_context.S: Fix the type of _xtensa_context_restore.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Abdelatif Guettouche
e9018b29bf xtensa_context.S: Remove the CALL0 ABI version of xtensa_context_switch
as it's the same as the Window ABI now.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-14 11:12:35 +08:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 10:17:25 +02:00
Xiang Xiao
f94093bc2e arch/ceva: Move the idle stack initialization to up_initial_state
to follow other arch's implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 00:28:05 +02:00
Xiang Xiao
1a7f49eeb3 arch/z[80|16]: Move up_getsp declaration to arch.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-12 19:21:59 +02:00
Gustavo Henrique Nihei
7ede285cfe xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-12 15:27:30 +02:00
Gustavo Henrique Nihei
86b18bd6e9 xtensa/esp32s3: Move code documentation to the correct place
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-12 11:53:14 +08:00
Gustavo Henrique Nihei
a4db4031c9 xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-12 11:53:14 +08:00
Xiang Xiao
39fb09738d arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-11 23:08:07 +02:00
Xiang Xiao
17d1a48fc9 arch: Remove up_puts prototype from up_inernal.h
since it's defined in include/nuttx/arch.h now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-11 23:08:07 +02:00
Jukka Laitinen
d9607f71d2 Revert "arch/risc-v: Correct FPU register save area in riscv_copystate"
This reverts commit 86358bff3bc814efb564a4427b4bcd6c3c91dbf0.
2022-03-11 23:43:41 +08:00
Petro Karashchenko
fc9e2d272e arch/arm/arm[-a|-r]: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-11 11:08:01 +08:00
Gustavo Henrique Nihei
c8796c1bc2 xtensa/esp32s3: Move SPI RAM configuration out of Peripheral menu
Menu for configuration of SPI RAM was wrongly placed inside the menu
for peripheral selection.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-11 11:05:24 +08:00
Abdelatif Guettouche
f0a5777a26 xtensa_swint.c: Restore the coprocessor state at the end for consistency.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
7c57739d1d xtensa_exit.c: Co-processor state is restored as part of the
SYS_Restore_context call, no need to call it separately.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
71ba4a6b76 arch/xtensa: Use the software interrupt when saving context too.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-11 02:23:09 +02:00
Abdelatif Guettouche
329db99e51 arch/xtensa: Use rsync around manipulating interrupt registers and
replace `isync` by `rsync` in other places.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-11 02:23:09 +02:00
Jukka Laitinen
81a19c1ce8 arch/riscv/src/mpfs: Make cleaner pinmux configurations for USB
Mux USB IO pins one-by-one using package specific pinmux definitions. This avoids accidentally overwriting IO settings for other pins.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-03-11 00:22:43 +02:00
Xiang Xiao
c0f3ac97bc arch/risc-v: Update opensbi to 4998a712b2ab504eff306110879ee05af6050177
include theis commit:
commit 6ad8917b7e27e5e80fb9268492b9111b17ed2024
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
Date:   Fri Jan 28 09:13:23 2022 +0200

    lib: fix compilation when strings.h is included

    In a systems that provide strings.h and it is included
    together with sbi_bitops.h the compilation error appears.
    The ffs() and fls() are provided by strings.h

    Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
    Reviewed-by: Anup Patel <anup@brainfault.org>

and fix this warning:
Error: include/sbi/sbi_bitops.h:47:19: declaration of 'ffs' shadows a built-in function
 static inline int ffs(int x)
                   ^~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
Xiang Xiao
29cb85ba17 arch/stm32: Fix compiler warning
chip/stm32_i2s.c:1949:12: error: conflicting types for built-in function 'roundf'; expected 'float(float)' [-Werror=builtin-declaration-mismatch]
 1949 | static int roundf(float num)
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
Xiang Xiao
a07dc2363e c5471/c5471_irq.c: Fix error: '__builtin_memcpy' forming offset [4, 31] is out of the bounds [0, 4] of object '_svectors' with type 'int'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
Huang Qi
8267a76186 arch/risc-v: Implement SYS_save_context in swint
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Huang Qi
7022c630fe arch/risc-v: Correct FPU register save area in riscv_copystate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Alan C. Assis
dc1b6776b9 xtensa/esp32s3: Add SPI RAM/PSRAM Support 2022-03-09 19:22:56 +02:00
Huang Qi
69cfe8d626 arch/arm: Support setjmp/longjmp for all socs
After check the official specification of ARM ISA
and Thumb ISA, the arch_setjmp_thumb.S are written
by arm unified assembly language,
so it easy to make it works for ARM and thumb ISA.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 17:13:21 +02:00
Eero Nurkkala
a21a396bd8 risc-v/mpfs: usb: apply review fixes
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-09 10:26:56 +02:00
chao.an
ba2cb65a91 arch/sim: add all symbols support
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-09 10:16:54 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Gustavo Henrique Nihei
4a29fa903b xtensa/esp32s3: Enable SMP support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-09 10:42:50 +08:00
Richard Tucker
4888be37e3 arch/arm/src/sam34/sam_dmac.c: Fix compilation error 2022-03-09 10:18:32 +08:00
Gustavo Henrique Nihei
140dc248db xtensa/esp32s2: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-08 22:24:07 -03:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 23:00:31 +08:00
Gustavo Henrique Nihei
bd7ee0d675 xtensa/esp32s2: Sync IRQ management API with ESP32 and ESP32-S3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-08 11:36:32 -03:00
Huang Qi
bfedbf1c05 arm/imx6: Enable setjmp test in ostest
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-08 21:00:29 +08:00
Huang Qi
cfff115f21 arm: Move setjmp to common place
Since some Cortex A core supports thumb mode also,
thus they can share same implementation.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-08 21:00:29 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 16:49:29 +08:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-08 10:14:04 +02:00
chao.an
a14ed02571 sim/syscall: add syscall note support in the flat build
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-07 23:58:28 +08:00
zhuyanlin
981282696f xtensa:backtrace: fix backtrace last buffer error in some scene
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-07 10:21:37 +01:00
Abdelatif Guettouche
fa0e5da18e xtensa/xtensa_user_handler.S: Store EXCCAUSE and EXCVADDR into the user
frame. The user frame is passed them to xtensa_user that actually uses
EXCVADDR.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-04 11:19:06 +02:00
Juha Niskanen
779665c704 arch/arm/src/stm32l4: STM32L4+ might need flash data cache corruption workaround
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2022-03-04 14:00:20 +08:00
Oleg Evseev
625d230d28 arch/arm/src/stm32f7/stm32_can.c: fix CAN3 receiving
by fixing filter initialization.

STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.
2022-03-03 14:31:37 -03:00
Abdelatif Guettouche
c820085a23 arch/xtensa/esp32s3: Add encrypted support for SPI FLASH.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-03 19:57:59 +08:00
Abdelatif Guettouche
9d5b13cd0e xtensa/esp32s3: Add SPI-Flash support.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-03 19:57:59 +08:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
zhuyanlin
5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation
Some chip not use the default cache size & way , read from
CCSIDR instead of hardcode.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-03 14:11:31 +08:00
Gustavo Henrique Nihei
16030f713e xtensa/esp32s3: Add support for Free-running Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-03 10:58:53 +08:00
Gustavo Henrique Nihei
3b7a6ae311 xtensa/esp32s3: Add support for Tickless kernel using Systimer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-02 18:08:44 +01:00
ligd
fe6aa4a874 sim: add loop thread to handle dev loops
For some dev loops will call sem_wait/sem_trywait

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-02 20:29:52 +09:00
Xiang Xiao
4a16cf71f9 Fix -Werror=nonnull-compare and -Werror=format-truncation=
Error: module/mod_insmod.c:203:3: error: 'strncpy' specified bound 16 equals destination size [-Werror=stringop-truncation]
  203 |   strncpy(modp->modname, modname, MODLIB_NAMEMAX);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

wqueue/kwork_thread.c: In function 'work_start_lowpri':
Error: wqueue/kwork_thread.c:212:22: error: '%lx' directive output may be truncated writing between 1 and 16 bytes into a region of size 14 [-Werror=format-truncation=]
  212 |   snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);

local/local_sockif.c: In function 'local_getsockname':
Error: local/local_sockif.c:392:11: error: 'strncpy' specified bound depends on the length of the source argument [-Werror=stringop-overflow=]
  392 |           strncpy(unaddr->sun_path, conn->lc_path, namelen);
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

chip/esp32_wifi_utils.c: In function 'esp_wifi_scan_event_parse':
Error: chip/esp32_wifi_utils.c:373:37: error: argument to 'sizeof' in 'memset' call is the same expression as the destination; did you mean to dereference it? [-Werror=sizeof-pointer-memaccess]
   memset(ap_list_buffer, 0x0, sizeof(ap_list_buffer));
                                     ^

stdio/lib_fputs.c: In function 'fputs':
Error: stdio/lib_fputs.c:99:9: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s == NULL || stream == NULL)
         ^
Error: stdio/lib_fputs.c:99:27: error: nonnull argument 'stream' compared to NULL [-Werror=nonnull-compare]
   if (s == NULL || stream == NULL)
                           ^

stdio/lib_vfprintf.c: In function 'vfprintf':
Error: stdio/lib_vfprintf.c:40:6: error: nonnull argument 'stream' compared to NULL [-Werror=nonnull-compare]
   if (stream)
      ^

string/lib_strdup.c: In function 'strdup':
Error: string/lib_strdup.c:39:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

string/lib_strndup.c: In function 'strndup':
Error: string/lib_strndup.c:56:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

string/lib_strpbrk.c: In function 'strpbrk':
Error: string/lib_strpbrk.c:39:7: error: nonnull argument 'str' compared to NULL [-Werror=nonnull-compare]
   if (!str || !charset)
       ^~~~
Error: string/lib_strpbrk.c:39:15: error: nonnull argument 'charset' compared to NULL [-Werror=nonnull-compare]
   if (!str || !charset)
               ^~~~~~~~

string/lib_strrchr.c: In function 'strrchr':
Error: string/lib_strrchr.c:40:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

Error: time/lib_asctimer.c:73:50: error: '%d' directive output may be truncated writing between 1 and 11 bytes into a region of size between 0 and 12 [-Werror=format-truncation=]
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
                                                  ^~
time/lib_asctimer.c:73:21: note: directive argument in the range [-2147481748, 2147483647]
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
time/lib_asctimer.c:73:3: note: 'snprintf' output between 17 and 68 bytes into a destination of size 26
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            g_wday_name[tp->tm_wday], g_mon_name[tp->tm_mon],
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            tp->tm_mday, tp->tm_hour, tp->tm_min, tp->tm_sec,
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            1900 + tp->tm_year);
            ~~~~~~~~~~~~~~~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-02 15:55:38 +08:00
zhuyanlin
a4e93be0fb arch:xtensa: fix sp duplicate reduce in handler enter
In xtensa/include/irq.h the XCPTCONTEXT_SIZE is
`#define XCPTCONTEXT_SIZE    ((4 * XCPTCONTEXT_REGS) + 0x20)`

XCPTCONTEXT_SIZE is already byte size of xcpcontext

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-01 13:46:31 +01:00
Xiang Xiao
a8ab090764 sim: Simplify boards and arch's Makefile
1.Remove the unused LIBPATHS and HOSTLDFLAGS
2.Move HOSTCFLAGS to arch/Makefile

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-01 12:33:56 +01:00
Masayuki Ishikawa
2a434fe1fa arch: imx6: Add the pgheap for imx6
Summary:
- This commit adds the pgheap for imx6

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-03-01 12:18:47 +08:00
Xiang Xiao
da954956e7 Simplify DEFAULT_SMALL usage in Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-01 03:15:01 +08:00
chao.an
0961f12e28 arm/phy62xx: remove unused private header
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-01 00:33:58 +08:00
Xiang Xiao
9bc2b4c31b board/sim: Remove CCLINKFLAGS, use CFLAGS/CXXFLAGS instead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 23:13:22 +08:00
Huang Qi
d0356bb9ba arch/risc-v/qemu-rv: Set FS bits in mstatus
FPU test may fail without correct FS bits.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-28 16:28:22 +08:00
Masayuki Ishikawa
56e0e6a5ec arch: imx6: Remove sem_t from imx_serial.c
Summary:
- I noticed that when exiting getprime, DEBUGASSERT happens in
  nxsem_wait()
- Finally, I found that up_putc() uses nxsem_wait()
- This commit fixes this issue by removing the semaphore.
- Also, up_putc() now calls imx_lowputc()

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-28 16:09:01 +08:00
Masayuki Ishikawa
a75d905760 arch: imx6: Refactor imx_lowputc()
Summary:
- Remove '\n' -> '\r\n' conversion
- Remove waiting for FIFO empty after sending a character
- Remove CONFIG_DEBUG_FEATURES

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-28 16:09:01 +08:00
Xiang Xiao
872c570343 arch: Align the implementation of stack related functions
arm: Avoid call k[u]mm_memalign to save the code size
ceva: Correct stack_base_ptr usage(top of stack v.s. bottom of stack)
mips: Correct the stack alignment in up_use_stack
misoc: Correct the stack alignment in up_use_stack
or1k: Correct the stack alignment in up_use_stack

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 15:05:41 +08:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 15:05:41 +08:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
0c7517e579 arch: Remove the duplicated syscall.h in each arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
8b77801b1c arch/xtensa: Remove the unused SYS_pthread_exit
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
chao.an
b57e0b6118 arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-27 17:25:22 +09:00
chao.an
c369e47107 arm/armv7-a/r: handle swi on interrupt stack
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-27 17:25:22 +09:00
lp.xiao
fac10b6ebd stm32f103re has a dac module.but the pinmap file has no corresponding definition 2022-02-27 14:39:17 +08:00
Xiang Xiao
f634ea24b5 arch/sim: Don't include execinfo.h since cygwin doesn't support it
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-26 07:05:42 -06:00
Jiuzhu Dong
c5ba9261bc procfs: add memdump interface to dump used/free memory info
usage:echo <used/free> > /proc/memdump
echo used > /proc/memdump // output all used memory node info(address + size)
echo free > /proc/memdump // output all free memory node info(address + size)

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-02-26 14:32:42 +08:00
Xiang Xiao
b95022f8de arm/armv7-a: Remove CONFIG_SMP guard from arm_scu.c
since ACTLR.SMP need enable to make cache work on Cortex A7:
https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-26 14:15:30 +09:00
Gustavo Henrique Nihei
6a12befcd5 xtensa/esp32s2: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
d2ada5f030 xtensa/esp32: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00