Commit Graph

886 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
baa09aa999 risc-v/esp32c3: Remove deprecated option for disabling atomics support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-17 23:40:29 +08:00
Huang Qi
807304f283 arch/risc-v: Rework riscv_get_newintctx
Some fields of mstatus were marked as Reserved Writes Preserve Values, Reads Ignore Values (WPRI),
so we must keep its origin value with addition flags.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-17 15:43:30 +08:00
Huang Qi
9cc0a609bd arch/risc-v: Correct stack coloration in riscv_cpu_boot
In smp system riscv_cpu_boot run in idle task so there is a overlap with the origin coloration range and in used stack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-16 14:12:45 +02:00
Eero Nurkkala
c38d547900 risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
Fix EP0 stall and resume properly. EP0 wasn't clearly addressed
on stall / resume operations.

Also fix data reads that provide garbage for the first request.
It has always random data as it's completed prior to any read
operation.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-16 00:59:25 +08:00
Ville Juven
e843c441de RISC-V: Fix nasty bug in PMP region test
The end address was not handled correctly, it is not a part of a mapped
region.
2022-03-15 18:59:20 +02:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 22:51:00 +02:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Xiang Xiao
e800f54bfd arch/mpfs: Don't include nuttx header file in mpfs_opensbi.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-14 09:32:17 +02:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 11:24:48 -03:00
Xiang Xiao
ea614090cd arch/risc-v: Change hex number to low case in csr.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-13 10:17:25 +02:00
Jukka Laitinen
d9607f71d2 Revert "arch/risc-v: Correct FPU register save area in riscv_copystate"
This reverts commit 86358bff3bc814efb564a4427b4bcd6c3c91dbf0.
2022-03-11 23:43:41 +08:00
Jukka Laitinen
81a19c1ce8 arch/riscv/src/mpfs: Make cleaner pinmux configurations for USB
Mux USB IO pins one-by-one using package specific pinmux definitions. This avoids accidentally overwriting IO settings for other pins.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-03-11 00:22:43 +02:00
Xiang Xiao
c0f3ac97bc arch/risc-v: Update opensbi to 4998a712b2ab504eff306110879ee05af6050177
include theis commit:
commit 6ad8917b7e27e5e80fb9268492b9111b17ed2024
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
Date:   Fri Jan 28 09:13:23 2022 +0200

    lib: fix compilation when strings.h is included

    In a systems that provide strings.h and it is included
    together with sbi_bitops.h the compilation error appears.
    The ffs() and fls() are provided by strings.h

    Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
    Reviewed-by: Anup Patel <anup@brainfault.org>

and fix this warning:
Error: include/sbi/sbi_bitops.h:47:19: declaration of 'ffs' shadows a built-in function
 static inline int ffs(int x)
                   ^~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-10 19:46:01 +02:00
Huang Qi
8267a76186 arch/risc-v: Implement SYS_save_context in swint
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Huang Qi
7022c630fe arch/risc-v: Correct FPU register save area in riscv_copystate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-10 16:11:14 +08:00
Eero Nurkkala
a21a396bd8 risc-v/mpfs: usb: apply review fixes
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-09 10:26:56 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 23:00:31 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 16:49:29 +08:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-08 10:14:04 +02:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
Huang Qi
d0356bb9ba arch/risc-v/qemu-rv: Set FS bits in mstatus
FPU test may fail without correct FS bits.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-28 16:28:22 +08:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 15:05:41 +08:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Gustavo Henrique Nihei
36ac532c98 risc-v/esp32c3: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
a6fea1c3a5 risc-v/esp32c3: Enable Timer Groups clocks on timer initialization
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 22:49:22 +08:00
Gustavo Henrique Nihei
1d15196df7 risc-v/esp32c3: Fix detection of CPU reset by Watchdog Timer
This commit fixes an issue where some peripheral clocks are being
disabled during CPU reset on ESP32-C3.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 22:48:09 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Xiang Xiao
6fa5885d2d arch/esp32: Update esp-wireless-drivers-3rdparty to verion 45701c0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 09:05:40 +01:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-23 01:21:26 +08:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
2022-02-17 02:55:25 +08:00
Xiang Xiao
db57e2cd8e Fix the minor style issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 15:26:38 +01:00
Huang Qi
5cde8c6934 risc-v: Let g_cpu_basestack determined at compile time
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
55d88627a0 risc-v: Implement common up_cpu_idlestack
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-12 21:07:35 +09:00
Huang Qi
3fe9c9523c risc-v: Fix style issue in SoC's Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-11 15:20:17 +08:00
Alan C. Assis
d49ad207ef esp32c3: Fix issue #5377 UART1 not working because clock as disabled 2022-02-11 10:01:25 +08:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
9223547afc risc-v: Support cpu activity led in up_idle
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
6f18747dc2 risc-v: Add WFI to up_idle and fix compile issue
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
9d91d69ee0 arch/risc-v/mpfs: Remove riscv_pthread_exit.c in Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit"
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Abdelatif Guettouche
f49a579721 esp32c3/: Remove unused exported variables from ROM and add declaration
for the one used.
2022-01-31 23:35:50 +08:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-30 11:04:35 +09:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-28 12:02:38 +01:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
2022-01-27 10:22:30 +01:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine
This way old PMP configurations are removed upon warm reset.
2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Jukka Laitinen
49085eebae arch/risc-v/src: Cleanups for opensbi
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
5bb3936212 arch/risc-v/src/opensbi: Update 3rd party opensbi version into Make.defs
This fixes build errors with more strict compiler settings

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
8a6d62423d Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit d611e2d99b.
2022-01-25 00:10:46 +08:00
Eero Nurkkala
eb462a2eb3 risc-v/mpfs: configure harts according to CONFIG_MPFS_HART*_SBI
The following options need to be taken in account while determining
the proper hart_index2id -table:
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART3_SBI
  CONFIG_MPFS_HART4_SBI

Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Huang Qi
71d3ff1045 arch/risc-v: Remove g_serial_ok
`WFI` is enough to wait the ready signal from master core,
so we can remove it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Huang Qi
422e005183 arch/risc-v: Move xxx_cpustart.c to common
It's a common solution for MSIP and IPI based risc-v smp soc,
also works on qemu-rv smp (WIP).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Norman Rasmussen
da5659138b Fix regression where used code was marked as unused
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
2022-01-23 14:57:19 +08:00
Petro Karashchenko
6c27f3c19d toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 15:36:29 +08:00
Petro Karashchenko
d611e2d99b risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 14:58:56 +08:00
Huang Qi
b803919b9d arch/risc-v: Merge mcause.h into irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-22 14:57:05 +08:00
Jukka Laitinen
9061c92ec8 arch/risc-v/src/mpfs: Make each hart entry configurable for bootloader
Add two config flags for each hart for a bootloader nuttx:

CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.

CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
  from SBI if CONFIG_MPFS_HARTx_SBI is set

This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Jukka Laitinen
36b73fd0a3 arch/risc-v/src/mpfs/mpfs_opensbi.c: Ensure stack alignment of 16 bytes
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Eero Nurkkala
2a22c0e32d risc-v/mpfs: OpenSBI: utilize an index2id table
Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-21 13:40:58 -03:00
Abdelatif Guettouche
8c582c27b8 esp32c3_irq.c: Add a comment explaining the assigment of CURRENT_REGS to
regs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Abdelatif Guettouche
e335d44028 esp32c3_irq.c: Skip over ECALL instruction.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Petro Karashchenko
a32381ca32 Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit 1dccc374ab.
2022-01-21 21:38:31 +08:00
Petro Karashchenko
1dccc374ab risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-21 17:12:22 +08:00
Huang Qi
d846bb0235 arch/risc-v: Remove dupped irq code from mpfs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f arch/risc-v: Remove dupped irq code from rv32m1
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090 arch/risc-v: Remove dupped irq code from litex
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5 arch/risc-v: Remove dupped irq code from c906
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c arch/risc-v: Remove dupped irq code from bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc arch/risc-v: Remove dupped irq code from qemu-rv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e arch/risc-v: Unify common irq code to arch/irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Ville Juven
0a1a1e9b79 Fix user PGT flags (don't map them globally)
A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31 Add pte getter to RISC-V MMU driver
Like the title says, a getter to read one PTE.
2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937 RISC-V MMU driver: fix region setting for L1/L2 page tables
The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
2022-01-20 20:30:13 +08:00
Ville Juven
e676d2985d Present common MMU flags in common MMU driver header
Flags to use for intermediate page tables, as well as leaf entries
2022-01-20 20:30:13 +08:00
Ville Juven
33435e76da Changes to Sv39 MMU driver public header
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
  combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
2022-01-20 20:30:13 +08:00
Ville Juven
926a19217e Add simple MMU driver for RISC-V (Sv39)
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.

The driver is tested with mpfs only, but it should work with any riscv
implementation.
2022-01-20 20:30:13 +08:00
Eero Nurkkala
133faf203d risc-v/mpfs: don't reset uart1 while entering OpenSBI
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-20 18:37:08 +08:00
Eero Nurkkala
54a4eb01ce risc-v/mpfs: avoid OpenSBI redefinition conflicts
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-20 18:37:08 +08:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Jukka Laitinen
6428c1fdc4 arch/riscv/mpfs: Switch to use riscv_exception_common
Clean up mpfs port by using the common code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Jukka Laitinen
7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
  support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
  only on one hart, but the startup code executes on all harts and handles SW IRQs

Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Petro Karashchenko
9551de7115 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-18 10:59:47 +01:00
Huang Qi
676d35f007 risc-v: Make exception_common 8 byte align
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-17 11:44:50 +08:00
Huang Qi
e97ba17451 arch/risc-v: Refine riscv_cpupause.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-16 23:11:32 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
Huang Qi
3200c936cc arch/risc-v: Refine riscv_cpuindex.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 21:54:05 +08:00
Huang Qi
56a95ad0b5 risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Huang Qi
74cce59ac6 arch/risc-v: Make ISA configurable for qemu-rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
chao.an
3544fc1fd6 risc-v/assert: add CURRENT_REGS check to avoid null pointer reference
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-15 02:20:01 +08:00
Eero Nurkkala
09bf8a5f89 risc-v/mpfs: mpfs_opensbi: fix fw_size calculation
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.

Also add the next_arg1 initialization.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Jukka Laitinen
122b907b91 arch/risc-v/src/mpfs/mpfs_opensbi_utils.S: Remove unncessary mv
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-14 10:10:24 +01:00
Huang Qi
6f1011a85e arch/risc-v: Rename bl602_entry.S to bl602_head.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 22:06:49 +01:00
Huang Qi
7c93e96908 arch/risc-v: Fix typo in riscv_assert.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Huang Qi
3c15ae23cf arch/risc-v: Make __tarp_vec 4 byte align
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Huang Qi
e47a915f4c arch/risc-v: Refine riscv_vectors.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-12 18:53:01 +08:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-11 23:24:33 +08:00
chao.an
8c35d31808 Kconfig: Remove CONFIG_ prefix from config definition
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-07 13:16:18 +08:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
2022-01-05 21:36:44 +09:00
Jukka Laitinen
9aea5d5dbb arch/risc-v/src/mpfs/mpfs_serial.c: Correct setting of nbits
Number of bits was set wrongly in TCSETS for mpfs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-05 12:21:38 +08:00
Huang Qi
3a0e86c99b arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 23:22:43 +08:00
Eero Nurkkala
c87ae33459 risc-v/opensbi: update to version 1.0
OpenSBI recently introduced version 1.0. Use the latest
version here as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-04 15:50:25 +08:00
Huang Qi
845168ce12 arch/risc-v: Refine riscv_assert.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 14:46:24 +08:00
Huang Qi
a6662c2887 arch/risc-v: Refine arch.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 14:46:24 +08:00
Gustavo Henrique Nihei
c04fbb0365 risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-02 20:50:30 +01:00
Huang Qi
b11e90f384 arch/risc-v: Refine riscv_initialstate.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
74c02fbadb risc-v/esp32c3: Remove unavailable support for ROM Basic Console
This feature is only available on ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 22:54:17 +09:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-30 16:57:40 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 06:06:01 -06:00
Huang Qi
901361be48 arch/risc-v: Move more files to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121 arch/risc-v: Refine riscv_fpu.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 12:09:54 +08:00
Huang Qi
e75321e61c arch/risc-v: Move riscv_blocktask.c to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a Use userspace chosen channel numbers when starting bl602 pwm
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
2021-12-28 06:27:51 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
Norman Rasmussen
1e2f067181 pwm: add option to break the loops when using multiple PWM channels
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
Eero Nurkkala
3394dca826 risc-v/opensbi: Make.defs: use a wildcard for file listing
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
chao.an
362fe2c6f8 arch/risc-v: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
ChenWen
6d165506d5 risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts 2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96 risc-v/esp32c3: Remove deprecated note about Flash Detect feature
Flash Detect option is already available on esptool.py installed via pip

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
1c8e84b341 risc-v/esp32c3: Add Secure Boot support on top of MCUboot
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393 Kconfig: fix non-string default values uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:10:57 +01:00
xiewenxiang
b1d051b651 riscv/esp32c3: Initialize the BLE Mac 2021-12-16 22:31:02 -03:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 01:43:18 -06:00
lupyuen
2a87b37a69 riscv/bl602: Swap SPI MISO and MOSI 2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-12 10:19:00 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash
This can fix BLE assert when erase SPI Flash.
2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0]
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Abdelatif Guettouche
251b8a3445 esp32xx_rtc: Include "clock/clock.h" to have a declaration of
g_basetime.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1 esp32xx_rtc.c: Fix a duplicated assignment.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c risc-v/esp32c3: Refactor ADC calibration
Use calibration parameters from efuse rather than self-calibration.
2021-11-26 15:23:24 -03:00
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a Fix GPIO output 2021-11-24 06:48:50 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2021-11-18 10:59:44 -03:00
Eero Nurkkala
6db480a7f9 mpfs: emmcsd: boost waitresponse perf
When waiting for a response to a sent command, the command
complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee
the completion of that particular command. There's no need
to have some combinations skipping the check of the command
complete bit. Thus, remove the 'waitbits' parameter as it's
unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-16 10:25:57 -06:00
Dong Heng
92eedd93a7 risc-v/esp32c3: Fix reset triggering crash nested when crash 2021-11-16 10:44:54 -03:00
Abdelatif Guettouche
5a41572fd0 esp32c3/esp32c3_usbserial.c: Initialize cpuint to ENOMEM, otherwise the
first attempt to attaching an interrupt will trigger an assertion.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-15 12:11:45 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-15 00:04:12 +01:00
Abdelatif Guettouche
6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Dong Heng
fed7808d80 esp32 & esp32c3: Partition supports BIO cmd 2021-11-13 05:58:30 -06:00
Dong Heng
f5c5d77744 risc-v/esp32c3: Add hardware brownout check and reset 2021-11-12 16:50:19 -03:00
Eero Nurkkala
876b39914b mpfs: uart: add a way to configure uart3 and uart4
Currently configuring the uart3/4 as the serial console
doesn't work. Apply proper changes in mpfs_config.h that
enables the following configuration options:

 - CONFIG_UART3_SERIAL_CONSOLE
 - CONFIG_UART4_SERIAL_CONSOLE

Also, fix a typo in mpfs_lowputc.c that gives a compile
error if defined.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-11 06:02:27 -06:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug.
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-10 14:31:10 -03:00
Alan C. Assis
b8c33e585e esp32c3: Fix GPIO Output on pins 18 and 19 USB/JTAG 2021-11-09 20:54:34 -06:00
Abdelatif Guettouche
23039c92cf esp32c3/Make.defs: Alawys build esp32c3_serial.c
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
ebd94961c7 arch/riscv/esp32c3: Add the USB-Serial Driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
17cf3edf46 arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG
controller.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00