nuttx

Author	SHA1	Message	Date
Alan C. Assis	2079cc0f6e	esp32: Add support to RS485	2022-01-10 10:49:16 +08:00
Petro Karashchenko	1fd51ccbe2	arch/arm/samv7: rework SAMv7 timer counter implementation There are two issues that are addressed with this change: - According to SAM E70/S70/V70/V71 Family datasheet the timer counter channels are 16-bit so timer counter value should be changed from uint32_t to uint16_t - The interrupt handling for timer counter channels can be simplified Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-09 17:43:31 +08:00
Xiang Xiao	bbf5511e3a	arch/sim: Move the dummy ioe driver to drivers/ioexpender Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-09 11:06:06 +08:00
Xiang Xiao	b054bd9d37	arch/sim: Move the dummy foc driver to drivers/motor/foc Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-09 11:06:06 +08:00
Alan C. Assis	4ca38c6c50	esp32: Add PWM support using the LEDC peripheral Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-08 14:46:51 +01:00
Petro Karashchenko	e7f9c7af21	typos: fix typos in Kconfig files Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-08 06:46:26 -03:00
Gustavo Henrique Nihei	73ea0c1627	xtensa: Improve Kconfig description of ESP32-S2 arch family Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are composed of a single Xtensa LX7 core. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-01-07 22:25:05 +01:00
Xiang Xiao	3156a96a1b	arch/sim: Move qspiflash simulation to drivers/spi instead since it's common implementation can be used in other arch too Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-07 23:50:11 +08:00
Xiang Xiao	d296f9c085	arch/sim: Move spiflash simulation to drivers/spi instead since it's common implementation can be used in other arch too Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-07 23:50:11 +08:00
ligd	ee916bdb91	CEVA: add ceva platform xc5 xm6 support Signed-off-by: ligd <liguiding1@xiaomi.com>	2022-01-07 09:31:59 -03:00
Xiang Xiao	49c00e0361	arch/sim: Rename up_vfork[32\|64].S to up_vfork_x86[_64].S to follow other arch/x86 arch/x86_64 convention Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-07 15:59:34 +08:00
Xiang Xiao	1a02556265	Revert "arch/sim: Rename up_vfork[32\|64].S to up_vfork_x[32\|64].S" This reverts commit `3982296294`.	2022-01-07 15:59:34 +08:00
chao.an	8c35d31808	Kconfig: Remove CONFIG_ prefix from config definition Signed-off-by: chao.an <anchao@xiaomi.com>	2022-01-07 13:16:18 +08:00
Xiang Xiao	3982296294	arch/sim: Rename up_vfork[32\|64].S to up_vfork_x[32\|64].S to align with up_vfork_arm.S naming style Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-06 09:42:44 +01:00
raiden00pl	6fe95d8314	stm32: add SocketCAN support, based on stm32_can.c	2022-01-05 06:16:41 -08:00
Zeng Zhaoxiu	fb43fd73ed	signal: signal handler may cause task's state error For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2) in signal handler, and take sem2 successfully, after exit from signal handler to task, nxsem_wait(sem1) returns OK, but the correct result should be -EINTR. Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>	2022-01-05 21:36:44 +09:00
raiden00pl	5b9b3814f8	stm32: add CAN error support	2022-01-05 18:33:06 +08:00
Jukka Laitinen	9aea5d5dbb	arch/risc-v/src/mpfs/mpfs_serial.c: Correct setting of nbits Number of bits was set wrongly in TCSETS for mpfs Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2022-01-05 12:21:38 +08:00
Huang Qi	3a0e86c99b	arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64 It can provide better auto complete experience for modern code editor, since they use clang/gcc based parser to analyze code but lacks some target dependent info such as __LP64__ for riscv64. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-01-04 23:22:43 +08:00
Eero Nurkkala	c87ae33459	risc-v/opensbi: update to version 1.0 OpenSBI recently introduced version 1.0. Use the latest version here as well. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2022-01-04 15:50:25 +08:00
Huang Qi	845168ce12	arch/risc-v: Refine riscv_assert.c Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-01-04 14:46:24 +08:00
Huang Qi	a6662c2887	arch/risc-v: Refine arch.h Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-01-04 14:46:24 +08:00
Abdelatif Guettouche	4edc5fb701	xtensa: Rename up_stack_color to xtensa_stack_color since it's an internal function. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2022-01-04 02:45:45 +08:00
Petro Karashchenko	4b190fbce1	arch/arm/samv7: correct number on interrupts Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-03 22:10:22 +08:00
Petro Karashchenko	6c2b40f98a	typos: fix typos in many files Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-03 22:10:07 +08:00
Gustavo Henrique Nihei	c04fbb0365	risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-01-03 10:37:04 -03:00
Gustavo Henrique Nihei	78362b0949	xtensa/esp32: Use ROM implementations of libc functions Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-01-03 10:37:04 -03:00
Petro Karashchenko	c7d3a674fd	drivers/sensors/as5048b: fix lower half init issue Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-03 11:38:44 +08:00
Xiang Xiao	d2309195da	boards/sim: Add vncserver config for test Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2022-01-03 11:19:32 +08:00
Petro Karashchenko	d23ad9b9b0	userspace: fix typos in comments Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2022-01-02 20:50:30 +01:00
Huang Qi	b11e90f384	arch/risc-v: Refine riscv_initialstate.c Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei	c1fac720ec	xtensa/esp32: Add missing param documentation for SPI Flash function Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei	25f2dc2077	risc-v/esp32c3: Enable the creation of encrypted Flash partitions Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei	9e5e60ba48	esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support	2022-01-01 20:37:44 +08:00
Norman Rasmussen	185de258bf	Fix preprocessing directives for uart flow control commit `58bd873729` had a mix of `#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl logic which causes compile warnings.	2021-12-31 18:51:17 +08:00
Dong Heng	c56c58020a	risc-v/esp32c3: SPI flash MTD device uses all flash space	2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei	f130d8b91e	xtensa/esp32s2: Remove unavailable support for ROM Basic Console This feature is only available for ESP32 chips. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-31 00:56:08 +08:00
Gustavo Henrique Nihei	74c02fbadb	risc-v/esp32c3: Remove unavailable support for ROM Basic Console This feature is only available on ESP32 chips. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-31 00:56:08 +08:00
Huang Qi	33df35f003	arch/risc-v: Correct epc adjustment with C ISA Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-30 22:54:17 +09:00
chao.an	736add0fe8	arch/backtrace: correct the skip counter Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-30 16:57:40 +08:00
Gustavo Henrique Nihei	80da9abd6a	xtensa/esp32: Move assertions after logging to improve debugging Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei	b6addaa4c7	xtensa/esp32: Enable the creation of encrypted Flash partitions Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei	340e0c8a8f	xtensa/esp32: Build MCUboot bootloader with Flash Encryption support Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-30 12:35:41 +08:00
Jukka Laitinen	3beecbe905	risc-v/mpfs: Add MSSIO GPIO pinmap configuration Add a pinmap header for mpfs to be able to configure MSSIO GPIOs This also adds Kconfigs for some different chip/package types of the PolarFire SOC Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-12-30 11:49:00 +08:00
Huang Qi	2de22980e5	arch/risc-v: Refine syscall interface Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-30 11:47:42 +08:00
Norman Rasmussen	091322ba4a	Add backtrace to risc-v common sources	2021-12-30 01:30:08 +08:00
Xiang Xiao	b92c90ee81	arch/arm: Fix rebase error in arm_backtrace_thumb.c Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-29 20:42:05 +08:00
Huang Qi	c15195b126	arch/risc-v: Refine riscv_testset.S Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-29 06:06:01 -06:00
Xiang Xiao	228442ee23	arch/renesas: Undefine macro B0 to avoid the confliction Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-29 08:11:08 -03:00
Huang Qi	901361be48	arch/risc-v: Move more files to common Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-29 01:19:30 -06:00
Huang Qi	22ae2e0121	arch/risc-v: Refine riscv_fpu.S Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-29 01:19:30 -06:00
ChenWen	6ce335fa84	xtensa/esp32: Fix some Wi-Fi issues 1. Fix the issue that Wi-Fi can't connect to some special routers occasionally. 2. Update Wi-Fi driver code to fix issue of failure to send pkt. 3. Replace software random with hardware random	2021-12-28 23:48:25 -06:00
chao.an	7ed0b97414	make/allsyms: skip the unnecessary link operation For incremental compilation, skip the stage 1 dummy link operation if nuttx elf has been generated Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-28 23:47:10 -06:00
Xiang Xiao	186ac17f1f	arch: Select ARCH_HAVE_BACKTRACE in Kconfig for supported arch Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-29 13:34:02 +08:00
Xiang Xiao	dd942f0b04	sched/backtrace: Dump the complete stack regardless the depth Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-29 12:09:54 +08:00
Xiang Xiao	f302e8fd40	arch/sim: Implement up_backtrace Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-29 11:03:08 +08:00
Xiang Xiao	f061766801	video/fb: Fix typo error in include/nuttx/video/fb.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-28 17:21:18 -03:00
Huang Qi	e75321e61c	arch/risc-v: Move riscv_blocktask.c to common Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-28 11:32:15 -06:00
Norman Rasmussen	934a79736a	Use userspace chosen channel numbers when starting bl602 pwm commit `2889315c20` added support for pwm but didn't read the channel numbers provided by user-space. They should be, otherwise it's not possible to start a sub-set of channels that are not the first "n" channels.	2021-12-28 06:27:51 -06:00
chao.an	cf2dfa8985	arch/arm/assert: move the arm_assert to common code Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-28 05:09:30 -06:00
Huang Qi	d71cfc178a	arch/risc-v: Remove unneeded kconfigs CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is controlled by M extension. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-28 05:02:42 -06:00
chao.an	579738c8fa	arch/arm: move the backtrace implement to common code Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-28 03:02:01 -06:00
Norman Rasmussen	1e2f067181	pwm: add option to break the loops when using multiple PWM channels commit `7354ab187e` added an option to break the loops when using multiple PWM channels to arm pwm drivers. This adds the same support to the risc-v pwm drivers.	2021-12-28 03:01:27 -06:00
Huang Qi	c2e8c92b25	arch/risc-v: Refine Toolchain.defs Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-28 00:30:10 -06:00
chao.an	a42aa8415d	compile/flags: add FRAME_POINTER into Toolchain.defs Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-27 22:31:27 -06:00
chao.an	8eb999ff03	arch/arm: select ARM_THUMB by default for Cortex-M Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-27 22:30:53 -06:00
Petro Karashchenko	3ccb657dc2	nuttx: remove space befone newline in logs Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-27 21:01:19 -06:00
Huang Qi	0751bcd4ca	arch/sim: Support vncserver as display device Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-24 11:59:43 -06:00
Alan C. Assis	01e4e249cc	Add WiFi/BLE Coexistence support Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-23 20:42:23 -06:00
chao.an	6069433d2d	arch/arm/cortex-a/r: dump all registers with alias Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-23 06:54:32 -06:00
Eero Nurkkala	3394dca826	risc-v/opensbi: Make.defs: use a wildcard for file listing The source directory contents of the OpenSBI directory lib/sbi may be listed with a one-line wildcard. This makes the Make.defs file look simpler. The rest of the files need to be picked one at a time. Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae> Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-12-23 02:42:09 -06:00
Eero Nurkkala	b128ce334f	mpfs: introduce OpenSBI OpenSBI may be compiled as an external library. OpenSBI commit d249d65 (Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to end up in the wrong section. That issue has yet no known workaround. OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot and eventually the Linux kernel on harts 1-4. OpenSBI, once initialized properly, will trap and handle illegal instructions (for example, CSR time) and unaligned address accesses among other things. Due to size size limitations for the mpfs eNVM area where the NuttX is located, we actually set up the OpenSBI on its own section which is in the bottom of the DDR memory. Special care must be taken so that the kernel doesn't override the OpenSBI. For example, the Linux device tree may reserve some space from the beginning: opensbi_reserved: opensbi@80000000 { reg = <0x80000000 0x200000>; label = "opensbi-reserved"; }; The resulting nuttx.bin file is very large, but objcopy is used to create the final binary images for the regions (eNVM and DDR) using the nuttx elf file. Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com> Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-12-22 20:48:12 -06:00
Eero Nurkkala	491ae6cc53	mpfs: cache: assign ways to L2 zero device Assign ways to L2 zerodevice. L2 zero device is used for the scratchpad functionality. The area may be used for the harts communicating to each other. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-12-22 20:48:12 -06:00
David Sidrane	74e692b3c1	stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite For FAT the same buffer is used for read and writes, there is a possibility a cache line is dirty. But the fs is not dirty and will not write the sector to disk. This can be seen https://github.com/PX4/NuttX/pull/175 When the system is busy that cache line can be evicted after the RX DMA has completed and overwrite the data in memory. The solution is to invalidate before the DMA to prevent an evection causing an overwite, and after the DMA it to insure coherency.	2021-12-22 20:44:04 -06:00
chao.an	fe2830ec94	xtensa: enhance the task dump add irq stack information add cpu loading Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-22 11:46:02 -03:00
chao.an	362fe2c6f8	arch/risc-v: enhance the task dump add irq stack information add cpu loading Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-22 11:46:02 -03:00
chao.an	a0b61bbf6f	arm/cortex-a/r: enhance the task dump add irq stack information add cpu loading Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-22 11:46:02 -03:00
Abdelatif Guettouche	4f0dd95fe1	arch/Kconfig: Add HAVE_SYSCALL_HOOKS configs to Xtensa arch. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-22 06:26:36 -06:00
Xiang Xiao	b03886415f	sim/netdev: Update IFF_RUNNING flag by netdev_carrier_on and netdev_carrier_off Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-22 07:15:00 -03:00
chao.an	2737701996	cortex-m/hardfault: add secure-fault handler Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-21 07:08:13 -06:00
ChenWen	6d165506d5	risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts	2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei	c471f0fe96	risc-v/esp32c3: Remove deprecated note about Flash Detect feature Flash Detect option is already available on esptool.py installed via pip Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei	1c8e84b341	risc-v/esp32c3: Add Secure Boot support on top of MCUboot Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei	f542ab4564	xtensa/esp32s2: Add Secure Boot support on top of MCUboot Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei	d22a2aa7a0	xtensa/esp32: Refactor makefiles for compliance to Function Call Syntax According to Make documentation: - "Commas and unmatched parentheses or braces cannot appear in the text of an argument as written"; - "Leading spaces cannot appear in the text of the first argument as written". Although in the current state it was not resulting in parsing issues, it is better to fix it. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei	6c3223289f	xtensa/esp32: Add Secure Boot support on top of MCUboot This adds the capabitlity of building signed images on NuttX. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-12-21 07:02:40 -06:00
Juha Niskanen	54b652235c	Update arch/Kconfig Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>	2021-12-21 03:26:16 -06:00
Juha Niskanen	422ceec99b	Fix typos in comments and Kconfig files Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-12-21 03:26:16 -06:00
chao.an	287348475c	sim/usrsock: increase the sim usrsock buffer size 1. Increase the sim usrsock buffer size: arch/sim/src/sim/up_usrsock.c 2. Fix build break arch/sim/src/sim/up_usrsock_host.c Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-21 00:53:31 -06:00
Simon Filgis	6cc48ff6ff	arch/arm/samv7: initial support for LIN bus communication Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-20 18:23:05 -03:00
Petro Karashchenko	3e76c3266e	assert: unify stack and register dump across platforms Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-20 00:02:12 -03:00
Petro Karashchenko	67d8a82393	Kconfig: fix non-string default values uniformity Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-20 00:10:57 +01:00
David Sidrane	e269b5fa28	Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working." This reverts commit `0aecfe8691`.	2021-12-19 01:40:35 -06:00
chao.an	c1c1882783	sim/usrsock: Reuse all addresses to avoid bind fail Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-18 13:15:46 -06:00
raiden00pl	87a8b1bed9	nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832	2021-12-18 12:27:59 -06:00
raiden00pl	f3fdd5a019	arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice	2021-12-18 09:13:36 -06:00
raiden00pl	a6c64795f4	arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected	2021-12-18 09:13:36 -06:00
raiden00pl	cf2dae8d79	arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes	2021-12-17 12:35:17 -06:00
raiden00pl	af143c96fc	arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support	2021-12-17 12:35:17 -06:00
raiden00pl	c7f6ac63b0	arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device	2021-12-17 12:35:17 -06:00
raiden00pl	23ef3ea64c	arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines	2021-12-17 12:35:17 -06:00
raiden00pl	26951f5018	arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex	2021-12-17 12:35:17 -06:00
raiden00pl	07c9204fd6	arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset	2021-12-17 12:35:17 -06:00
raiden00pl	ab66800e13	arch/arm/src/nrf52/Kconfig: fix typos	2021-12-17 12:35:17 -06:00
raiden00pl	ba6e8696b2	arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types	2021-12-17 12:35:17 -06:00
Jiuzhu Dong	5a22d33475	up_putc: do up_putc when enable CONFIG_ARCH_LOWPUTC Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-12-17 11:43:08 -06:00
raiden00pl	07d295b8db	add 5-Clause Nordic License barrier for Nordic SoftDevice Controller	2021-12-17 11:22:39 -06:00
xiewenxiang	b1d051b651	riscv/esp32c3: Initialize the BLE Mac	2021-12-16 22:31:02 -03:00
Gerson Fernando Budke	2dd5578d50	arch/arm/src/samv7/Kconfig: Define mem sizes Current samv7 platform does not define SoC memories sizes. This define both internal flash and sram memories sizes and update all defconfig files. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>	2021-12-16 06:56:42 -03:00
Alexander Lunev	0aecfe8691	stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working.	2021-12-16 01:28:05 -06:00
chao.an	b11833cbba	arch/assert: flush the syslog before stack dump flush the syslog before stack dump to avoid buffer overwrite Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-15 12:00:35 -06:00
chao.an	56ef1419dd	arch/xtensa: set the current reg before print syslog ensure the semantics of the up_interrupt_context() works as expected Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-14 21:40:03 -06:00
chao.an	2fe06ac083	arch: xtensa: save current SP before overwrting Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-14 21:40:03 -06:00
chao.an	93b133fe66	arch/xtensa: correct the interrupt stack on irq handler Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-14 21:40:03 -06:00
Petro Karashchenko	51a2db6ffc	Kconfig: improve uniformity Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-14 07:32:48 -06:00
Jiuzhu Dong	6b5a7a73ba	sim: add CONFIG_SIM_STACKSIZE_ADJUSTMENT to reduce variability between sim and other different platform stack size setting Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-12-13 21:15:30 -06:00
Petro Karashchenko	af614ac77d	tls: restore C89 compatibility for TLS Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-12-13 21:14:53 -06:00
chao.an	c2fd66bfab	arch/arm/risc-v/xtensa: add support of all symbols for debugging Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-13 08:31:13 -06:00
Abdelatif Guettouche	d31a0d8aca	arch/xtensa/esp32: Show CPU activity on IDLE task and on interrupts. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-13 08:30:58 -06:00
Abdelatif Guettouche	6262f7e99a	esp32_idle.c: Change private function's name to start with esp32_ instead of up_. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-13 08:30:58 -06:00
chao.an	89e2f00dad	arch/assert: fix the stack dump overflow [ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4 [ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init [ EMERG] backtrace\|10: 0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168 [ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff [ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8 [ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8 [ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6 [ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004 Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-13 01:43:18 -06:00
chao.an	0b7b8d274f	arm/cortex-m: enhance the crash dump 1. add irq stack information to list 2. add cpu loading into list before: Idle Task: PID=0 PRI=0 Stack Used=512 of 3048 hpwork: PID=1 PRI=224 Stack Used=304 of 2016 lpwork: PID=2 PRI=100 Stack Used=304 of 2016 rptun: PID=4 PRI=224 Stack Used=856 of 2008 after: [ EMERG] [ap] up_showtasks: PID PRI USED STACK FILLED CPU COMMAND [ EMERG] [ap] up_showtasks: ---- ---- 928 2048 45.3% ---- irq [ EMERG] [ap] up_dump_task: 0 0 512 3048 16.7% 99.4% Idle Task [ EMERG] [ap] up_dump_task: 1 224 304 2016 15.0% 0.0% hpwork [ EMERG] [ap] up_dump_task: 2 100 304 2016 15.0% 0.0% lpwork [ EMERG] [ap] up_dump_task: 4 224 856 2008 42.6% 0.0% rptun Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-12 21:40:29 -06:00
lupyuen	2a87b37a69	riscv/bl602: Swap SPI MISO and MOSI	2021-12-12 20:40:49 -06:00
Huang Qi	8ce3337e85	arch/risc-v: Implement TLS support Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-12 10:19:00 -06:00
Matheus Castello	294694bb2f	arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040 Use the common atomic operations when needed. Signed-off-by: Matheus Castello <matheus@castello.eng.br>	2021-12-11 11:32:17 -06:00
Juha Niskanen	a35d205f3b	arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-12-10 12:30:26 -06:00
Daniel Agar	efc949bceb	arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3	2021-12-09 21:30:41 -06:00
chao.an	3d75c25737	cortex-m/hardfault: enhance the dump information of mem/hard-fault Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 11:42:21 -06:00
chao.an	66e604b40e	cortex-m/hardfault: add usage-fault handler Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 11:42:21 -06:00
chao.an	2f449245cc	cortex-m/hardfault: add bus-fault handler Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 11:42:21 -06:00
chao.an	99fa58c871	arm/cortex-m23: armv8-m baseline do not support mem-fault Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 05:36:00 -06:00
chao.an	3e812dd88c	cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 04:30:06 -06:00
Xiang Xiao	6357523892	arch: Add _wchar_t typedef like other basic types Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-09 16:57:23 +09:00
chao.an	9b502dca05	arm/backtrace: disable the sanitize address check Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 01:05:46 -06:00
chao.an	7a61588b00	cortex-m/backtrace: remove the push process to simplify backtrace Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 01:05:46 -06:00
chao.an	437c81f8d0	cortex-m/assert: dump all registers with alias Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-09 00:16:04 -06:00
Michal Lenc	ae57492189	samv7: enable MCAN driver support for both rev A and rev B This commit enables the MCAN driver to function with both rev A and rev B version of the chip. The version of the chip is selected automtically from SAM_CHIPID_CIDR register so there is no need to predefined it in the configuration. The functonality was tested on rev B version of the chip. The rev A was not tested since I do not have the functional board but the code remains the same as in the previous NuttX version so it should not cause any additional troubles. The code is co-authored by Miloš Pokorný who wrote the initial transition to rev B of the chip. Signed-off-by: Michal Lenc <michallenc@seznam.cz> Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>	2021-12-07 23:36:11 -06:00
Huang Qi	58e0781e2e	arch/arm: Implement TLS support Signed-off-by: Huang Qi <no1wudi@qq.com>	2021-12-07 23:31:41 -06:00
Masayuki Ishikawa	bec9058b4c	arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c Summary: - This commit replaces the critical section with spinlock - The logic is the same as cxd56_serial.c Impact: - None Testing: - Tested with lc823450-xgevk:bt Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-12-07 23:28:54 -06:00
Huang Qi	63ab2f4308	arch/risc-v: Introduce basic support for qemu rv32 Signed-off-by: Huang Qi <huangqi3@xiaomi.com>	2021-12-07 23:28:33 -06:00
raiden00pl	54e3b148e9	arch/sim/src/sim/up_assert.c: fix implicit declaration warning	2021-12-07 07:51:44 -06:00
anjiahao	9d6c92f0fa	arch:move debug.h form headfile to c file Signed-off-by: anjiahao <anjiahao@xiaomi.com>	2021-12-07 04:01:27 -08:00
fenghang	c39ef4420e	1.phyplus update files to accord with the requirement of chcekpatch.sh 2.fix some files to fix compile warning 3.remove blueteeth header files, which are not used in nuttx core. 4.fix configs and add lost files 5.update defconfig, remove useless items 6.fix compile warning for nuttx phyplus 7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder 8.fix file format check error on phyplus source code 9.fix phyplus kconfig param error 10.update configure file for nuttx	2021-12-07 01:37:29 -06:00
fenghang	073c9880a3	phyplus first submit	2021-12-07 01:37:29 -06:00
chao.an	437a30d117	arch/tcbinfo: fix build break if task name disabled Signed-off-by: chao.an <anchao@xiaomi.com>	2021-12-06 00:47:58 -06:00
Dong Heng	698f1f76ff	risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash This can fix BLE assert when erase SPI Flash.	2021-12-06 13:13:11 +09:00
Xiang Xiao	a0990ee416	arch: Remove the duplicated up_tls_info implementation Define up_tls_info in arch/arch.h directly if the general one isn't suitable Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-05 20:59:53 -06:00
Xiang Xiao	19e5ee6ce0	arch: Remove FILE dump code from _up_dumponexit since the kernel build can't access the userspace memory inside other process directly Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-06 11:23:58 +09:00
Abdelatif Guettouche	50d217a9e8	esp32_cpustart.c: Improve comments around the usage of the inter-cpu startup handshake. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-02 11:21:49 -06:00
Abdelatif Guettouche	b34951e3a0	esp32_cpustart.c: Remove the CONFIG_SMP condition on some part of code because the whole file is only built if CONFIG_SMP is enabled. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-12-02 11:21:49 -06:00
Xiang Xiao	b65c7c26cf	arch: Dump task name through tcb_s::name instead of argv[0] since argv is defined in task_tcb_s not tcb_s Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-12-01 16:04:15 +01:00
Gerson Fernando Budke	c3307fce6b	arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config The Atmel samv7 implements progmem functionality. However, there is missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>	2021-11-29 21:31:08 -06:00
Petro Karashchenko	31809724e1	boards/same70-xplained: disable systick before loading MCUboot application Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-11-28 20:33:53 -06:00
Petro Karashchenko	fae27cc945	arch/samv7: fix unaligned address write for progmem interface Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-11-28 11:04:28 -06:00
Michal Lenc	ce53ea5da6	arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC) can now be triggered by Timer/counter at chosen frewuency and samples can be transfered via DMA with configurable number of samples. Timer/counter trigger is now set as a default option with the possibility to change it to software generated trigger. DMA is inspired by SAMA5 driver and also uses ping pong buffers. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-11-27 06:17:45 -06:00
Michal Lenc	6f2e23ad0c	arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors Just a minor change fixing some compile warnings and errros, does not have any impact on functionality. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-11-27 06:17:45 -06:00
Abdelatif Guettouche	251b8a3445	esp32xx_rtc: Include "clock/clock.h" to have a declaration of g_basetime. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-26 15:23:47 -03:00
Abdelatif Guettouche	af11cf6cd1	esp32xx_rtc.c: Fix a duplicated assignment. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-26 15:23:47 -03:00
Dong Heng	66023da10c	risc-v/esp32c3: Refactor ADC calibration Use calibration parameters from efuse rather than self-calibration.	2021-11-26 15:23:24 -03:00
Petro Karashchenko	0d9425676d	arch/arm/src/samv7: add flash progmem erasestate ioctl support Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-11-26 14:55:34 -03:00
Petro Karashchenko	134b2e6ec9	arch/arm/include/samv7: fix typo in samv7 irq header files Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-11-26 14:55:34 -03:00
Petro Karashchenko	dd647d200e	arch/samv7/sam_progmem: fix page size flash writing Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>	2021-11-26 08:47:08 -06:00
Xiang Xiao	e30a5f3790	arch/sim: Add new option to enable arch specific hostfs we have many different hostfs implementation now, so it's better to select the implementation explicitly, just like what we have done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS). Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-11-25 14:42:23 +01:00
zhuyanlin	1b3005accf	arch:cache_invalidate: fix unalign cacheline invalidate Only invalidate may corrupt data in unalign start and end. Use writeback and invalidate instead. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-24 22:48:13 -06:00
zhuyanlin	4db5016d83	arch:hostfs: add cache coherence config for semihosting option N/A Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-24 22:48:13 -06:00
David Sidrane	ad7e36d83f	stm32f7:sdmmc defer invalidate until after DMA completion The FAT was not coherent. Resulting in a write failed with errno:28 No space left on device. It is unclear how the memory is acesses prior to the DMA completion. But this restructuring ensures the data is coherent. This issue was not detected on the stm32h7	2021-11-24 20:38:23 -06:00
Jani Paalijarvi	4dfd3c9160	arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs Make it possible to override SPI CS function in board logic Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-11-24 06:50:32 -06:00
Lee Lup Yuen	6e68d55f8a	Fix GPIO output	2021-11-24 06:48:50 -06:00
chao.an	7cbb8da692	binfmt/elf: add bare metal coredump support Signed-off-by: chao.an <anchao@xiaomi.com>	2021-11-23 20:48:00 -06:00
chao.an	0f76ff42eb	arch/sim: add arch elf define Signed-off-by: chao.an <anchao@xiaomi.com>	2021-11-23 20:34:56 +09:00
chao.an	4c76c356ef	arch/arm: add more arch elf define Signed-off-by: chao.an <anchao@xiaomi.com>	2021-11-23 20:34:56 +09:00
Abdelatif Guettouche	65db787eff	esp32_irq.c: Fix retrieving IRQ number and peripheral ID when it comes to GPIOs in SMP mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-22 11:41:10 -06:00
Xiang Xiao	a29ee19af4	driver/motor: Remove the unnecessary critical section operation Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-11-18 19:27:07 -06:00
Jani Paalijarvi	6dd4d5de15	risc-v/mpfs: Add support for Aries M100PFSMVP board - Add defconfig and board specific files - Create mpfs/common for code which is shared between MPFS boards. - Add support for GPIO driven EMMCSD mux. - Move DDR Libero definitions from arch to boards. Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>	2021-11-18 10:59:44 -03:00
Xiang Xiao	a799835ec6	arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX since it work on the product device Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-11-17 08:59:14 -03:00
zhuyanlin	ffb543d061	xtensa: add setjmp.h include file N/A Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-17 02:23:45 -06:00
zhuyanlin	0e002af323	xtensa_backtrace: fix typ error N/A Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-17 01:47:26 -06:00
Andres Sanchez	064f6c8c55	add MTDIOCTL_PROGMEM_ERASESTATE support Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com> solve style check errors.	2021-11-16 14:45:03 -03:00
Eero Nurkkala	6db480a7f9	mpfs: emmcsd: boost waitresponse perf When waiting for a response to a sent command, the command complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee the completion of that particular command. There's no need to have some combinations skipping the check of the command complete bit. Thus, remove the 'waitbits' parameter as it's unnecessary. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-11-16 10:25:57 -06:00
Dong Heng	92eedd93a7	risc-v/esp32c3: Fix reset triggering crash nested when crash	2021-11-16 10:44:54 -03:00
Abdelatif Guettouche	5a41572fd0	esp32c3/esp32c3_usbserial.c: Initialize cpuint to ENOMEM, otherwise the first attempt to attaching an interrupt will trigger an assertion. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-15 12:11:45 -06:00
Alin Jerpelea	6deaba896d	arch: Haltian Ltd: update licenses to Apache Gregory Nutt has submitted the SGA Haltian Ltd has submitted the SGA Uros Platise has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-11-15 06:49:32 -06:00
Xiang Xiao	2262ddfa6d	arch: Remove fflush(stdout) from driver code it's wrong to call stdio function inside driver Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-11-15 00:04:12 +01:00
Abdelatif Guettouche	6cbcbd5481	arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig option doens't exist and we are not providing any external implementation. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-13 11:54:42 -03:00
Abdelatif Guettouche	a01cb867ce	esp32c3_rom.ld: Add some of the string.h functions to the linker script. These functions are strongly declared and thus will be used instead of any other implementation. Furthermore, necessary Kconfig options are selected to avoid building those function from NuttX's C library. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-13 11:54:42 -03:00
zhuyanlin	c6c534f27b	xtensa:mpu:use WRITEBACK attribute for intsram & extsram Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-13 05:59:10 -06:00
Dong Heng	fed7808d80	esp32 & esp32c3: Partition supports BIO cmd	2021-11-13 05:58:30 -06:00
anjiahao	edaa8a0ce9	fix sim_x11fb compile error Signed-off-by: anjiahao <anjiahao@xiaomi.com>	2021-11-13 05:58:01 -06:00
Dong Heng	f5c5d77744	risc-v/esp32c3: Add hardware brownout check and reset	2021-11-12 16:50:19 -03:00
Eero Nurkkala	876b39914b	mpfs: uart: add a way to configure uart3 and uart4 Currently configuring the uart3/4 as the serial console doesn't work. Apply proper changes in mpfs_config.h that enables the following configuration options: - CONFIG_UART3_SERIAL_CONSOLE - CONFIG_UART4_SERIAL_CONSOLE Also, fix a typo in mpfs_lowputc.c that gives a compile error if defined. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-11-11 06:02:27 -06:00
zhuyanlin	012bd1494c	arch:debug: add struct for task aware debug. When enable DEBUG_TCBINFO config, a global struct will provide, then debuggers can aware nuttx task infomation. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-10 14:31:10 -03:00
Juha Niskanen	201c67acbd	stm32l4 dfumode: enable for STM32L4+ chips	2021-11-10 11:18:37 -06:00
Alan C. Assis	b8c33e585e	esp32c3: Fix GPIO Output on pins 18 and 19 USB/JTAG	2021-11-09 20:54:34 -06:00
Abdelatif Guettouche	23039c92cf	esp32c3/Make.defs: Alawys build esp32c3_serial.c Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-09 09:22:57 -03:00
Abdelatif Guettouche	ebd94961c7	arch/riscv/esp32c3: Add the USB-Serial Driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-09 09:22:57 -03:00
Abdelatif Guettouche	17cf3edf46	arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG controller. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-09 09:22:57 -03:00
Dong Heng	a59aae6927	esp32/esp32c3: Fix MMU pages number calculation error	2021-11-07 21:59:54 -06:00
Michal Lenc	e0cef411e1	arch/arm/src/samv7: add support for AFEC (ADC) driver This commit adds microcontroller support for Analog Front End driver to samv7 MCUs. Only software trigger via IOCTL is currently supported, averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-11-07 21:04:56 -06:00
Yuichi Nakamura	3a0cd56623	rp2040: support I2C_RESET	2021-11-07 03:43:22 -08:00
Yuichi Nakamura	c109262a7f	rp2040: add rp2040_gpio_get_function_pin()	2021-11-07 03:43:22 -08:00
raiden00pl	7b595ab73a	arch/arm/stm32/stm32_qencoder: add support for Qenco index pin	2021-11-07 03:52:48 -06:00
zhuyanlin	5a4140f020	arch:xtensa: add setjmp xtensa function N/A Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-06 07:39:27 -05:00
zhuyanlin	580d17cc02	arch:xtensa: make xtensa_abi.h global include and usage N/A Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-11-06 07:39:27 -05:00
David Sidrane	4b96c28ed4	stm32h7:Support SPI SPI_DELAY_CONTROL	2021-11-06 05:14:05 -05:00
David Sidrane	040a04241e	drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays	2021-11-06 05:14:05 -05:00
Eero Nurkkala	f8832f7d86	mpfs: emmcsd: fix uninitialized value cppcheck reports the following: arch/risc-v/src/mpfs/mpfs_emmcsd.c:2375:22: error: Uninitialized variable: waitbits [uninitvar] while (!(status & (waitbits \| MPFS_EMMCSD_SRS12_EINT)) The finding is positive and this patch initializes it to zero properly. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-11-05 11:47:49 +01:00
David Sidrane	c077361a8a	imxrt:usb Fix EP type allocation	2021-11-04 13:23:25 -05:00
David Sidrane	95f7f4b9e6	imxrt:usb DMA cache aligned Buffers for Endpoints	2021-11-04 13:23:25 -05:00
David Sidrane	bd2bc1e351	imxrt:usbdev Clean up cache maintainence	2021-11-04 13:23:25 -05:00
David Sidrane	c3d10ad0aa	imxrt:usbdev formatting cleanup	2021-11-04 13:23:25 -05:00
David Sidrane	532635129c	imxrt:usdhc add proper support for dcache (wb)	2021-11-04 13:23:25 -05:00
David Sidrane	5022244339	imxrt mpuinit:Set Data and Code Type to Normal Strongly-Ordered requires aligned access unless caching is enabled. Normal memory Accesses to normal memory region are idempotent... - unaligned accesses can be supported	2021-11-04 13:23:25 -05:00
David Sidrane	34c3efcb91	imxrt mpuinit:Remove duplicate entry for ITCM (0x0)	2021-11-04 13:23:25 -05:00
David Sidrane	08d0434bad	imxrt:mpu init handle dcache setting in MPU config With CONFIG_ARMV7M_DCACHE the cache maintenance operation are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is on then buffering operations are no-ops. This change enables MPU_RASR_C and MPU_RASR_B if CONFIG_ARMV7M_DCACHE is only set. if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only MPU_RASR_C is enabled. N.B When caching is disalbed unaligned access may cause hard faults so add -mno-unaligned-access It is always safe to enable Buffering in FLASH to achive unaligned access leniency, as it is not written to.	2021-11-04 13:23:25 -05:00
ChenWen	440787c0c1	risc-v/esp32c3: Fix Wi-Fi & BLE coexist issue 1. Wi-Fi and BLE use common PHY functions. 2. Fix Wi-Fi & BLE coexist adapter error. 3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.	2021-11-04 11:02:05 -03:00
ChenWen	65d7f4bfb3	riscv/esp32c3: Support more country codes	2021-11-04 11:02:05 -03:00
ChenWen	4fc2f6e28c	riscv/esp32c3: Support debug log configuration for Wi-Fi library	2021-11-04 11:02:05 -03:00
ChenWen	02968cc124	risc-v/esp32c3: Improve Wi-Fi connection success rate	2021-11-04 11:02:05 -03:00
ChenWen	222ec556d5	riscv/esp32c3: Fix some Wi-Fi issues 1. Fix the issue that Wi-Fi can't connect to some special routers occasionally. 2. Support Wi-Fi 12/13 channel active scanning by default. 3. Update Wi-Fi driver code to fix issue of failure to send pkt. 4. Replace software random with hardware random 5. Fix Wi-Fi mode start error	2021-11-04 11:02:05 -03:00
chenwen	33031a2813	riscv/esp32c3: Fix the issue of Wi-Fi automatic disconnection	2021-11-04 11:02:05 -03:00
chenwen	afbad5ca9d	riscv/esp32c3: Clear station configuration when connection fails or disconnect	2021-11-04 11:02:05 -03:00
Eero Nurkkala	8e43f39141	mpfs: cache: provide L1/L2 cache enablers E51 may configure the L1 and L2 caches. Once configured, no reconfiguration is possible after hardware reset is issued. L2 is 16-way set associative with write-back policy. The size 2 MB, from which 1 MB is utilized with the values provided here. That's a total of 8 ways. The rest of the L2 is left out for the bootloader usage. mpfs_enable_cache() first checks the bootloader usage doesn't overlap with the cache itself, thus providing a set of functional values. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-11-04 11:00:55 -03:00
Alexander Lunev	60de445ab3	stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.	2021-11-03 22:50:14 -05:00
Xiang Xiao	3e967f784e	sim: Split SIM_SANITIZE to SIM_ASAN and SIM_UBSAN align the naming style with MM_ASAN Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-11-02 21:02:43 +01:00
mage1	c82a676630	sim: fix sim runtime err under sanitize check mode. since gcc sanitize can not stub proper code in nuttx kernel code.	2021-11-02 21:02:43 +01:00
Jani Paalijarvi	a16a9f80e2	mpfs: i2c: Add support for adaptive I2C bus frequency Select the closest possible frequency which is smaller than or equal to requested in I2C msg	2021-11-02 04:10:08 -05:00
ligd	2f4662c513	arch/arm: Remove -mcpu for fix warning warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8-m.main' switch Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-11-01 21:28:10 -05:00
ligd	8417b4726b	Revert "arch/armv8-m: use -mfpu=auto based on -mcpu=cortex-m55" This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d. Revert "arch/arm: Remove -march and -mtune" This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.	2021-11-01 21:28:10 -05:00
Abdelatif Guettouche	860370284e	esp32c3_dma: Remove the DMA test included in the driver along with its defconfig. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-01 13:49:59 -05:00
Alexander Vasiljev	aeb1d3098d	stm32h7/dmamux: correct bit fields	2021-11-01 14:40:33 -03:00
Abdelatif Guettouche	73f15ed544	esp32/Kconfig: Make ESP32_BT_RESERVE_DRAM default to 0 again if Bluetooth is not enabled. When Bluetooth is enbaled then it defaults to 64KB. This will not wast those 64KB of memory when Bluetooth is not enabled. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-11-01 10:01:38 -05:00
Alexander Lunev	33d236121f	stm32h7 sdmmc: added missing sdio_set_sdio_card_isr() function to initialize SDIO in-band interrupt logic	2021-10-31 22:26:13 -05:00
Xiang Xiao	b58379b738	arch/arm: Add l suffix for INT32_C macro since int32_t typedef to signed long Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-10-31 12:56:41 -03:00
Michal Lenc	a64903acc7	samv7: adds support for QSPI driver in SPI Mode This commit adds new files that support functionality of QSPI driver in SPI Master Mode. This functionality is included in new files sam_qspi_spi.x to avoid too much mess in the source code. QSPI in SPI mode can be turn on by config option SAMV7_QSPI_SPI_MODE. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-10-30 01:24:31 -05:00
yinshengkai	ee17ae5ba1	tool: add code coverage tool	2021-10-29 19:21:23 +02:00
raiden00pl	bb5e3fee44	arch/arm/src/stm32/stm32_foc.c: define missing FOC1_PWM_FZ_BIT for G4	2021-10-29 07:49:59 -05:00
raiden00pl	8e9e54cad3	arch/arm/src/stm32/hardware/stm32_dbgmcu.h: fix invalid STM32_DBGMCU_APB2_FZ offset for G4	2021-10-29 07:49:59 -05:00
Alexander Vasiljev	35e93644cf	stm32h7: add low power timers	2021-10-27 10:37:05 -05:00
Jiuzhu Dong	1ed4118378	power/battery: add baterr, batinfo, batwarn for debug log Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>	2021-10-26 13:59:42 -03:00
chao.an	b90d094138	arch/sim: add native socket support based on usrsock Signed-off-by: chao.an <anchao@xiaomi.com>	2021-10-26 08:01:50 -05:00
Gustavo Henrique Nihei	de0e4d4aac	xtensa/esp32s2: Rename MTD-related configs to become more intuitive Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei	06bb85d8a5	risc-v/esp32c3: Rename MTD-related configs to become more intuitive Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei	fb00ab3242	xtensa/esp32: Rename MTD-related configs to become more intuitive Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei	eb889b0884	xtensa/esp32s2: Enable Partition Table allocation at custom offset Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei	eb7ffd014e	risc-v/esp32c3: Enable Partition Table allocation at custom offset Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei	211f899b62	risc-v/esp32c3: Refactor and reorganize Partition Table related configs Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei	9d7b9821b3	xtensa/esp32: Enable Partition Table allocation at custom offset Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei	b555b3f89e	xtensa/esp32: Refactor and reorganize Partition Table related configs Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei	793266d39e	espressif: Fix spacing style in Kconfig files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei	4ff754827c	espressif: Fix prompt string of Wi-Fi FS mount point configs Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei	a1af605973	espressif: Fix references to Wi-Fi according to Wi-Fi Alliance Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-25 08:01:44 -05:00
Alan C. Assis	7e8003cba1	Move chip specific file compilation to CHIP_CSRCS	2021-10-23 04:03:12 -05:00
Alan C. Assis	03738622a1	esp32s2: Add RNG driver support and board profile example	2021-10-23 04:03:12 -05:00
David Sidrane	e1a0a1188e	stm32h7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET	2021-10-23 03:58:26 -05:00
David Sidrane	e66423229a	stm32f7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET	2021-10-23 03:58:26 -05:00
David Sidrane	fd2c1cb216	stm32:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET	2021-10-23 03:58:26 -05:00
David Sidrane	9d8f7126f6	armv7-m,armv7-r,armv8-m:MPU Add mpu_reset and ARM_MPU_EARLY_RESET When NuttX is booted from a foreign (non NuttX) bootloader. There as a possibility that the bootloader configured the MPU, in an incompatible way for the NuttX memory usage. The option to reset the MPU before it is initialized may not succeed if the bss and data initialization code violated the previous MPU configurations. Added herein are ARM_MPU_RESET and ARM_MPU_EARLY_RESET. The former can be used If the system is capable of booting and running NuttX MPU configuration code without an MPU violation. The latter is used if the system can not run the bss and data initialization code. These are options so that a NuttX may be configured to not clobber a bootloader MPU configuration in a system that is architected to share the MPU configuration task.	2021-10-23 03:58:26 -05:00
zhuyanlin	cf1a04d0a2	xtensa:cache: add lock & unlock feature Since some xtensa cores cache support lock & unlock feature. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-10-22 13:31:32 -03:00
zhuyanlin	b4ea11f7b1	arch:cache: add lock feature for cache Some architectures support lock & unlock cache feature. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-10-22 13:31:32 -03:00
David Sidrane	90cfa6f313	imxrt:syslog is dependant on arm_lowputc	2021-10-22 10:07:20 -05:00
oreh-a	3c1ac89557	Fixed line length	2021-10-22 09:03:14 -05:00
Alexander Oryshchenko	ed392abb83	Added ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG option to stm32f0/g0/l0 chip configiuration	2021-10-22 09:03:14 -05:00
Eero Nurkkala	e57f3f7a3a	mpfs: emmcsd: provide proper internal emmc settings So far the SD-card functionality has been tested with the driver. Now, also the internal eMMC has been tested working with this patch. This patch applies IOMUX and clock settings that have been tested working with the internal eMMC in the Polarfire Icicle kit. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-10-21 22:41:08 -05:00
Eero Nurkkala	c34b9620db	mpfs: clockconfig: add clock initialiation sequence Add clock initialization sequence especially for systems containing no bootloader. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-10-21 22:40:26 -05:00
Eero Nurkkala	bc72ccdf6a	mpfs: Kconfig/Make: add DDR support flag This adds the proper flag for introducing the DDR support. Also call the mpfs_ddr_init() at the proper location. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-10-21 22:40:26 -05:00
Eero Nurkkala	3b330089d5	mpfs: ddr: add DDR training This adds DDR training. The training has a small chance of failing, and then the training is restarted. DDR training cannot be done meaningfully while the software is in DDR. If the system is intended to run from eNVM, like a bootloader, the linker script should be tuned to utilize the envm region as follows: envm (rx) : ORIGIN = 0x20220100, LENGTH = 128K - 256 l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k 256 bytes are reserved for the system; The fixed block may be installed from the 'hart-software-services' -repository: https://github.com/polarfire-soc/hart-software-services.git For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin may be prepended on the nuttx bootloader image in the following manner: cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin cat nuttx.bin >> nuttx_bootloader.bin riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma *+0x20220000 nuttx_bootloader.bin flashable_image.hex This provides an image 'flashable_image.hex' that may be flashed on the eNVM region via Microsemi Libero tool. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-10-21 22:40:26 -05:00
Jukka Laitinen	c5b11f42b6	mpfs_head.S: Support for booting on different harts and from eNVM - Fix the FPU enabling code - If booting from eNVM, all harts start booting. With CONFIG_MPFS_BOOTLOADER, one can allow just one hart booting and rest are stuck in wfi. - Check that mtvec is actually updated before continuing the boot - Create 5 IRQ stacks, one for each hart Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-10-21 22:40:26 -05:00
Jukka Laitinen	37761c293d	mpfs_head.S: Fixes for booting on different harts - Jump to mpfs_start with mhartid in a0 as the comment says - Don't invalidate mmu tlb on e51 (it doesn't have mmu) - Fix FPU initialization flags on e54 (it fires IRQ5 and crashes) Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-10-21 22:40:26 -05:00
Jukka Laitinen	e5843db282	mpfs: Add configuration flags to configure NuttX booting on single hart The bootloader hart also configures the needed clocks and peripherals. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-10-21 22:40:26 -05:00
Eero Nurkkala	d909b0f635	mpfs: hardware/memorymap: add more base addresses Add a number of missing base addresses. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-10-21 22:40:26 -05:00
chao.an	bd7cb1aae5	sim/bluetooth: remove the WIRELESS_BLUETOOTH depends if native host is in use Signed-off-by: chao.an <anchao@xiaomi.com>	2021-10-21 11:24:46 -05:00
Abdelatif Guettouche	018aa8eb8d	esp32c3_serial.c: Remove the stub implementations of the early serial functions as they are only called when the configuration is enabled. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-20 10:22:10 -03:00
Xiang Xiao	1efc9fbac6	sim/rptun: Trigger the callback only the sequnece number change Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-10-20 10:21:54 -03:00
Abdelatif Guettouche	c83c1071cc	esp32c3_bignum.c & esp32c3_sha.c: Fix some trivial nxstyle complaints. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	e424241d09	arch/risc-v/esp32c3: Remove the bignum test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	91cb9dafaf	arch/risc-v/esp32c3: Remove the RSA test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	652d77efd2	arch/risc-v/esp32c3: Remove the SHA test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	5d1c01aea7	arch/risc-v/esp32c3: Remove the AES test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
Abdelatif Guettouche	8288a04a0b	arch/xtensa/esp32: Remove the AES test from the driver. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-19 18:41:57 -03:00
zhuyanlin	b5134565fa	arch:xtens:mpu: modify acc and memtype to uint32_t The uint8_t and uint16_t will overflow in MPU_ENTRY_AR marco. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-10-19 00:24:31 -05:00
Xiang Xiao	91398e73eb	arch/xtensa/Kconfig: add quotes in source to clean warnings from setconfig Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-10-19 00:33:51 +02:00
Michal Lenc	3e1ce5f770	arch/arm/src/imxrt/hardware: add header file for ADC_ETC module This commit adds header file imxrt_adc_etc.h for external ADC trigger module. This contains only definitions of ADC_ETC registers and separate bits, implementation of ADC_ETC driver is yet to be done. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-10-17 16:50:59 +02:00
Abdelatif Guettouche	7549de49b4	arch/*_cpupause:Allow a spin before taking the g_cpu_wait spinlock. If we repeatedly call up_cpu_pause and up_cpu_resume, there would be cases where the next call to up_cpu_pause happens while the other CPU is still responding to the previous resume request. In this case the DEBUGASSERT will trigger. We should allow the first CPU to wait until the other CPU has finished responding to the resume request. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-17 21:10:23 +09:00
Abdelatif Guettouche	7b43d11435	esp32_spiflash.c: Allocate only one variable to hold the cache state in single CPU mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	f54a929001	esp32_spiflash.c: Keep the index of the other CPU between SPI Flash operations. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	eeb68bda3d	xtensa_testset.c: Simplify the test-set function and remove some old comments. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	dfe1637864	esp32_spiflash.c: Pause the other CPU during flash operation. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	f2c2323642	esp32_intercpu_interrupt.c: Force the functions to internal SRAM. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 22:56:21 -07:00
Abdelatif Guettouche	d2bc011719	arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait spinlock. If we repeatedly call up_cpu_pause and up_cpu_resume, there would be cases where the next call to up_cpu_pause happens while the other CPU is still responding to the previous resume request. In this case the DEBUGASSERT will trigger. We should allow the first CPU to wait until the other CPU has finished responding to the resume request. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 09:46:23 -07:00
Abdelatif Guettouche	591c1563b8	esp32_oneshot_lowerhalf.c: Use the same alignment as the rest of the code base. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	9e1d2ca95e	esp32_rt_timer.c: Group static variables into a struct and fix naming standard Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0dff3f2762	esp32_wifi_adapter.c: Use the specified spin lock when enabling/disabling interrupts. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	a50d673df7	esp32_wifi_adapter.c: Don't hold another spinlock when calling enter_critical_section, we already hold the global IRQ spinlock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	11216257cf	esp32_rt_timer.c: Don't nest calls to spin_lock_irqsave with a device specific spinlock, this will lead to deadlocks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	e847c61801	esp32_wifi_adapter.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	32f7471f9e	esp32_wlan.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	4ae1285124	esp32_emac.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	e64390d5e9	esp32_rt_timer.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	c61009c2cf	esp32/esp32_spi_slave.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	2273684cb1	esp32/esp32_spi.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0123243f9a	esp32/esp32_i2c.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	0af9a49d9c	esp32/esp32_oneshot_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	698af43d78	esp32/esp32_freerun.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	04bd27400a	xtensa/esp32_wdt_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Abdelatif Guettouche	19a096cdfe	arch/xtensa/esp32_tim_lowerhalf.c: Use device specific locks. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei	ff705586bb	xtensa/esp32s2: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	4d5e0f8fe1	xtensa/esp32: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	99ac065d0a	risc-v/esp32c3: Provide SPI Flash parameters to MCUboot build Also unify bootloader config creation to reduce duplication. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	cc78541966	risc-v/esp32c3: Add esp-nuttx-bootloader folder to gitignore list Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Gustavo Henrique Nihei	ae25ebce4c	risc-v/esp32c3: Fix wrong arch in the path to chip folder Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-15 23:55:10 -07:00
Abdelatif Guettouche	a7d8d9dd98	esp32s2/tie.h: Run the file though detab. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	6d246eb18f	esp32s2/tie.h: The old tie.h file was from ESP32 which doesn't apply to ESP32-S2. This commit gets the correct S2 tie.h file Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	217fd97fd3	xtensa_coproc.S: Correctly save/restore coprocessor0 state. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 07:39:54 -03:00
Abdelatif Guettouche	7420f245bc	xtensa_context.S: Save and restore SCOMPARE1 when necessary. SCOMPARE1 is used by some atomic instructions and need to be preserved during a context switch. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-10-14 06:32:17 -03:00
Alin Jerpelea	b9986ca016	arch: arm: update licenses to Apache Gregory Nutt is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-10-11 10:13:07 +02:00
jsun	c58fddb915	Open ble controller adaptation code N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-10-08 02:30:27 -07:00
Jari van Ewijk	e4752fbaee	S32K1xx arch: Add (optional) support for SPI native/hardware chip select	2021-10-05 06:07:18 -07:00
Gustavo Henrique Nihei	47e804b167	risc-v/esp32c3: Make BLE adapter code compliant to nxstyle Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-10-05 08:45:40 -03:00
Alan C. Assis	867c6d0636	esp32: Add initial support to Bluetooth Low Energy Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com> Co-authored-by: Gustavo Henrique Nihei <gustavonihei@gmail.com>	2021-10-04 15:10:37 -03:00
Abdelatif Guettouche	d22b4ec539	espxx_rng.c: Add "/" at the beginning of paths for consistency. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	c811cefa2d	esp32c3_rng.c: Remove unused functions. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	5c6a30c00b	esp32_rng.c: Remove the initialization guard. The init function is called only once during startup. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
Abdelatif Guettouche	6a262c5203	esp32_rng.c: Remove unused functions. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-30 13:50:25 -03:00
liuhuan	ee6138e9ba	power: Open CONFIG_PM compilation failed include debug.h Signed-off-by: liuhuan <liuhuan16@xiaomi.com>	2021-09-30 07:16:07 -07:00
Jari van Ewijk	cf6dcbc6fd	S32K1XX arch: gpioread may also be used for output pins	2021-09-30 04:30:50 -07:00
Xiang Xiao	77bc1d1bdf	power/battery: Move the enumurate to the common place so the userspace program can handle the different battery driver equally Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-30 14:58:42 +09:00
P.Brier	b9d1fcb232	Use ethernet MAC programmed in imxrt OCOTP MAC0/MAC1 (teemsy board has this)	2021-09-29 20:45:14 -07:00
Sara Souza	8a142f474e	xtensa/esp32-s2/rttimer: Disable alarm before setting a new value and enabling it	2021-09-28 21:02:57 -03:00
Sara Souza	33f2d46bff	risc-v/esp32-c3/rttimer: Disable alarm before setting a new value and enabling it	2021-09-28 21:02:57 -03:00
Alin Jerpelea	15a37c5a5a	arch: Omni Hoverboards: update licenses to Apache Gregory Nutt has submitted the SGA Omni Hoverboards has submitted the SGA David Sidrane has submitted the ICLA Mateusz Szafoni has submitted the ICLA Sebastien Lorquet has submitted the ICLA Paul Alexander Patience has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-28 04:37:38 -07:00
Gustavo Henrique Nihei	20341e6f17	risc-v/esp32c3: Enable support for "make bootloader" target This enables the provisioning of the bootloader binaries through the build system. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei	3c63cb522c	risc-v/esp32c3: Enable booting from MCUboot bootloader Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei	a5f9e29d78	xtensa/esp32s2: Enable support for "make bootloader" target This enables the provisioning of the bootloader binaries through the build system. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:21:53 -07:00
Gustavo Henrique Nihei	800678ca78	xtensa/esp32s2: Enable booting from MCUboot bootloader Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-27 18:21:53 -07:00
Jari van Ewijk	62c41a723b	s32k1xx_eeeprom.c - fix compiler warnings	2021-09-27 06:02:59 -07:00
Abdelatif Guettouche	5336704c77	esp32_start.c: Initialize the SPI RAM before enabling its cache. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-27 05:13:51 -07:00
Gustavo Henrique Nihei	c23986ec63	xtensa/esp32: Select ARCH_HAVE_BOOTLOADER for ESP32 chips Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei	86518bdf25	tools: Trigger clean_bootloader on distclean for supported chips Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-24 10:48:19 -07:00
Gustavo Henrique Nihei	4ac3044cc3	xtensa/esp32: Enable build system to download or build bins from source Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-23 20:52:25 -07:00
Sara Souza	9c2c5d3919	risc-v/esp32-c3: fix pid initiatialization on esp32c3_rt_timer.c pid variable was initialized to -EINVAL to prevent rt_timer_deinit from delete an invalid kthread. But priv->pid was being overwritten in the rt_timer_init, so in case of failure to create a kthread, it would call rt_timer_deinit with a non expected initialization value.	2021-09-23 19:01:27 -07:00
Sara Souza	d0e7d7b77f	risc-v/esp32-c3: Remove _s of non static variables from esp32c3_rt_timer.c	2021-09-23 19:01:27 -07:00
Abdelatif Guettouche	f2f2040c44	esp32_spiram/psram/himem: Add and fix the files' sections. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Abdelatif Guettouche	3d8a6fb676	esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c file. This function is already defined in esp_himem and is used only when that file is built. We don't need another weak function. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Abdelatif Guettouche	2834d2a46f	esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-23 02:49:11 -07:00
Xiang Xiao	47c60b2de8	arch/arm: Remove -march and -mtune since -mcpu is enough https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58869 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-23 11:48:11 +02:00
Jari van Ewijk	bbb2f1f8c7	S32K1XX: Add LPI2C slave support	2021-09-22 19:36:34 -07:00
Sara Souza	962059f843	xtensa/esp32-s2: Adds oneshot device driver support	2021-09-22 22:53:54 -03:00
David Sidrane	6d299ce802	stm32h7:DMA_TRBUFF is DMA_SCR_TRBUFF	2021-09-22 22:48:10 -03:00
Sara Souza	fba6fa2dc1	xtensa/esp32-s2: Adds support to rt_timer and systimer to ESP32-S2.	2021-09-22 17:18:24 -03:00
Sara Souza	2cd4f4af79	xtensa/esp32-s2: Adds freerun timer wrapper	2021-09-22 09:38:10 -03:00
Gustavo Henrique Nihei	e651ef0969	arch/risc-v: Remove CODE qualifier for RISC-V-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	06f4ee850a	arch/risc-v: Remove FAR qualifier for RISC-V-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	e9c17c9332	risc-v/rv32m1: Fix wrong position for ++ operator on serial driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	eca1f86294	arch/xtensa: Remove CODE qualifier for Xtensa-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	e13dd7dab9	arch/xtensa: Remove FAR qualifier for Xtensa-specific files Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Gustavo Henrique Nihei	58f87ef443	xtensa/esp32: Fix wrong position for ++ operator on I2C driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-22 08:16:01 -03:00
Jari van Ewijk	e5f17f6604	S32K1XX: Add FlexIO registers	2021-09-22 03:15:42 -07:00
David Sidrane	a9ff808dd1	stm32xx:sdmmc/sdio remove redundant GPIO config The stm32_gpiosetevent calls stm32_configgpio. So the pin is infact restored to the SDMMC/SDIO D0. The seconday init, dropped interrupts in a debug build with HW stack checking on after the GPIO glich fixes and that was how it was detected.	2021-09-21 18:25:16 -07:00
David Sidrane	a8d5f21f81	stm32H7:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.	2021-09-21 18:25:16 -07:00
David Sidrane	5e19ebb818	stm32F7:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source.	2021-09-21 18:25:16 -07:00
David Sidrane	d5e306e6f3	stm32:Etablish device before enabling outputs This prevents gliches on changing to an output mode. If not the ALT mux can be selecting a IP block that is drving the line to say 0. Then the output is connected to that source, then swithced to the correct source. This produced a 430 nS glich on a F4 @168 Mhz. It was a enough to corrupt an I2C device with a bus monitor.	2021-09-21 18:25:16 -07:00
Sara Souza	fc12d6888b	risc-v/esp32-c3: Group static variables into a struct and prevent an unitialized thread to be deleted	2021-09-21 15:45:59 +02:00
P.Brier	35824b449a	Added CONFIG_ETH0_PHY_DP83825I to imxrt_enet: make driver compile for teensy 4.1 (link detection needs more checks to see if it works as expected)	2021-09-21 10:27:33 -03:00
P.Brier	f9850cf433	Fixed imxrt flexcan driver compilation error due to incorrect scope of variable	2021-09-21 10:00:12 -03:00
Abdelatif Guettouche	9f4d7e4767	xtensa_dumpstate.c: Fix the name of the TCB variable when dumping the backtrace. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-21 09:22:28 -03:00
Eero Nurkkala	812f504c16	mpfs: emmcsd: add Kconfig/Makefile and board files Add necessary Kconfig, Make.defs, Makefile and board file changes. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-09-18 12:18:09 -03:00
Eero Nurkkala	772432e7c3	mpfs: add emmcsd driver This adds the emmcsd driver for the Polarfire Icicle kit. The driver has been tested with several SD-cards, such as: - Kingston 32 GB SDS2 Canvas Select Plus - Kingston MicroSD Canvas Select Plus - Sandisk Extreme PRO 32 GB - Transcend 8 GB MicroSD The internal eMMC hasn't been tested comprehensively. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>	2021-09-18 12:18:09 -03:00
Xiang Xiao	75a119ac1c	arch: Compile up_puts in all Make.defs Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	71c61b11d9	arch/riscv: Rename riscv_puts to up_puts since it's a common API defined in include/nuttx/arch.h Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	0625f9888c	arch/z16: Implement up_puts function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
Xiang Xiao	5b75df2203	arch/sim: Implement up_puts function Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-18 07:33:44 -03:00
jsun	f4b6bb281c	Update bl602 MTU_SIZE and TX_BUF_SIZE N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-09-17 22:11:30 -05:00
jsun	d489392d08	Add bl602 os adapter layer N/A Signed-off-by: jsun <jsun@bouffalolab.com>	2021-09-17 22:11:30 -05:00
Abdelatif Guettouche	15b68b9abb	esp32_spiflash.c: Correctly disable APP's CPU cache. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-17 17:43:45 -03:00
Masayuki Ishikawa	204d88bcf3	arch: cxd56xx: Replace the critical section with spinlock in cxd56_serial.c Summary: - This commit replaces the critical section with spinlock in cxd56_serial.c Impact: - None Testing: - Tested with spresense:rndis_smp, spresense:rndis and spresense:rndis_wifi Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-09-16 21:56:40 -05:00
Alin Jerpelea	48f92e6f1d	author: Bill Gatliff : update licenses to Apache Gregory Nutt has submitted the SGA Bill Gatliff has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-16 21:56:08 -05:00
Gustavo Henrique Nihei	52cea558af	risc-v/esp32c3: Make the semaphore timeout on I2C configurable Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-16 14:07:26 -03:00
Gustavo Henrique Nihei	b33ccd01cf	xtensa/esp32: Make the semaphore timeout on I2C configurable Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-16 14:07:26 -03:00
zhuyanlin	7947e50f06	xtensa:backtrace: flush to stack when in interrupt The registers may be in window during interrupt. Flush window stack to stack first. And fix warning in build. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:53:35 -05:00
Peter Bee	2a8b076b38	risc-v/esp32c3: fix pwm driver bug Wrong offset sign and pwm multichan fix Signed-off-by: Peter Bee <bijunda1@xiaomi.com>	2021-09-16 08:38:49 -03:00
zhuyanlin	cdb441cc3f	arch:xtensa:dumpstate: use sched_dumpstack Use sched_dumpstack instead. The backtrace infomation like xtensa_user_panic: User Exception: EXCCAUSE=0009 task: hello xtensa_registerdump: PC: 202b32b8 PS: 00060030 xtensa_registerdump: A0: a02acb87 A1: 20998d10 A2: ffffaaaa A3: 12345678 xtensa_registerdump: A4: a02ba26c A5: 209949c0 A6: 20990994 A7: 00000258 xtensa_registerdump: A8: a02b32af A9: 20998cb0 A10: 0000000f A11: 209949a0 xtensa_registerdump: A12: a02be95c A13: 20994980 A14: 00000003 A15: 209949d0 xtensa_registerdump: SAR: 00000000 CAUSE: 00000009 VADDR: ffffaaaa xtensa_registerdump: LBEG: 00000000 LEND: 00000000 LCNT: 00000000 xtensa_registerdump: TMP0: 202b1512 TMP1: 20998af0 sched_dumpstack: [BackTrace\| 3\|0]: 0x202acbae 0x202b232e 0x202b1912 0x202b19f5 0x202b24f1 0x202b152f 0x40023 0x202b32b0 sched_dumpstack: [BackTrace\| 3\|1]: 0x202acb87 0x202a86a4 Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	6e0f84dc88	arch:xtensa: add up_backtrace support Up_backtrace can be backtrace from task or interrupt. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	3acdbef60d	xtensa:arch: force up_getsp to inline Up_getsp may be not inline in gcc, thus get the sp is up_getsp function's sp, not the caller function. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
zhuyanlin	583dce0b98	arch:xtensa: remove WSBITS/WBBITS to core.h Remove WSBITS/WBBITS macro to core.h as may be used by arch common code. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-16 10:32:38 +08:00
Cis van Mierlo	b316c679c1	S32K1xx: added PM support	2021-09-15 12:20:23 -03:00
SPRESENSE	74df4b70b3	drivers: video: Rearchitect video driver Rearchitect video driver: - Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s), and support them. - CISIF driver supports new video I/F struct imgdata_ops_s. - ISX012 driver supports new video I/F struct imgsensor_ops_s. - Move ISX012 driver to general driver directory.	2021-09-15 07:06:35 +02:00
Juha Niskanen	4487b352c0	arch/arm/src/stm32l4: fix baud rate setting for LPUART Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-14 08:57:25 -07:00
Harri Luhtala	7e3c813346	arch/arm/src/stm32l4: LPUART1 support Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>	2021-09-14 08:57:25 -07:00
Abdelatif Guettouche	198c30eaa6	stm32*7/stm32_serial.c: Don't fake an interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-14 22:50:43 +08:00
chao.an	ba9b829372	arch/arm: correct the function name from arm_getsp() to up_getsp() Signed-off-by: chao.an <anchao@xiaomi.com>	2021-09-14 22:48:47 +08:00
Cis van Mierlo	91c945a2e8	s32k1xx: added way to get the reset cause in proc fs	2021-09-14 08:35:41 +02:00
Sara Souza	83a9c2b24b	xtensa/irq.h: Fixes the routine that clears the processor interrupt	2021-09-13 17:01:49 -03:00
Alin Jerpelea	bb54ed4227	author: OffCode Ltd : update licenses to Apache OffCode Ltd has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-13 22:43:36 +08:00
zhuyanlin	8e6fbe700e	xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>	2021-09-13 14:38:57 +08:00
Xiang Xiao	850367d5bb	arch/arm: Add ARCH_CORTEXM55 Kconfig for cortex-m55 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-12 09:09:42 -03:00
Jukka Laitinen	3654db3517	mpfs: Modify IRQ handling to support also HART0 on PF Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-09-11 23:33:01 +08:00
Janne Rosberg	8b560e7894	mpfs/i2c: fix bus initialize for i2c1	2021-09-11 23:33:01 +08:00
Janne Rosberg	1e3919e55a	mpfs/corepwm: remove wrong header include	2021-09-11 23:33:01 +08:00
Janne Rosberg	7db3456824	risc-v/mpfs: serial: add termios support and init device clocks	2021-09-11 23:33:01 +08:00
Janne Rosberg	aa057e25f2	mpfs/i2c: adapt to sysreg define changes	2021-09-11 23:33:01 +08:00
Janne Rosberg	dc54ba924e	mpfs/spi: adapt to sysreg define changes	2021-09-11 23:33:01 +08:00
Janne Rosberg	3e6b19dfc5	risc-v/mpfs: add more sysreg defines and fix clock and reset defines	2021-09-11 23:33:01 +08:00
Abdelatif Guettouche	31aa616bf2	stm32_serial.c: Don't fake a TX interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-10 15:15:44 -07:00
David Sidrane	41e1696b27	stm32f4:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
David Sidrane	e488f0047d	stm32h7:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
David Sidrane	21f049b43a	stm32f7:USB otgdev Ensure proper EP state Repeated automated sercon, serdis on VBUS proved to fail for CDCACM DATA IN (device Serial TX). The root cause was that the EP was left active after disconnect. This resulted in the first serial write falling to kick-off the EP IN request. That should restart the EP ISR.	2021-09-09 14:27:41 -04:00
Sara Souza	acf18bd82d	risc-v/esp32-c3: refactor the Wi-Fi board logic. This commit moves the Wi-Fi initialization to Wi-Fi specific file and to spiflash initialization. It also reserves one partition for Wi-Fi use and for general use, and makes it possible to me mounted by several FS.	2021-09-09 20:14:04 +08:00
Sara Souza	11068fad1b	risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions	2021-09-09 20:14:04 +08:00
Harri Luhtala	d4e59b7e8d	arch/arm/src/stm32l4: add control for Vddio2 independent I/Os supply valid Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>	2021-09-09 08:26:08 -03:00
Abdelatif Guettouche	4ef859924b	esp32_serial.c: Release the spinlock before calling uart_xmitchars, this functions will call esp32_txint again which leads to deadlock since esp32_txint has already locked the spinlock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-09 19:35:17 +09:00
Abdelatif Guettouche	b5bb1fb8a3	esp32_serial.c: Replace critical section by a device specific spin lock. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-09 19:35:17 +09:00
Abdelatif Guettouche	f47d28c108	esp32_serial.c: Don't fake an interrupt when interrupts are not suppressed. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-09-08 09:27:08 -03:00
zhuyanlin	26b4bb3075	xtensa:cache: fix typo error use addr instead of add	2021-09-08 11:19:02 +02:00
YAMAMOTO Takashi	4f7226ac4a	arch/avr: Remove -nostartfiles -nodefaultlibs from LDFLAGS These options are not ld options. The recent versions of ld complain on them. https://sourceware.org/pipermail/binutils/2021-June/116826.html	2021-09-08 09:40:48 +08:00
YAMAMOTO Takashi	58bdcbab9b	Revert "Make: use gcc as LD" This reverts commit `45672c269d`. Because: * It's very confusing to have cc as LD. * I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are supposed to do when we use LD directly. It would be simpler to remove them from our LDFLAGS.	2021-09-08 09:40:48 +08:00
Jari van Ewijk	5f63fa391f	Fix error in s32k118_pinmux.h	2021-09-07 17:34:19 -07:00
zhuyanlin	7b5c39a9d3	arch:xtensa: add xtensa_cache code support Add xtensa_cache code support	2021-09-07 13:33:31 +08:00
zhuyanlin	d6fe0f18f5	arch:xtensa: add XTENSA_CACHE config support Add support for XTENSA_HAVE_ICACHE & XTENSA_HAVE_DACHE	2021-09-07 13:33:31 +08:00
YAMAMOTO Takashi	5ad1cba338	Revert "arch: Replace ar and nm with gcc-ar and gcc-nm" This reverts commit `b05737d78f`. Because it broke clang-based builds.	2021-09-07 10:54:15 +08:00
Fotis Panagiotopoulos	eb48a0dbe0	Fix in STM32_UART8 Kconfig.	2021-09-07 10:52:44 +08:00
Jukka Laitinen	1b75b5d5aa	Fix compilation of arm protected build Correct typos in include/nuttx/arch.h and suppress "'noreturn' function does return" warning coming from arm_pthread_exit.c Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>	2021-09-07 00:31:47 +08:00
Juha Niskanen	b70ae9ae82	arch/arm/src/stm32l4/stm32l4_flash.c: fix FLASH_CONFIG_I to use dual-bank access This is currently only used on STM32L4+ devices. Page erase in flash_erase() function supports only dual-bank mode so it makes little sense to configure this for unsupported single-bank mode. Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-04 14:31:16 +08:00
Sara Souza	26397c6695	xtensa/esp32: Wi-Fi board logic refactoring. This commit removes the initialization of the Wi-Fi partition from the Wi-Fi board logic and moves it to the SPI Flash board code. It creates 2 different partition (one for Wi-Fi and one for general use). It also allows these partitions to be mounted over several FSs.	2021-09-04 14:30:02 +08:00
Juha Niskanen	508215581f	arch/arm/src/stm32l4: fix STM32L4+ option bytes memory address Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>	2021-09-03 09:55:54 -03:00
liucheng5	fdb9576d7a	feature: driver: Add a Linux SPI into simulator. When SIM_SPI is valid, a specified Linux SPI device ‘spidevN.P’(N is bus number and P is CS number) is attached to nuttx simulator, shown as 'spi0' under /dev. One may type spi command (need SPITOOL valid) in NSH to control the Linux SPI and exchange data, other devices such sensors can use it to debug in simulator on a Ubuntu PC. Note that a USB<>SPI module (e.g. CH341A/B) should be plugged in to achieve Linux SPI ports. Change-Id: I275b2c2bbf6d14bcdf514c89efb9a2264d69e9a3 Signed-off-by: liucheng5 <liucheng5@xiaomi.com>	2021-09-03 18:15:25 +08:00
Alin Jerpelea	a20d4ac4ec	author: Aleksandr Vyhovanec: update licenses to Apache Aleksandr Vyhovanec has submitted the ICLA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-09-03 17:38:33 +08:00
Xiang Xiao	b05737d78f	arch: Replace ar and nm with gcc-ar and gcc-nm to make enable LTO easily Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-09-02 10:02:14 -03:00
zhuyanlin	fd9ce0137e	arch:xtensa: add xtensa mpu support Add support for Xtensa Memory Protect Unit. Change-Id: I27e2f05daae24429ef7513d843b4f217daeefa0d	2021-09-02 09:17:26 -03:00
Sara Souza	8081228556	xtensa/esp32-s2: Adds support to the timer driver Only one more support for ESP32-S2 chip.	2021-09-01 14:10:01 -03:00
Gustavo Henrique Nihei	2071aadc0e	sim: Inhibit stack protector on stack coloration function Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-09-01 23:11:03 +08:00
Michal Lenc	1ec0258407	arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs CAN_ESR2 register was having problems of havng the correct values when the bus was busy (with 3 and more nods). The register bit fields were incorrectly indicating that there is no free MB and would not updated itself from this state which was causing the applications to freeze on write. This change relies only on a software control which should avoid the problems described above. Signed-off-by: Michal Lenc <michallenc@seznam.cz>	2021-08-31 14:47:41 -03:00
Masayuki Ishikawa	24697e8f67	arch: x86_64: Fix idle stack allocation Summary: - I noticed that qemu-intel64:nsh does not work - And I found that commit `6e6eecaa73` affected this issue - This commit changes idle stack allocation to fix the issue Impact: - None Testing: - Tested with qemu-intel64:nsh and qemu-intel64:ostest Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>	2021-08-31 17:06:59 +08:00
Oleg	e95f23ef8b	arch/arm/stm32f7/stm32_irq: Fix format strings	2021-08-31 16:56:55 +08:00
Alin Jerpelea	da92258333	arch: k210: remove extra license information the Apache license header uses a standard format and the extra information should be removed. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-31 08:20:18 +09:00
Xiang Xiao	b0c782255c	libxx: Change CXX_LIBSUPCXX to LIBSUPCXX align with other Kconfig(e.g. LIBCXXABI, LIBCXX, UCLIBCXX) Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-28 17:14:48 -03:00
zhuyanlin	9ea7676731	arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS The name used in Tensilica support file core-isa.h for all vendors is `XCHAL_NUM_INTLEVELS`. Use a new name may be confused by newer porting xtensa arch. Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de	2021-08-28 21:51:45 +02:00
zhuyanlin	cd18d1f050	arch:riscv: remove arch atomic, use libc atomic when need It is more common for implement in libc/machine Change-Id: I3da6c3db64adb78c05ddb26d3956817ac6ada93e	2021-08-28 13:17:30 -03:00
Xiang Xiao	f0001574ed	arch/armv8-m: Update per the latest architecture reference manual https://developer.arm.com/documentation/ddi0553/latest Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-27 11:39:27 +02:00
Abdelatif Guettouche	1385ea7673	arch/esp32: Properly handle GPIO interrupt in SMP. The PRO CPU and APP CPU have different peripherals for GPIO interrupts. Each CPU needs to allocate an interrupt and attach it to its GPIO peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-27 13:24:00 +09:00
chao.an	bcce3314e5	arch/arm/cortex-m: add up_backtrace support add up_backtrace support based on push/branch instruction Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 18:31:51 +08:00
chao.an	d5d6297ca1	arch/arm/assert: enhance the assert dump show the all tasks info including backtrace and registers Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 13:31:08 +08:00
chao.an	f14bd44001	arch/armv7: add up_backtrace support based on frame pointer This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory This feature can not be used in THUMB2 mode if you are using GCC toolchain, More details please refer: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172 Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-26 13:30:08 +08:00
Kapil Gupta	ec99e11f5e	esp32/softap: Enable the WPA2 by default to ask user password Signed-off-by: Kapil Gupta <kapil.gupta@espressif.com> Co-author: Alan Carvalho de Assis <alan.carvalho@espressif.com>	2021-08-26 13:26:57 +08:00
ligd	f1aec38ffa	arm: add ARM_HAVE_NEON to Kconfig Change-Id: I112037aa15a6fae76cf4b7c2df10a42899c38a61 Signed-off-by: ligd <liguiding1@xiaomi.com>	2021-08-26 13:25:43 +08:00
Abdelatif Guettouche	fc594c5d25	esp32_irq.c: Extend the CPU interrupt/peripheral map to include the status of the interrupt (enabled/disabled). Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	810ed19b8f	arch/xtensa/esp32_irq.c: Enable/disable interrupts using the Interrupt Matrix. This allows manipulating interrupts from both CPUs. Internal interrupts however, still need to be disabled/enabled by each CPU. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	a7abd56448	arch/xtensa: Move the Xtensa specific part of interrupts to xtensa/include/irq.h Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	470799b0b3	arch/xtensa/esp32_irq: Remove the map/unmap IRQ functions they are used only inside this file. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	04cd520293	arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	79cc12c034	arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. They do the same thing (manipulate interrupts) keeping them separated was making things harder. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	237aebb7e1	arch/xtensa/esp32_cpuint.c: Refactor retrieving the intmap and register address of a peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	02c17c3169	arch/esp32: Simplify the interrupt allocation process. Allocating and attaching interrupts were both exported outside, however these two move hand in hand and we don't have to expose these details. Also, the parameters passed are saved and will be used to retrieve information about the interrupt and the attached peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	eefe7ebe5f	xtensa/esp32_cpuint: export only one function to allocate a CPU interrupt. That function will have a parameter to decide whether to allocate a level sensitive interrupt or an edge sensitive interrupt. All the drivers are also updated with this API change. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-26 07:06:22 +09:00
Abdelatif Guettouche	dbdec45049	arch/xtensa/src/common: Use irq_spin APIs in modifyregXX Replace enter_critical_section with spin_lock_irqsave. Replace leave_critical_section with spin_unlock_irqrestore. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-25 23:32:40 +08:00
Abdelatif Guettouche	5ff703d5d0	arch/*_testset: Fix few typos. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-25 00:20:20 +08:00
Alin Jerpelea	07d528fd8d	license: Ken Pettit: update licenses to Apache Ken Pettit is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-23 11:41:41 +08:00
chao.an	6cfb132232	arch/cortex-m: replace arm_switchcontext to c-style Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-22 14:44:01 +08:00
chao.an	68d6dbf86f	arch/riscv/assert: enhance the assert dump enhance the assert dump to show the all tasks info including backtrace and registers [ 7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init [ 7.617000] [ EMERG] riscv_dumpstate: Call Trace: [ 7.617000] [ INFO] [BackTrace\| 3\|0]: 0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894 [ 7.617000] [ INFO] [BackTrace\| 3\|1]: 0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56 [ 7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0 [ 7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074 ... ... [ 7.617000] [ EMERG] riscv_showtasks: Tasks status: [ 7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0 [ 7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976 [ 7.617000] [ INFO] [BackTrace\| 0\|0]: 0x4200787e 0x3fc94ff0 [ 7.617000] [ EMERG] riscv_registerdump: EPC:4200787e [ 7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074 ... [ 7.617000] [ EMERG] riscv_taskdump: [ 7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1 [ 7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016 [ 7.617000] [ INFO] [BackTrace\| 1\|0]: 0x420082a6 0x4200328c 0x42001ab4 0x42001a42 [ 7.617000] [ EMERG] riscv_registerdump: EPC:420082a6 [ 7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000 ... Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-21 14:58:21 +08:00
chao.an	333191becd	riscv/backtrace: add up_backtrace support Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-21 14:56:34 +08:00
Abdelatif Guettouche	2925d4956b	xtensa/esp32: Use up_cpu_index instead of this_cpu. this_cpu requires sched.h to be included.	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	5d626f7267	xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs are do not go through the regular process where we attache the CPU interrupt to a peripheral and update our map, also, they are fixed and a have reserved CPU interrupt, thus hard code their values at startup. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	56a7f3b651	arch/xtensa/esp32: Update the drivers regarding the API change in IRQ handling. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	5be9f24fe5	arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. At this point we are in a critical section and have all the necessary information to disable the interrupt properly (CPU, and CPU interrupt). Leaving it to the drivers will complicate things as converting from IRQs to CPU interrupts could be tricky in SMP mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	97dca8fe10	arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and irq.c Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Abdelatif Guettouche	633cdf8e27	arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. This map also keeps track of the CPU that attached the IRQ. This will be used to properly disable the interrupt in the correct CPU in SMP mode. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-20 13:17:25 -03:00
Sara Souza	e092c457e6	xtensa/lx7: Fix the CROSSDEV variable	2021-08-20 16:48:20 +02:00
Xiang Xiao	af72376773	fs: Remove magic field from partition_info_s since it is wrong and impossible to return file system magic number from the block or mtd layer. Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-20 09:19:52 -03:00
Antti Vähälummukka	6eb73ced51	arch/risc-v/src/mpfs: Add CorePWM driver Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals	2021-08-20 08:56:30 -03:00
Xiang Xiao	4b41579ccf	arch/armv8-m: Add SAU support Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-20 10:22:43 +09:00
raiden00pl	78962165d8	arch/stm32: add 3-phase Hall effect sensor lower half	2021-08-19 08:19:38 -07:00
chao.an	1060953567	sched/backtrace: add sched_backtrace support Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-19 01:30:50 -07:00
chao.an	0a8d951837	arch/arm: correct the frame pointer register declare In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code. In AArch64, the frame pointer is stored in register X29. Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-19 01:26:07 -07:00
Abdelatif Guettouche	cd0f64d779	xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-18 10:49:58 -03:00
raiden00pl	532ec126e9	stm32/stm32_serial.c fix compile error when CONFIG_STM32_SERIALBRK_BSDCOMPAT=y. Fix for https://github.com/apache/incubator-nuttx/issues/4353	2021-08-18 04:43:32 -07:00
Abdelatif Guettouche	a220766d57	xtensa.h: Remove unused function prototype. ESP32 uses a different function to start the app CPU and no other xtensa CPU uses this __cpu1_start function. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-18 04:41:40 -07:00
chao.an	e37d8da074	riscv/common: add CURRENT_REGS declare in RV32 Signed-off-by: chao.an <anchao@xiaomi.com>	2021-08-18 04:40:38 -07:00
Juha Niskanen	e02e1c25f6	arch/arm/src/stm32l4/Kconfig: add new STM32L4+ chip types Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Change-Id: I74050913643db23b4d03abaf516989ff3cdac142	2021-08-17 06:27:18 -07:00
Alin Jerpelea	4b20cf30c0	arch: misoc: update licenses to Apache Gregory Nutt is the copyright holder for those files and he has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-16 07:11:32 -07:00
Alin Jerpelea	351091ed75	author: Pierre-noel Bouteville: update licenses to Apache Gregory Nutt has submitted the SGA as a result we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>	2021-08-16 07:11:32 -07:00
Xiang Xiao	71269811ca	mtd: Implement BIOC_PARTINFO for all drivers Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-16 10:08:26 -03:00
Virus.V	5a1de89370	riscv/bl602: Fix that AP cannot be start when STA have been started.	2021-08-16 02:06:59 -07:00
Xiang Xiao	f63d1cfbbb	arch/arm: Add NVIC_FPCCR_XXX macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-15 10:50:52 +02:00
Xiang Xiao	fad0c3b38b	arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-14 11:41:59 -07:00
Xiang Xiao	33666832c5	arch/arm: Add NVIC_AIRCR_VECTKEY macro to avoid the hard code value Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-14 11:41:59 -07:00
Abdelatif Guettouche	5b350f3a0f	arch/*_reprioritizertr.c: Fix typos in comments. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-14 11:19:34 -07:00
Gustavo Henrique Nihei	1dfcc6ab49	xtensa/esp32: Enable boot from Espressif's port of MCUboot Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>	2021-08-13 08:44:20 -03:00
zhuyanlin	1a1b1cc2b4	arch:xtensa: replace include file from src/chip_xxx to chip.h Use chip.h as a standard include file, replace chip_xxx in src dir	2021-08-12 16:18:35 +02:00
zhuyanlin	30a2338e92	arch:esp: create chip.h header for chip src code. Create chip.h header for esp src code.	2021-08-12 16:18:35 +02:00
zhuyanlin	6d592256fb	arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h Those header contain syntax not be recognize by gnu assembler.	2021-08-12 16:18:35 +02:00
Alexander Vasiljev	4229099944	arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart.	2021-08-12 08:07:18 -03:00
Xiang Xiao	6b6c11f0ad	mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-12 08:01:29 -03:00
Xiang Xiao	d1687418db	mtd: Remove the empty MTDIOC_XIPBASE implmentation Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>	2021-08-11 09:50:51 -03:00
zhuyanlin	e333733053	xtensa:coproc: fix XTENSA_CP_ALLSET error in some case Consider follow coprocessor configuration case: \#define XCHAL_CP_NUM 1 /* number of coprocessors / \#define XCHAL_CP_MAX 2 / max CP ID + 1 (0 if none) / \#define XCHAL_CP_MASK 0x02 / bitmask of all CPs by ID / \#define XCHAL_CP_PORT_MASK 0x00 / bitmask of only port CPs / \ \#define XCHAL_CP1_NAME "AudioEngineLX" \#define XCHAL_CP1_IDENT AudioEngineLX \#define XCHAL_CP1_SA_SIZE 208 / size of state save area / \#define XCHAL_CP1_SA_ALIGN 8 / min alignment of save area / \#define XCHAL_CP_ID_AUDIOENGINELX 1 / coprocessor ID (0..7) */ In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all vaild coprocs. Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f	2021-08-10 19:44:55 -07:00
Abdelatif Guettouche	054e284785	*_cpustart.c: Fix typos in function description. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>	2021-08-11 11:06:27 +09:00
Fotis Panagiotopoulos	5b7ff03f40	lpc17_40: Fixed I2C port sanity check.	2021-08-10 09:04:33 -07:00
raiden00pl	2b3106fb47	Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX	2021-08-10 11:19:05 -03:00
raiden00pl	51b24c4bad	stm32/qenco: add support for QEIOC_SETPOSMAX	2021-08-10 11:19:05 -03:00
raiden00pl	092a0c8453	stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit Previous implementation has always expanded the width of the timer to 32-bit. This feature is not always needed and should be configurable from Kconfig.	2021-08-10 11:18:40 -03:00
raiden00pl	b0c9a6133e	stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit STM32F3 has timers of the same length as in STM32F4.	2021-08-10 11:18:40 -03:00
raiden00pl	3dd385ac0c	stm32/qenco: add support for STM32G4 This required generalization of RCC definitions that are not compatible with previous chips	2021-08-10 11:18:40 -03:00

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18945 Commits