Summary:
- This commit fixes DEBUGASSERT in lm3s_ethernet.c
Impact:
- lm3s_ethernet.c only
Testing:
- Tested with lm3s6965-ek:discover with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes a compile warning in cxd56_sdhci.c
Impact:
- None
Testing:
- Built with spresense:wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit replaces SHES related headers under cxd56xx
Impact:
- No impact
Testing:
- Build check only
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds imx_enet driver derived from imxrt_enet
Impact:
- imx6 only
Testing:
- Tested with sabre-6quad:netnsh
- NOTE: telnetd works with QEMU
Summary:
- This commit fixes peripheral IP offsets in AIPS-2
Impact:
- No impact because there is no drivers
Testing:
- Tested with sabre-6quad:nsh and sabre-6quad:smp
Summary:
- During repeating ostest with sabre-6quad:smp (QEMU),
I noticed that pthread_rwlock_test sometimes stops
- Finally, I found that nxtask_exit() released a critical
section too early before context switching which resulted in
selecting inappropriate TCB
- This commit fixes this issue by moving nxsched_resume_scheduler()
from nxtask_exit() to up_exit() and also removing
spin_setbit() and spin_clrbit() from nxtask_exit()
because the caller holds a critical section
- To be consistent with non-SMP cases, the above changes
were done for all CPU architectures
Impact:
- This commit affects all CPU architectures regardless of SMP
Testing:
- Tested with ostest with the following configs
- sabre-6quad:smp (QEMU, dev board), sabre-6quad:nsh (QEMU)
- spresense:wifi_smp
- sim:smp, sim:ostest
- maix-bit:smp (QEMU)
- esp32-devkitc:smp (QEMU)
- lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When the architectural support for STM32G4 family was added, the
reference manual (RM0440) was at revision 2. Since then, it has
undergone several revisions. One significant change is in the
table of FLASH wait states: section 3.3.3 table 9. The outcome
of this change is that fewer FLASH wait states are needed for
most CPU clock (HCLK) frequencies. Notably, if running the CPU
clock at the maximum 170 MHz, only 4 FLASH wait states are
needed, rather than the previously programmed 8 wait states.
This gives a noticeable performance boost.
arch/arm/src/stm32/stm32g4xxxx_rcc.c:
* FLASH_ACR_LATENCY_SETTING: Reimplement compile-time logic
that selects the required wait state setting to use the new
updated table.
* Update all comments to indicate that RM0440 Rev 5 is used.
* Update section numbers mentioned in comments in cases where
they have changed due to added sections in the manual.
arch/arm/src/stm32/hardware/stm32_adc_v2g4.h:
* New file.
arch/arm/src/stm32/hardware/stm32_adc.h:
* Distinguish between the normal STM32 ADC IPv2 core and the
modified IPv2 core used in the G4 family, and include either
stm32_adc_v2.h or stm32_adc_v2g4.h as needed.
Summary:
- This commit introduces SP_WFE() and SP_SEV() to be used for spinlock
- Also, use wfe/sev instructions for ARMV7-A to reduce power consumption
Impact:
- ARMV7-a SMP only
Testing:
- sabre-6quad:smp (QEMU, dev board)
- maix-bit:smp, esp32-devkitc:smp, spresense:smp sim:smp (compile only)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Because this_task() returns the current task of the current CPU
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes global IRQ control logic
- In previous implementation, g_cpu_irqset for a remote CPU was
set in sched_add_readytorun(), sched_remove_readytorun() and
up_schedule_sigaction()
- In this implementation, they are removed.
- Instead, in the pause handler, call enter_critical_setion()
which will call up_cpu_paused() then acquire g_cpu_irqlock
- So if a new task with irqcount > 1 restarts on the remote CPU,
the CPU will only hold a critical section. Thus, the issue such as
'POSSIBLE FOR TWO CPUs TO HOLD A CRITICAL SECTION' could be resolved.
- Fix nxsched_resume_scheduler() so that it does not call spin_clrbit()
if a CPU does not hold a g_cpu_irqset
- Fix nxtask_exit() so that it acquires g_cpu_irqlock
- Update TODO
Impact:
- All SMP implementations
Testing:
- Tested with smp, ostest with the following configurations
- Tested with spresense:wifi_smp (NCPUS=2,4)
- Tested with sabre-6quad:smp (QEMU, dev board)
- Tested with maix-bit:smp (QEMU)
- Tested with esp32-core:smp (QEMU)
- Tested with lc823450-xgevk:rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
imxrt UART must be placed in 9 bit mode (M=1) with when 8 bit
data with parity is required. If left in 8 bit mode (M=0) with
parity then D7 of the TX/RX register becomes parity bit. Hence
what is called 9-bit or 8-bit Mode Select is a misnomer.
8 bit mode when parity is enabled is realy 7 bit with parity.
I left mixed case identifiers for another commit.
arch/arm/src/imxrt/imxrt_lcd.c:142:13: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:143:13: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:147:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:157:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:162:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:173:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:184:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:195:39: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:208:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:210:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:212:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:214:17: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:11: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:23: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:514:33: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:519:11: error: Mixed case identifier found
arch/arm/src/imxrt/imxrt_lcd.c:519:23: error: Mixed case identifier found
The following nxstyle errors are intentionally left.
They are constants definitions like TPM_CnSC_MSB.
arch/arm/src/kl/kl_pwm.c:438:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:438:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:445:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:445:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:452:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:452:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:459:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:459:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:466:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:466:59: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:473:44: error: Mixed case identifier found
arch/arm/src/kl/kl_pwm.c:473:59: error: Mixed case identifier found
The following errors are intentionally left.
(Hardware constants like DMA2D_xGPFCCR_CCM.)
arch/arm/src/stm32/stm32_dma2d.c:484:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:692:13: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:701:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:706:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:711:18: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:725:14: error: Mixed case identifier found
arch/arm/src/stm32/stm32_dma2d.c:732:18: error: Mixed case identifier found
The following nxstyle errors are intentionally left.
They are "Lx" constants shared among multiple files.
arch/arm/src/stm32/stm32_ltdc.c:1774:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1775:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1779:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1780:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1784:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1785:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1804:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1805:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1806:10: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1845:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1849:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:11: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1903:34: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:12: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1907:35: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1987:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:1991:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2027:16: error: Mixed case identifier found
arch/arm/src/stm32/stm32_ltdc.c:2031:17: error: Mixed case identifier found
arch/arm/src/stm32/stm32_oneshot.c:
arch/arm/src/stm32/stm32_oneshot.h:
arch/arm/src/stm32/stm32_oneshot_lowerhalf.c:
arch/arm/src/stm32/stm32_dbgmcu.h:
* Fix nxstyle errors.
arch/arm/src/stm32/stm32_lsi.c:
* Fix nxstyle errors.
* Also a minor grammar fix in a comment: add "in" to "setting the
LSION bit in the RCC CSR register."
stm32f7, stm32h7, stm32l4 and stm32f0l0g0 do it this way and there is no
reason for classic stm32 to differ. Also manipulation of priv->ie was not
atomic with respect to interrupts.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with lc823450-xgevk:rndis
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic added to cxd56_cpupause.c
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Run smp and ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that sched_add_readytorun() runs on multiple CPUs simultaneously
- Finally, I found the root cause which was described in TODO
- Actually, the task newly scheduled on remote CPU did not acquire g_cpu_irqlock
- This commit fixes this issue by adding a critical section to the pause handler
- Which will acquire g_cpu_irqlock on the remote CPU explicitly
Impact:
- SMP only
Testing:
- Tested with spresense:wifi_smp (NCPUS=2 and 4)
- Run smp, ostest, nxplayer
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that Cortex-A SGI can be masked
- We thought the SGI is not maskable
- Although I can not remember how I tested it before
- It actually works as expected now
- Also, fixed the number of remaining bugs in TODO
Impact:
- No impact
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
- Add the following code in up_idle() before calling asm("WFI");
+ if (0 != up_cpu_index())
+ {
+ up_irq_save();
+ }
- Run the hello app, you can see "Hello, World!!"
- But nsh will freeze soon because arm_pause_handler is not called.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
It seems that part of the patch
stm32l4: correct build of stm32l4_can.c to respect L4 variant
has been lost on its way to mainline.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Summary:
- Remove unnecessary d-cache operation to make boot fast
Impact:
- armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:
* New files, based on STM32G474RE reference manual, RM0440 Rev 4.
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:
* Remove all mentions of DMAMUX12 from comments. This family has
at most DMAMUX1 only.
* Add missing defines DMAMUX_CCR_SPOL_NONE,
DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
DMAMUX_CCR_SPOL_BOTH.
* DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
but datasheet shows bits 24-28 (5 bits).
* DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
shows (5 bits) 0x1f.
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
datasheet shows only 2 bits (0x3).
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
but datasheet shows 5 bits (0x1f).
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_spi.h:
* Avoid numerous ifdef on STM32 part numbers and make the
different variations of SPI peripheral features more
self-documenting: based on STM32_HAVE_IP_SPI_V* defines
from chip.h, define some or all of HAVE_SPI_I2S,
HAVE_SPI_TI_MODE, HAVE_SPI_ARB_DATA_SIZE, HAVE_SPI_FIFOS,
HAVE_SPI_NSSP, HAVE_SPI_I2S_ASTRT, and make decisions on
which registers and bitfields to define based on them.
* Define registers and bitfields for STM32_HAVE_IP_SPI_V4,
currently used only for STM32G47XX family MCUs, including
SPI_CR1_CRCL, SPI_CR2_NSSP, SPI_CR2_FRXTH, SPI_CR2_LDMARX,
SPI_CR2_LDMATX, SPI_CR2_DS_SHIFT/SPI_CR2_DS_MASK,
SPI_SR_FRLVL_SHIFT/SPI_SR_FRLVL_MASK, and
SPI_I2SCFGR_ASTRTEN.
* SPI_I2SCFGR_I2SSTD_PHILLIPS: Was defined incorrectly as
(xx << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(0 << SPI_I2SCFGR_I2SSTD_SHIFT).
* SPI_I2SCFGR_I2SSTD_MSB: Was defined incorrectly as
(0 << SPI_I2SCFGR_I2SSTD_SHIFT). Corrected this to
(1 << SPI_I2SCFGR_I2SSTD_SHIFT).
* Fix nxstyle errors.
arch/arm/include/stm32/chip.h:
* Add new section "Peripheral IP versions" and specify version of
SPI IP block for STM32F10XX, STM32F20XX, STM32F30XX, STM32F33XX,
STM32F37XX, STM32F4XXX, STM32G47XX, and STM32L15XX.
arch/arm/src/stm32h7/hardware/stm32_dmamux.h:
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows only 2 bits.
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 7 (3 bits) but
datasheet shows 5 bits.
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
This change improves upon current support for pin interrupts. Before,
a pin interrupt was handled (with nrf52_gpiote_setevent) using one
of the eight available GPIOTE channels. Moreover, it didn't event let
the user specify which channel to use (simply tried to get a free one).
Also, it was buggy since it did not consider unsetting the callback.
Besides GPIOTE channels, there is another way to deal with pin interrupts.
The GPIO peripheral is capable of generating a PORT event
(for the whole GPIO port) depending on the pin SENSE configuration
(HIGH or LOW, or NONE) and GPIO DETECTMODE register
(latching or non-latching).
This change then renames nrf52_gpiote_setevent into nrf52_gpiote_set_ch_event,
maintaining functionality of original function, but now allows specifying
channel (and correctly handles unsetting the callback). Then, a
new nrf52_gpiote_set_pin_event is added, which allows to set a callback
for a given pin. During initialization, interrupt for the PORT event is
enabled and handled in such way that for each pin whose corresponding
bit in LATCH register (indicates the result of pin SENSEing) the
callback for this pin will be invoked. This mechanism means that
every pin can get an ISR. It also avoids using GPIOTE channels for this
purpose which carry higher current consumption.
This new per-pin callback mechanism has some added memory requirement
so it can be disabled and its default is dependant on DEFAULT_SMALL.
When disabled, a callback for the PORT event can be set directly
with nrf52_gpiote_set_port_event
There was only one use of nrf52_gpio_setevent() which was migrated
into nrf52_gpio_set_ch_event() passing channel zero.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_flash.h:
* Merge comments when they are section separators for
similar/related registers:
- TIVA_FLASH_FWPWRITE*
- TIVA_FLASH_FSM_SECTOR1*
- TIVA_FLASH_FSM_BSLE*
- TIVA_FLASH_FSM_BSLP*
When HAVE_HSI_CONTROL, adc_reset_hsi_disable() calls adc_reset()
followed by adc_shutdown() and this combination is called before
adc_setup() by upper level ADC driver. Without this patch,
priv->initialized wraps from 0 to 255 in this case.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h:
* Fix syntax error. The define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MIN
had an unintentional comment closing "*/" in the middle of its
name.
This separation allows to interact with the watchdog from OS code,
for example initiating the watchdog very early on boot. Moreover,
these changes make the lower-half driver support an already running
watchdog, which may happen if there's a bootloader which already
started it.
Summary:
- This commit fixes kernel stack dump information
Impact:
- Affects armv7-a with kernel build
Testing:
- Built with sama5d4-ek:knsh
- Not tested
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects armv6-m with interrupt stack enabled
Testing:
- Built with freedom-kl25z:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-m
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv8-m with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-r with interrupt stack enabled
Testing:
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same logic for armv7-a
- NOTE: stack pointer alignment is 4-byte
Impact:
- Affects arm (arm7/9) and c5471 with interrupt stack enabled
Testing:
- Built with c5471evm.nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Built with ea3131:nsh (CONFIG_ARCH_INTERRUPTSTACK=2048)
- Not tested but should work
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Remove -4/-8 offset coding in imx_irq.c and arm_vectors.S
- Instead, add SP adjustment after calling setirqstack/setfiqstack
- Fix off-by-one irq/fiq stack allocation in 8-byte aligned arch
- Fix comments on the user stack pointer in arm_vectors.S
- Also, fix up_dumpstate() to extract the user stack pointer
- NOTE: stack pointer alignment is 8-byte
Impact:
- Affects armv7-a with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp with QEMU
- Tested with sabre-6quad:nsh with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit fixes CPUx IDLE stack top for SMP
- Also removes SMP_STACK_TOP from smp.h
Impact:
- Affects armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
There is a good case on sim platform:
When we input some cmd and click enter key to start application in terminal,
this context will change to application from IDLE loop. Althrough entey key '\r'
has been received to recv buffer and complete post semaphore of reader, but
pollnotify may not be called because context change. So when application run
poll function, because no events happend and poll enter wait, context will
again change to IDLE loop, this pollnotify of IDLE loop will run to send poll
events, poll function of applicaton will wake up. It's wrong!
Change-Id: I812a889f2e90781a9c3cb4b0251cccc4d32bebd1
Signed-off-by: dongjiuzhu <dongjiuzhu1@xiaomi.com>
Summary:
- Modify arm_intstack_base() to return "top" of the IRQ stack for the current CPU
- This change fixes IRQ stack dump information for ARM SMP
- Add arm_intstack_alloc() to return "bottom" of the IRQ stack for the current CPU
- Also, these functions are now implemented in xxx_irq.c (imx/cxd56/lc823450)
- up_color_intstack() and up_check_intstack() now call arm_intstack_alloc()
- These semantics are now consistent with non-SMP case
- up_color_intstack() now initializes whole IRQ stack region for SMP
- Adjust IRQ stack top address for each CPU (e.g. -8)
- Fix setintstack to handle in case of NCPUS=1 (cxd56, lc823450)
- Adjust INTSTACK_SIZE to 8 bytes alignment (cxd56, lc823450)
- Refactor setintstack for lc823450
- Remove old IRQ stack coloring code from up_irqinitialize() (lc823450)
- Introduce g_cpu_intstack_top for lc823450
- Refactor header files
Impact:
- Affects imx6/cxd56xx/lc823450 SMP with interrupt stack enabled
Testing:
- Tested with sabre-6quad:smp (with QEMU, NCPUS=1 and 4)
- Tested with spresense:wifi_smp (NCPUS=1 and 2)
- Tested with lc823450-xgevk:rndis (NCPUS=1 and 2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
cfsetispeed() now stores baud rate to c_cflag member of
struct termios, so it must not be overridden later on.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
1.Get the stack pointer from sp instead of .Lstkinit's field
2.Make g_idle_topstack point to the end of the idle stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
arch/arm/src/tiva/cc13xx/cc13x0_rom.h,
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h:
* Fix nxstyle errors; nxstyle was complaining about lack of a
space after comma because of the presence of line
continuation backslashes immediately after the comma.
Removed these backslashes as they are not necessary: these
lines are typedefs, not preprocessor defines.
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c:
* Fix nxstyle errors.
* No functional changes; however modified one function,
trim_wakeup_fromshutdown(), to avoid blocks that existed
only to declare variables mid-function; nxstyle was
complaining about the positions of the opening and
closing braces of those blocks.
