arch/arm/src/tiva/cc13xx: Trim code now kind of looks like NuttX code. But does not yet compile.
arch/arm/src/tiva/cc13xx: The first few, feeble steps toward getting the overall trim files compatible with the requirements of the NuttX coding standard.
arch/arm/src/tiva/cc13xx: Replace last of TI hardware access macros with NuttX hardware access macros.
arch/arm/src/tiva/cc13xx: Change TI HWREGB to NuttX getreg8 or putreg8 in trim logic.
arch/arm/src/tiva/cc13xx: Change TI HWREGBITW to NuttX getreg32/putreg32 sequence in trim logic.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Completes the DDIO OSC header file.
cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Updated, but still not finished.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h: Add DDI0 OSC header file. Still a work in progress. Does not yet conform to the NuttX coding standard.
Change _M and _S to _MASK and _SHIFT.
Some minor improvements.
Clean up typos in some comments.
Run all new files against tools/indent.sh
arch/arm/src/tiva/cc13xx: Bring in trim files from SDK. Convert to C-style comments, lowercase hex contants. Remove Windows-style line endings.
I still observe data abort crash if I compile the code with optimization enabled.
The next steps are to investigate the optimization issue and add Watchdog module. Currently, NSH does not run for a long time ;)
arch/arm/src/am335x/am335x_irq.c: Correct interrupt processing routine
configs/beaglebone-black/nsh/defconfig: Enable debug compilation options. Otherwise data abort crash is observed
arch/arm/src/am335x/am335x_lowputc.c and arch/arm/src/am335x/chip/am335x_uart.h: UART-related cosmetic changes
arch/arm/src/am335x/am335x_timerisr.c: Make sure that Timer 1 interrupts are disabled before any access to peripheral registers
stm32f0l0: SPI and GPIO EXTI support
arch/arm/src/stm32f0l0: add support for GPIO EXTI
configs/nucleo-l073rz: support for nrf24l01
configs/b-l072z-lrwan1/include/board.h: add note about onboard Murata CMWX1ZZABZ-09 module and definitions for available peripherals
Approved-by: GregoryN <gnutt@nuttx.org>
Masayuki Ishikawa reports that this commit breaks ALL PROTECTED mode builds.
It violates the basic requirements of the use of the MPU in protected mode. Those basic requirements are:
1. The MPU region must be aligned to the base address of the memory region being mapped (it may NEVER extend before the memory region). That is, the following MUST always be zero:
(base & ((1 << l2size) - 1))
2. The MPU region must never extend beyond the end of the memory region. That is, the following must be true:
size >= (1 << l2size)
This reverts commit 8b63d02309.
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Many small changes related to coding style.
Author: Petro Karashchenko <petro.karashchenko@gmail.com>
configs/beaglebone-black: Adds initial support for the BeagleBone Black board.
arch/arm/src/am335x: Adds initial support for the TI AM355x family.
Fix lc823450 start
* arch/arm/src/lc823450: Use CONFIG_STACK_COLORATION instead of CONFIG_DEBUG_STACK
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix go_os_start() in lc823450_start.c
I found a bug in go_os_start() that it returns immediately
because it does not compare r1 to zero. This commit fixes
this bug. Also, this commit fixes its description.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
- Avoids the use of up_aesinitialize() entirely, which resolves dependency problems, because this function does not make sure that an actual hardware aes implementation was made available: each SoC is now responsible to ensure the AES hardware is initialized before first use. This applies to lpc43xx, stm32 and sam34.
- Remove definitions of the NEVER used aes_init and aes_update operations. The new AES API will be more suitable.
- Change the unusual naming in stm32 (avoiding possible naming clashes)
- Change the unusual naming in sam34 (avoiding possible naming clashes)
- Add some FAR to pointers and enforce the 80 col limit in stm32 and sam
Fix lc823450 related
* configs/lc823450-xgevk: Fix IOB params in rndis/defconfig
These prameters work for HTTP audio streaming.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix up_allocate_heap() in lc823450_allocateheap2.c
This change fixes heap size and also implements up_addregion().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/stm32f0l0: Some fixes for a clean build. Still have a problem with lots of error messages coming from kconfig-mconf, but the configuation looks fine. Sometimes kconfig errors are difficult to spot. I would appreciate it anyone can spot the issue.
arch/arm/src/stm32f0l0/hardware: Rename the chip directory to hardware. This will hopefully eliminate some problems that I have seen with the chip include paths not being unique in more complex configuartions.
configs/nucleo-f072rb, configs/nucleo-f091rc, configs/stm32f051-discovery, and configs/stm32f072-discovery: Update for all of the naming changes made in arch/arm/src/stm32f0l0
arch/arm/include/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/stm32f0l0: Rename stm32f0 to stm32f0l0 to make a speace for STM32 L0. Rename files, functions and defines, removeing the f0_ from the names in order to make them MCU agnostic.
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Adjust cloned CC13x9 FCFG1 header file so that it reflects reality.
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h: Add CC13x0 FCFG1 header file. Initial commit is the same as the CC13x2/CC26x2 FCFG1 header with a few name changes.
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_fcfg1.h: Initial FCFG1 header file for the cc13xx/cc26xx family.
arch/arm/src/tiva: Add GPIO IRQ stubs for clean compile
arch/arm/src/tiva/cc13xx: Add build framework for CC13xx GPIO interrupts. Change prototypes of some GPIO IRQ interfaces so that the function prototype is common between LM3S, LM4F, TM4C, and CC13xx.
Master
configs/nucleo-f334r8: add example for the SPWM generation (custom STM32 PWM usage)
arch/arm/src/stm32/stm32_pwm: fix compilation errors if the upper-half PWM logic is not enabled
include/nuttx/drivers/pwm.h: remove dependency on CONFIG_PWM for the upper-half PWM header. This allows compilation for the lower-level PWM drivers even if the upper-half PWM logic is not used.
arch/arm/src/stm32/stm32_tim.c: fix compilation error if there is no TIM8
configs/nucleo-f334r8/highpri: remove the upper-half ADC from configuration
configs/nucleo-f302r8/highpri: remove the upper-half ADC from configuration
configs/stm32f429i-disco/highpri: remove the upper-half ADC from configuration
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/tiva: Add CC13xx GPIO driver plus various fixes for clean compilation.
arch/arm/src/tiva/ and configs/launchxl-cc1312r1: Make type of the GPIO pin configuration an abstract type so that CC13xx MCUs can share the same GPIO function prototypes and usage model.
arch/arm/src/tiva: Add CC13xx logic to enable power domains needed by peripherals and to enable clocking to peripherals.
arch/arm/src/tiva: Rename some header files so that they are unique in order to avoid including the wrong file. Fix various compile issues found during some initial trial builds.
arch/arm/src/tiva: Add CC13xx clock enable and power enable macros that are backward compatible with lm/tm4c macros.
Improvements in STM32 ADC
arch/arm/src/stm32/stm32_adc.c: start conversion on startup is now possible if TIM triggering selected. This can be useful to start ADC TIM conversion for ADC IPv2 when opening ADC device.
arch/arm/src/stm32/stm32_adc.c: fix compilation errors for chips with one ADV TIM
configs/nucleo-f303re: refresh ADC example
configs/nucleo-f334r8: refresh ADC example
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/stm32h7/stm32_i2c.c
arch/arm/src/stm32l4/stm32l4_i2c.c
Those easy because F7 patch applied with no problem (after changing path and file names appropriately). The patch could not be appleed to the following. The logic is different. I don't know if a similar change is needed there or not.
arch/arm/src/stm32/stm32f30xxx_i2c.c
arch/arm/src/stm32/stm32f40xxx_i2c.c
arch/arm/src/stm32/stm32_i2c.c
arch/arm/src/stm32/stm32_i2c_alt.c
arch/arm/src/stm32f0/stm32f0_i2c.c
stm32f7:i2c out of bounds access on priv->msgv
Error in if statment. It was checking for msgc > 0.
If message count is 1, only index 0 is valid on
priv->msgv. There for random values in memory were
used to set next_norestart.
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/include/stm32/chip.h: remove redundant STM32 family definitions. It is already done in arch/arm/src/stm32/Kconfig
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/stm32/stm32_adc.c: refactor adc_reset. It should be easier to maintain this code if it's divided into smaller functions
Approved-by: GregoryN <gnutt@nuttx.org>
Use STM32 DMA IP core version instead of chip family names and some minor improvements
arch/arm/src/stm32/chip/stm32_adc.h: raise error if two IP cores seleceted
libs/libdsp/Kconfig: cosmetic change
arch/arm/src/stm32/Kconfig: hide TIMER menu, HRTIM menu and USB Host debug menu if peripherals not enabled
configs/stm32f429i-disco/highpri/defconfig: fix configuration warning
Approved-by: GregoryN <gnutt@nuttx.org>
configs/nucleo-f207zg, configs/nucleo-f103rb: add ADC and PWM examples; arch/arm/src/stm32_adc.c: there is no DMA CFG bit for the basic IPv1 ADC
Approved-by: GregoryN <gnutt@nuttx.org>
arch/arm/src/tiva/hardwar: Move LM3S and LM4F include files to hardware/lm/ sub-directory. Move all TM4C header files files to hardware/tm4c/ sub-directory.
arch/arm: Add basic configuration/build support for CC13xx parts. Conditioned on EXPERIMENTAL.
Squashed commit of the following:
arch/arm/src/tiva/Make.defs: Trivial change to conditional VPATH.
arch/arm/src/tiva: Move LM3S and LM4F source files to lm/ sub-directory. Move all TM4C source files to tm4c sub-directory.
arch/arm/src/tiva and configs/: Change include patch from chip/ to hardware/ in all Tiva files includes.
arch/tmp/src: Rename chip/ subdirectory to hardware/. This is a better name since it does not conflict with other directory names and, well, we are going to be change a lot of the Tiva directory structure in the next few commits.
arch/arm/src/max326xx/max32660/max32660_spim.c: SPI0 master mode support is complete (sans DMA and completely untested). configs/max32660-evsys/src: Add framework for SPI support.
arch/arm/src/max326xx/max32660/max32660_spim.c: Fleshes out some of the data transfer logic. More needs to be done. Also removes leveraged DMA support. It will be a long time (if ever) before DMA is supported. No point in dragging all of that bogus logic around.
Squashed commit of the following:
arch/arm/src/max326xx/max32660/max32660_spim.c: A few updates tot he SPI master driver. Still incomplete and does not even compile.
Update some comments
arch/arm/src/max326xx: Clean up some general build issues. Still STM32 code posing as MAX32660.
arch/arm/src/max326xx: Starting SPI driver. Initial commit is just the STM32 SPI driver with name changes.
arch/arm/src/max326xx and configs/max32660-evsys/src: Fix some issues with GPIO setup of output pins. Correct polarity of on-board LED output. The on-board LED is now functional.
arch/arm/src/max326xx: WFI instruction in IDLE loop seems to interfere with stability. Commented out for now. Needs to be investigated further.
arch/arm/src/max326xx: Fixes for GPIO configuration problems and serial driver problems. I now get the NuttShell prompt (if I also band on ENTER to force all of the characters out). Progress, but not yet ready.
configs/max32660-evsys: Support CONFIG_BOOT_RUNFROMISRAM=y.
arch/arm/src/max326xx/max32660/max32660_clockconfig.c: Fix an error in a register name.
arm/src/max326xx/max32660: Fix a few new compilation errors when DEBUG is enabled.
Improvements in STM32 ADC, minor changes in STM32 PWM, DMA, HRTIM and add some highpri ADC examples
arch/arch/src/stm32/stm32_adc: fix RCC reset logic
arch/arch/src/stm32/stm32_adc: move sample time change functions to low-level ADC ops
arch/arch/src/stm32/stm32_adc: configurable ADC DMA mode (one shot mode, circular mode)
arch/arch/src/stm32/stm32_pwm: remove llops_get interface. We can use structure casting to get pwm low-level ops
arch/arch/src/stm32/stm32_pwm: add timer enable/disable and frequency update to low-level ops
arch/src/arm/stm32: remove redundant stm32f33xxx_dma.c
arch/arm/src/stm32/stm32f40xxx_dma.c: add interfaces to interact with highp priority DMA interupts
arch/src/arm/stm32/stm32_hrtim: do not enable timers on startup if option from Kconfig selected and add interface to enable/disable timers
arch/src/arm/stm32/stm32_hrtim: fix some warnings
configs/nucleo-f334r8/highpri: update configuration due to changes in stm32_adc
configs/stm32f334-disco/buckboost: update configuration due to changes in stm32_adc
configs/nucleo-f334r8/highpri: add support for ADC injected sequence, add triggering from TIM1
configs/nucleo-f302r8/highpri: add high priority ADC interrupts example
configs/stm32f429i-disco/highpri: add high priority ADC interrupts example
Approved-by: GregoryN <gnutt@nuttx.org>
The user of this invalidation are mmcsd_sdio currently. The mmcsd_sdio driver makes calls for dcache invalidation through the chip specific architecture function SDIO_DMARECVSETUP(). I changed the arch/arm/stm32f7 chips to use arch_invalidate_dcache_by_addr() instead of arch_invalidate_dcache().
This commit includes additional changes to mmcsd_sdio.c. I created SDIO_DMADELYDINVLDT() (DMA delayed invalidate) to invalidate store-into mode dcaches after the DMA transfer. I have been using SDIO_DMADELYDINVLDT() for several weeks now and it has fixed the problems that I previously reported regarding non-cache aligned buffer invalidation errors (for my store-through dcache). However, it does not permit use of unaligned DMA buffers for store-into mode dcaches.
SDIO_DMADELYDINVLDT() is a NoOp unless the chip specific Kconfig file selects CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT. I have modified all the stm32f7 chips to select it.
arch/arm/src/max326xx/max32660/max32660_serial.c: Add a mostly commented out serial driver. With this, we can accomplish a complete build with many warnings for 'Missing logic'
configs/max32660-evsys/src/max326_button.c: Add support for the on-board button.
arch/arm/src/max326xx: Add a mostly empty max326_lowputc.c file mostly so that we can get further in the compilation. Fixed several more compile errors revealed by this.
arch/arm/src/max326xx: Add peripheral clock control header file.
Author: Gregory Nutt <gnutt@nuttx.org>
A few trivial updates from review of changes.
Remove references to NRF52-PCA10040 from documentation. Replace with NRF52-generic.
Remove configs/nrf52-pca10040/ Replaced with configs/nrf52-generic.
Author: Zou Hanya <hanyazou@gmail.com>
Improve LED handling #if~#endif in nrf52_autoleds.c and nrf52_userleds.c
Add Adafruit Feather nRF52 board LED support
Add Adafruit Feather nRF52 board
Add nrf52-generic
Replace 'pca10040' with 'generic'
Copy from nrf52-pca10040 to nrf52-generic
Squashed commit of the following:
arch/arm/src/max326xx and configs/max32660-evsys/nsh/defconfig: Work out some issues related to MAX326xx configuration.
configs/max32660-evsys: Add unverified board support framework.
stm32/stm32_adc: major refator
stm32/stm32_adc: use STM32 ADC IP core version and ADC available functions instead of chip family names in conditional compilation
stm32/chip: replace family specific ADC headers with STM32 ADC IP core version headers
stm32/stm32_adc: configurable sample time supported for all chips, not only L1
stm32/stm32_adc: enable/disable interrupts supported for all chips, not only L1
stm32/stm32_adc: resolution configuration
stm32/stm32f33xxx_adc: remove wrong assertion
configs/nucleo-f303ze: support for ADC and ADC example
configs/stm32f429i-disco: support for ADC and ADC example
Approved-by: GregoryN <gnutt@nuttx.org>
NuttX: STM32F407VG has only one DAC
NDAC=2 causes compilation error when trying to use e.g. STM32_DAC1_CR macro.
Approved-by: GregoryN <gnutt@nuttx.org>
imxrt:Clock config fixes and board.h sets sources and divisors
* imxrt:clockconfig bug fix & Board config set clocks
Fixed logic that was not clearing bits as ~ was
mising in &= mask operations.
Use valuse from the board.h file so set the Mux that
selects the clock sources.
Use board defined PODF values to select clock.
Only configure USDHC2 clocks when board defines clocks.
* imxrt1050-evk:Board setting used to set LSPI and USDHC Clocks
Approved-by: GregoryN <gnutt@nuttx.org>
When MIPS port is built for microMIPS and then loaded as an application, the __start entry point is entered in microMIPS mode, but the CPU core initialization code there misses to set the config3ISAOnExc bit to 1. Subsequently, exceptions are entered in MIPS32 mode, but the code base was built for microMIPS.
This change is needed specifically for the case where a bootloader sets the SPE bit before starting NuttX. In that case, the test in the SPI driver is bogus. This change fixes that by assuring that NuttX has booted and initialized at least once (whether or not SPE is set) before the driver starts refusing to initialize.
arch/arm/stm32*: Don't rely on SPI_CR1_SPE to determine if peripheral has been initialized yet.
Approved-by: GregoryN <gnutt@nuttx.org>
Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207
* arch/arm/src/stm32: Fixes Kconfig options to include all STM32F20XX processors, not just STM32F207
* arch/arm/src/stm32: Removes redundant STM32_STM32F429 depends from Kconfig. STM32F4XXX already does this
Approved-by: GregoryN <gnutt@nuttx.org>
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Completes review of configs/gapuino.
arch/risc-v/include/gap8/chip.h: Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
Move include/gap8/chip.h to src/gap8/chip.h. Internal details should not be exposed outside of arch/ and configs/. Review all headers files in src/gap8
Review of arch/risc-v/include.
Author: hhuysqt <hyq9606@126.com>
corrected author and email
Add app initialization, add signal support, cleanup irq context and configs
fix some warnings
gapuino initial port
GAP8 initial port
In addition to the problems that were previously identified there were a few other bits and pieces outstanding;
* Timing was dependent on CPU speed rather than absolute time
* End of transfer handling was a bit mixed up
* It's possible for data to still be in the FIFO (i.e. not have reached
the card) when a next write is requested, so we need to wait for that to
complete
* Interrupt Status could be carried over from one transfer episode to the
next, corrupting progress
* Multi-descriptor DMA writing simply wasn't implemented, but there were no
indications ... it just failed silently
Master imxrt
* imxrt:Fix typos bit# and names
* imxrt:wdog Registers are 16 Bits
* imxrt:wdog Update has to be within 255 clocks of unlock
* imxrt:clockconfig Fix comments
* imxrt1050-evk:board.h Fix comments
* imxrt:imxrt_ccm.h Define Mux Selects for board.h use
* imxrt:clockconfig Allow better control from board.h
1) Allows a board config clock setting to be defined
in terms of the /n values shown in Figure 18-2.
Clock Tree of the i.MX RT1050 Processor Reference
Manual, Rev. 1, 03/2018
2) Allows the clock multipelx selection to be made in
The board config.
* imxrt1050-evk:Define board clocking based on divisor and muxes
Approved-by: GregoryN <gnutt@nuttx.org>
* Clocks were wrongly configured - way too fast because there is no primary divider on LPC4330
This is fixed by means of changing the definitions in the board.h file. I've edited the one for the lpc4330-xplorer board because I'm actually working with Versiboard and don't want to contribute that config just yet while I've still got the drains up on it.
* The LPC43_SDMMC_DELAY register was not being set
I suspect, in the 'real world', it's possible to get away without setting this, but I've added a register definition, default value and register access macros into arch/arm/src/lpc43xx/chip/lpc43_scu.h and then used them in arch/arm/src/lpc43xx/lpc43_sdmmc.c.
* The LPC43_SDMMC_BLKSIZ and LPC43_SDMMC_BYTECNT registers had the wrong values.
The management have already implemented a rather nice block level interface for the stm32 so I've just re-used that to write to these registers as required. I'm slightly nervous that accessing the configuration registers (SCR being the prime example) which has a much smaller block size may not be being done in the right way but it does seem to work correctly, so let's assume it's all OK until someone tells me otherwise.
These fixes have been tested with DMA-based read/write on a LPC4330. Speed via nsh is pretty low but I'm assuming that's just a buffering/implementation issue for now.
