Commit Graph

19289 Commits

Author SHA1 Message Date
Eero Nurkkala
a21a396bd8 risc-v/mpfs: usb: apply review fixes
PR#5688 review fixes are in this patch. The PR was already
merged so the fixes are addresses here as a separate patch.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-09 10:26:56 +02:00
chao.an
ba2cb65a91 arch/sim: add all symbols support
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-09 10:16:54 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Huang Qi
8dedf1d9af arch/risc-v: Correct handling of QPFPU and DPFPU
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Gustavo Henrique Nihei
4a29fa903b xtensa/esp32s3: Enable SMP support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-09 10:42:50 +08:00
Richard Tucker
4888be37e3 arch/arm/src/sam34/sam_dmac.c: Fix compilation error 2022-03-09 10:18:32 +08:00
Gustavo Henrique Nihei
140dc248db xtensa/esp32s2: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-08 22:24:07 -03:00
Eero Nurkkala
4b2fbab998 risc-v/mpfs: usb: fix an unused variable warning
Fix an unused variable warning if the CONFIG_HAVE_USBTRACE
(and USB_DEBUG) aren't set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 23:00:31 +08:00
Gustavo Henrique Nihei
bd7ee0d675 xtensa/esp32s2: Sync IRQ management API with ESP32 and ESP32-S3
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-08 11:36:32 -03:00
Huang Qi
bfedbf1c05 arm/imx6: Enable setjmp test in ostest
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-08 21:00:29 +08:00
Huang Qi
cfff115f21 arm: Move setjmp to common place
Since some Cortex A core supports thumb mode also,
thus they can share same implementation.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-08 21:00:29 +08:00
Eero Nurkkala
8c1ab129ac risc-v/mpfs: add USB device driver
This adds a simple USB device driver for the mpfs. However,
this driver is still at its early phase. Only limited testing
with CDC/ACM has been conducted.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-03-08 16:49:29 +08:00
zhuyanlin
634d337394 riscv/xtensa: corrent dumpstate xcp size
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-08 10:14:04 +02:00
chao.an
a14ed02571 sim/syscall: add syscall note support in the flat build
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-07 23:58:28 +08:00
zhuyanlin
981282696f xtensa:backtrace: fix backtrace last buffer error in some scene
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-07 10:21:37 +01:00
Abdelatif Guettouche
fa0e5da18e xtensa/xtensa_user_handler.S: Store EXCCAUSE and EXCVADDR into the user
frame. The user frame is passed them to xtensa_user that actually uses
EXCVADDR.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-04 11:19:06 +02:00
Juha Niskanen
779665c704 arch/arm/src/stm32l4: STM32L4+ might need flash data cache corruption workaround
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2022-03-04 14:00:20 +08:00
Oleg Evseev
625d230d28 arch/arm/src/stm32f7/stm32_can.c: fix CAN3 receiving
by fixing filter initialization.

STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.
2022-03-03 14:31:37 -03:00
Abdelatif Guettouche
c820085a23 arch/xtensa/esp32s3: Add encrypted support for SPI FLASH.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-03 19:57:59 +08:00
Abdelatif Guettouche
9d5b13cd0e xtensa/esp32s3: Add SPI-Flash support.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-03 19:57:59 +08:00
Huang Qi
e383439dda risc-v: Replace all inline assembly with macro
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
Huang Qi
35330a798b risc-v: Implement READ_AND_SET_CSR for CSR operate
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-03 19:55:54 +08:00
zhuyanlin
5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation
Some chip not use the default cache size & way , read from
CCSIDR instead of hardcode.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-03 14:11:31 +08:00
Gustavo Henrique Nihei
16030f713e xtensa/esp32s3: Add support for Free-running Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-03 10:58:53 +08:00
Gustavo Henrique Nihei
3b7a6ae311 xtensa/esp32s3: Add support for Tickless kernel using Systimer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-02 18:08:44 +01:00
ligd
fe6aa4a874 sim: add loop thread to handle dev loops
For some dev loops will call sem_wait/sem_trywait

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-02 20:29:52 +09:00
Xiang Xiao
4a16cf71f9 Fix -Werror=nonnull-compare and -Werror=format-truncation=
Error: module/mod_insmod.c:203:3: error: 'strncpy' specified bound 16 equals destination size [-Werror=stringop-truncation]
  203 |   strncpy(modp->modname, modname, MODLIB_NAMEMAX);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

wqueue/kwork_thread.c: In function 'work_start_lowpri':
Error: wqueue/kwork_thread.c:212:22: error: '%lx' directive output may be truncated writing between 1 and 16 bytes into a region of size 14 [-Werror=format-truncation=]
  212 |   snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);

local/local_sockif.c: In function 'local_getsockname':
Error: local/local_sockif.c:392:11: error: 'strncpy' specified bound depends on the length of the source argument [-Werror=stringop-overflow=]
  392 |           strncpy(unaddr->sun_path, conn->lc_path, namelen);
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

chip/esp32_wifi_utils.c: In function 'esp_wifi_scan_event_parse':
Error: chip/esp32_wifi_utils.c:373:37: error: argument to 'sizeof' in 'memset' call is the same expression as the destination; did you mean to dereference it? [-Werror=sizeof-pointer-memaccess]
   memset(ap_list_buffer, 0x0, sizeof(ap_list_buffer));
                                     ^

stdio/lib_fputs.c: In function 'fputs':
Error: stdio/lib_fputs.c:99:9: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s == NULL || stream == NULL)
         ^
Error: stdio/lib_fputs.c:99:27: error: nonnull argument 'stream' compared to NULL [-Werror=nonnull-compare]
   if (s == NULL || stream == NULL)
                           ^

stdio/lib_vfprintf.c: In function 'vfprintf':
Error: stdio/lib_vfprintf.c:40:6: error: nonnull argument 'stream' compared to NULL [-Werror=nonnull-compare]
   if (stream)
      ^

string/lib_strdup.c: In function 'strdup':
Error: string/lib_strdup.c:39:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

string/lib_strndup.c: In function 'strndup':
Error: string/lib_strndup.c:56:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

string/lib_strpbrk.c: In function 'strpbrk':
Error: string/lib_strpbrk.c:39:7: error: nonnull argument 'str' compared to NULL [-Werror=nonnull-compare]
   if (!str || !charset)
       ^~~~
Error: string/lib_strpbrk.c:39:15: error: nonnull argument 'charset' compared to NULL [-Werror=nonnull-compare]
   if (!str || !charset)
               ^~~~~~~~

string/lib_strrchr.c: In function 'strrchr':
Error: string/lib_strrchr.c:40:6: error: nonnull argument 's' compared to NULL [-Werror=nonnull-compare]
   if (s)
      ^

Error: time/lib_asctimer.c:73:50: error: '%d' directive output may be truncated writing between 1 and 11 bytes into a region of size between 0 and 12 [-Werror=format-truncation=]
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
                                                  ^~
time/lib_asctimer.c:73:21: note: directive argument in the range [-2147481748, 2147483647]
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
time/lib_asctimer.c:73:3: note: 'snprintf' output between 17 and 68 bytes into a destination of size 26
   snprintf(buf, 26, "%.3s %.3s%3d %.2d:%.2d:%.2d %d\n",
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            g_wday_name[tp->tm_wday], g_mon_name[tp->tm_mon],
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            tp->tm_mday, tp->tm_hour, tp->tm_min, tp->tm_sec,
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            1900 + tp->tm_year);
            ~~~~~~~~~~~~~~~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-02 15:55:38 +08:00
zhuyanlin
a4e93be0fb arch:xtensa: fix sp duplicate reduce in handler enter
In xtensa/include/irq.h the XCPTCONTEXT_SIZE is
`#define XCPTCONTEXT_SIZE    ((4 * XCPTCONTEXT_REGS) + 0x20)`

XCPTCONTEXT_SIZE is already byte size of xcpcontext

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-01 13:46:31 +01:00
Xiang Xiao
a8ab090764 sim: Simplify boards and arch's Makefile
1.Remove the unused LIBPATHS and HOSTLDFLAGS
2.Move HOSTCFLAGS to arch/Makefile

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-01 12:33:56 +01:00
Masayuki Ishikawa
2a434fe1fa arch: imx6: Add the pgheap for imx6
Summary:
- This commit adds the pgheap for imx6

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-03-01 12:18:47 +08:00
Xiang Xiao
da954956e7 Simplify DEFAULT_SMALL usage in Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-01 03:15:01 +08:00
chao.an
0961f12e28 arm/phy62xx: remove unused private header
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-01 00:33:58 +08:00
Xiang Xiao
9bc2b4c31b board/sim: Remove CCLINKFLAGS, use CFLAGS/CXXFLAGS instead
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 23:13:22 +08:00
Huang Qi
d0356bb9ba arch/risc-v/qemu-rv: Set FS bits in mstatus
FPU test may fail without correct FS bits.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-28 16:28:22 +08:00
Masayuki Ishikawa
56e0e6a5ec arch: imx6: Remove sem_t from imx_serial.c
Summary:
- I noticed that when exiting getprime, DEBUGASSERT happens in
  nxsem_wait()
- Finally, I found that up_putc() uses nxsem_wait()
- This commit fixes this issue by removing the semaphore.
- Also, up_putc() now calls imx_lowputc()

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-28 16:09:01 +08:00
Masayuki Ishikawa
a75d905760 arch: imx6: Refactor imx_lowputc()
Summary:
- Remove '\n' -> '\r\n' conversion
- Remove waiting for FIFO empty after sending a character
- Remove CONFIG_DEBUG_FEATURES

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-28 16:09:01 +08:00
Xiang Xiao
872c570343 arch: Align the implementation of stack related functions
arm: Avoid call k[u]mm_memalign to save the code size
ceva: Correct stack_base_ptr usage(top of stack v.s. bottom of stack)
mips: Correct the stack alignment in up_use_stack
misoc: Correct the stack alignment in up_use_stack
or1k: Correct the stack alignment in up_use_stack

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 15:05:41 +08:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-28 15:05:41 +08:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
0c7517e579 arch: Remove the duplicated syscall.h in each arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
8b77801b1c arch/xtensa: Remove the unused SYS_pthread_exit
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
chao.an
b57e0b6118 arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-27 17:25:22 +09:00
chao.an
c369e47107 arm/armv7-a/r: handle swi on interrupt stack
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-27 17:25:22 +09:00
lp.xiao
fac10b6ebd stm32f103re has a dac module.but the pinmap file has no corresponding definition 2022-02-27 14:39:17 +08:00
Xiang Xiao
f634ea24b5 arch/sim: Don't include execinfo.h since cygwin doesn't support it
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-26 07:05:42 -06:00
Jiuzhu Dong
c5ba9261bc procfs: add memdump interface to dump used/free memory info
usage:echo <used/free> > /proc/memdump
echo used > /proc/memdump // output all used memory node info(address + size)
echo free > /proc/memdump // output all free memory node info(address + size)

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-02-26 14:32:42 +08:00
Xiang Xiao
b95022f8de arm/armv7-a: Remove CONFIG_SMP guard from arm_scu.c
since ACTLR.SMP need enable to make cache work on Cortex A7:
https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-26 14:15:30 +09:00
Gustavo Henrique Nihei
6a12befcd5 xtensa/esp32s2: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
d2ada5f030 xtensa/esp32: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
36ac532c98 risc-v/esp32c3: Fix Scheduler CPU Load feature using Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-26 03:23:13 +08:00
Gustavo Henrique Nihei
a6fea1c3a5 risc-v/esp32c3: Enable Timer Groups clocks on timer initialization
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 22:49:22 +08:00
Gustavo Henrique Nihei
1d15196df7 risc-v/esp32c3: Fix detection of CPU reset by Watchdog Timer
This commit fixes an issue where some peripheral clocks are being
disabled during CPU reset on ESP32-C3.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 22:48:09 +08:00
zhuyanlin
fbc1da98b7 xtensa: use swint to swith context
Reason for use sw-interrupt as syscall interrupt:
The xtensa `syscall` instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter `enter_critical_section` and gerenate
interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-25 20:43:03 +08:00
zhuyanlin
f5d180bbdf xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO
For up_irq_disable, use XCHAL_EXCM_LEVEL
For up_irq_save,  use XCHAL_IRQ_LEVEL.
Then we can use svcall in enter_crritical_section.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-25 20:43:03 +08:00
Huang Qi
e8552156b6 arch/risc-v: Remove unneeded ISA specifc interface
They are not really defined and used in any where:
uint32_t up_getmisa(void);
uint32_t up_getarchid(void);
uint32_t up_getimpid(void);
uint32_t up_getvendorid(void);
uint32_t up_gethartid(void);

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
cfed970633 arch/misoc: Correct gurad macro for irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Huang Qi
8b66280b4f arch/risc-v: Update outdated comments
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-25 20:36:16 +08:00
Gustavo Henrique Nihei
ea1b49119a xtensa/esp32s3: Apply minor fixes to documentation and code style
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
add99fead3 xtensa/esp32s3: Add support for Oneshot timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 10:51:25 +08:00
Masayuki Ishikawa
de95a8550f arch, board: Add thumb support to i.MX6
Summary:
- This commit adds thumb support to i.MX6
- Also, applies the same coding style to arch_elf.c

Impact:
- i.MX6 only

Testing:
- Tested with sabre-6quad:smp (QEMU, Dev board)
- Tested with sabre-6quad:netnsh (QEMU)
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-25 10:51:12 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-25 09:18:53 +09:00
Abdelatif Guettouche
dc130b4830 arch/xtensa/esp32s2_irq.c: Correctly enable the software interrupt.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-25 08:55:41 +09:00
Gustavo Henrique Nihei
b49ee3d4ed xtensa/esp32s3: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 02:13:00 +08:00
Anton Potapov
9603b8f67c Add DAC2 configuration for stm32f405. 2022-02-24 12:09:41 -05:00
Gustavo Henrique Nihei
3400b42a33 xtensa/esp32: Fix a minor typo in documentation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
a5024a707d xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-24 17:43:39 +01:00
Gustavo Henrique Nihei
83f3ba6d22 xtensa/esp32s3: Add support for Timer Groups 0 and 1
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 00:13:34 +08:00
zhuyanlin
7d350204f0 xtensa: fix XTHAL_REL_LE not find
fix `XTHAL_REL_LE` not find build break

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 22:13:46 +08:00
Xiang Xiao
6fa5885d2d arch/esp32: Update esp-wireless-drivers-3rdparty to verion 45701c0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 09:05:40 +01:00
zhuyanlin
fc9791c269 xtensa:esp32s3: setup software interrupt as swi interrupt.
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
zhuyanlin
bf40d70df9 xtensa:esp32s2: setup software interrupt as swi interrupt
Enable and setup software interrupt for esp32s2

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
zhuyanlin
7b32ce190e xtensa:esp32: setup software interrupt. (bit 29)
Enable and setup software interrupt.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-24 01:06:36 +08:00
chao.an
13889ba868 arch/arm: unify some duplicate code to common layer
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 21:35:55 +08:00
chao.an
6cc0aaf5b9 arch/arm: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
chao.an
db3a40ac25 arch/armv7-r: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
chao.an
61cd9dfca1 arch/armv7-a: unify switch context from software interrupt
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-23 15:04:29 +09:00
Gregory Nutt
1ded8bbabb Garbage configuration setting in EFM32 code
arch/arm/src/efm32/efm32_start.c:

      /* For the case of the separate user-/kernel-space build, perform whatever
       * platform specific initialization of the user memory is required.
      * Normally this just means initializing the user space .data and .bss
       * segments.
       */

    #ifdef CONFIG_NUTTX_KERNEL
      efm32_userspace();
      showprogress('E');
    #endif

But there is no CONFIG_NUTTX_KERNEL configuration setting.  Comparing this to other architectures it is clear this should be

    #ifdef CONFIG_BUILD_PROTECTED
2022-02-23 03:40:44 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-23 01:21:26 +08:00
zhuyanlin
7b00c8bdb8 arch:xtensa: modify svcall to swint
Reason: xtensa svcall only have level-1 interrupt level.
Sush do not generate interrupt when up_irq_save.
Software int can generate interrupt when up_irq_save.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-22 14:06:24 -03:00
chao.an
0aa0022b12 arch/armv7-a: replace SYS_signal_handler_return hardcode
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-22 17:59:02 +08:00
chao.an
e0fabbfdd6 arch/arm: replace SYS_syscall_return hardcode from syscall
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-22 17:59:02 +08:00
Xiang Xiao
2f24d2c265 arch/ceva: Replace OUTDIR with TOPDIR
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-21 09:25:26 +01:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
Oki Minabe
e9a94a003d old arm: add BUILD_KERNEL code in arm/arm_vectors.S 2022-02-20 21:03:54 +09:00
Oki Minabe
19e5c8f6d3 armv7-a/r: fix SVC's sp restore in arm_vectors.S 2022-02-20 18:39:30 +08:00
Xiang Xiao
d29f3bd21c arm/rtl8720c: Remove the unused Toolchain.defs
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 04:15:34 +01:00
Huang Qi
da25883c64 arch/sim: Fix usrsock build break on macOS
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 09:06:46 -03:00
chao.an
5da5ffb7d4 sim/usrsock: correct the xid type to uint64_t
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-18 08:16:17 +01:00
Abdelatif Guettouche
ab18b7b3d3 esp32xx_irq.c: Fix CPU interrupt documentation to remove the MAC
interrupt from the internal interrupt table.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
ee88235d81 esp32_irq.c: Don't reserve BT and Wifi CPU interrupts for APP CPU as
they are attached to the PRO CPU.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
17e43b0b4a esp32_irq.c: For internal interrupts use the current CPU to enable them.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Abdelatif Guettouche
3d2771c49a esp32_irq.c: Move interrupt initialisation for special drivers to
`up_irqinitialize`.  `esp32_cpuint_initialize` is not a good place as
it's also called from CPU1.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-18 13:40:21 +08:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
36ff081b1a risc-v: Support more than 2 cores in riscv_cpu_boot
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Huang Qi
7c18290331 risc-v: Rename up_fault to riscv_fault
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
lp.xiao
bc12260540 dp83848c ethernet phy interrupt support 2022-02-17 08:00:53 +01:00
Xiang Xiao
69a6072946 arch/ceva: Replace adj_stack_ptr with stack_base_ptr
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
814cab1cd1 arch/ceva: Mark the allocated stack with TCB_FLAG_FREE_STACK
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
f8df491d5d arch/ceva: Update tls handle to the latest mainline
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
Xiang Xiao
4bc5b246ac arch/ceva: Remove B2C and C2B
since TL420 doesn't support anymore, we
can safely remove the special hack for it

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-17 11:06:09 +09:00
YAMAMOTO Takashi
85af0f37ad arch/sim/src/Makefile: Fix build issues with clang on linux
This commit fixes at least two issues.

* Fix a build with clang on linux

```
/usr/bin/ld: cannot open linker script file nuttx.ld: No such file or directory
clang: error: linker command failed with exit code 1 (use -v to see invocation)
```

* Restore symbol renaming for clang on linux

I guess it actually depends on the linker.
For now, use CONFIG_HOST_MACOS.

This fixed the following crash seen with sim/linux built with clang.

```
    #135462 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135463 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135464 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135465 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135466 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135467 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135468 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135469 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135470 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135471 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520
    #135472 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
    #135473 0x0000000000402aed in exit (status=1) at task/exit.c:103
    #135474 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
    #135475 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
    #135476 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
    #135477 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
    #135478 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
    #135479 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
    #135480 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
    #135481 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520

```
2022-02-17 09:36:20 +08:00
YAMAMOTO Takashi
7fcfe40821 arch/sim/src/Makefile: Fix whitespace 2022-02-17 09:36:20 +08:00
Peter Kalbus
6abdf73535 sim: Initial support on MacOS M1 and Linux AARCH64 based hosts. 2022-02-17 09:35:09 +08:00
Xiang Xiao
1d963058b4 arch/sparc: Replace adj_stack_ptr with stack_base_ptr
since adj_stack_ptr doesn't exist anymore

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-16 17:19:43 -03:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
2022-02-17 02:55:25 +08:00
Oki Minabe
68a305438b fix armv7-a gtm.h GTM_COMP1 and GTM_AUTO defines. 2022-02-16 18:50:42 +01:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
Simon Filgis
cf008c94cc arch/arm/samv7: fix peripheral id shift during transmit xdma configuration 2022-02-16 17:16:53 +01:00
Masayuki Ishikawa
b60b6120de arch: armv7-a: Fix arm_syscall for SYS_pthread_start
Summary:
- I noticed that pthread always crashes when started
  if CONFIG_BUILD_KERNEL=y
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-16 13:06:25 +01:00
Petro Karashchenko
41c95da594 register_driver: fix driver modes accross the code
State of problem:
 - Some drivers that do not support write operations (does not
   have write handler or ioctl do not perform any write actions)
   are registered with write permissions
 - Some drivers that do not support read operation (does not
   have read handler or ioctl do not perform any read actions)
   are registered with read permissions
 - Some drivers are registered with execute permissions

Solution:
 - Iterate code where register_driver() is used and change 'mode'
   parameter to reflect the actual read/write operations executed
   by a driver
 - Remove execute permissions from 'mode' parameter

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-16 16:15:29 +08:00
Xiang Xiao
db57e2cd8e Fix the minor style issue
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 15:26:38 +01:00
Masayuki Ishikawa
34cf6949ac arch: armv7-a: Add debug messages for addrenv
Summary:
- This commit adds debug messages for addrenv

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 17:22:52 +08:00
Masayuki Ishikawa
e7cb1b4fb1 arch: rt8920c: Move -fno-common option to ARCHCFLAGS/ARCHCXXFLAGS
Summary:
- Apply the same style as sabre-6quad

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 16:27:53 +08:00
Xiang Xiao
6b02e32904 arch/sim: Remove 08 from the format string in up_vfork
to make the code more general for both x86 and x64.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Xiang Xiao
e1879e35cd arch/sim: Always typedef xcpt_reg_t to unsigned long
to simplify the code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 06:44:21 +01:00
Huang Qi
5cde8c6934 risc-v: Let g_cpu_basestack determined at compile time
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
Huang Qi
0d7f30c86d risc-v/k210: Move wfi to entry of the slave cpu boot routine
Fix another potential bug in non-smp case: load a value from overflowed address of g_cpu_basestack.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-15 11:40:34 +09:00
fenghang
555d25633a add phyplus_rel_1.4
update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files
2022-02-15 10:21:10 +08:00
Xiang Xiao
4207882cdc arm/armv8-m: Handle the special irq correctly in up_secure_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 09:45:34 +09:00
David Sidrane
1ca952243c stm32h7:flash can not use usleep
commit 328374f4658d11655f268f968f4c6c7a3942f320

   changed the wait to use usleep. This killed the
   write performace from the published values in the
   datasheet of ~100 us to 2 mS per 256 bits. On
   a 1000 per tick config. It can be 10 X worse
   on the default 100 per tick config.

   This changes uses up_udelay.
2022-02-15 02:09:04 +08:00
David Sidrane
8659a31c9d stm32h7:flash Fix lock violations 2022-02-15 02:09:04 +08:00
David Sidrane
8ca4cf49b1 stm32h7:Fix build for all config {R|T}XDMA states 2022-02-14 18:43:30 +01:00
Xiang Xiao
17a7d612df arch: Replace nx_vsyslog with vsyslog
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-14 09:41:45 -03:00
chao.an
4be416a2a8 arm/backtrace: fix the compile warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-14 16:29:38 +08:00
Huang Qi
b8477f857b k210: Use common cpu idle stack implementation
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
55d88627a0 risc-v: Implement common up_cpu_idlestack
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
raiden00pl
00917bfe9d stm32/fdcan: add CAN FD frames support 2022-02-14 10:42:01 +08:00
raiden00pl
dd8408a973 stm32/fdcan: use array indexes when accessing RX/TX FIFO 2022-02-14 10:42:01 +08:00
Michael Jung
70dae3bb3b Add arm_tcbinfo.c to stm32u5's common C sources
And re-order the list of common C sources alphabetically.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Michael Jung
5c1c939cdc stm32u5: Architecture Support for STM32U5
Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
2022-02-13 16:32:35 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Michal Lenc
56b3fc0ef9 arch/arm/src/samv7: added support for PWM driver
This commit adds initial support for PWM driver to SAM MCU series.
Only general PWM on PWMH output is currently supported, complementary
output on PWML is not allowed. The current state of the driver also does
not support external triggering of other perihperals.

Multichannel option is supported. The functionality of the driver was
tested on an example pwm application and with a real time control system.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2022-02-13 03:20:07 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-12 21:07:35 +09:00
Peter Kalbus
271518a5ff sim: detect clang native compiler on MacOS. 2022-02-11 21:23:07 +08:00
Huang Qi
3fe9c9523c risc-v: Fix style issue in SoC's Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-11 15:20:17 +08:00
Alan C. Assis
d49ad207ef esp32c3: Fix issue #5377 UART1 not working because clock as disabled 2022-02-11 10:01:25 +08:00
zhuyanlin
c833048484 xtensa:kconfig: move ARCH_HAVE_TESTSET config to chip
Some xtensa arch have not implentment testset instructions

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-10 14:22:58 +08:00
Huang Qi
7134220ae2 risc-v: Remove duplicated up_idle logic
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
9223547afc risc-v: Support cpu activity led in up_idle
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
Huang Qi
6f18747dc2 risc-v: Add WFI to up_idle and fix compile issue
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-10 13:09:32 +08:00
zhuyanlin
3ab65f9b08 armv7-a/r: use flush/clean_all if size large than cache size
For cache flush/clean performance

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
zhuyanlin
4eba2f3527 armv7-a/r:cache: add cp15_cache_size function
Add cp15_cache_size function for armv7-a/r

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-09 18:16:31 +01:00
Huang Qi
9d91d69ee0 arch/risc-v/mpfs: Remove riscv_pthread_exit.c in Make.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit"
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Alin Jerpelea
0cfdfde6c7 arch: sim: update licenses for FishSemi
FishSemi is part of Xiaomi and according to xiaoxiang781216
the SGA covers those files

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
7a674b6287 Makefiles: change license to Apache
Make files are recipes based on contributions from from Gregory Nutt

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
Alin Jerpelea
e2725d536a arch: sim: update licenses to Apache
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-02-09 19:58:52 +08:00
zhuyanlin
cc8ab23550 armv7-r/a: fix a4 register use in xxx_invalidate/flush/clean_all.S
Use sub loop instead of add loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-08 19:39:43 +09:00
SPRESENSE
8de07b2ae8 boards: cxd56xx: audio: Support I2S input
Enable the driver setting of I2S input.
2022-02-08 10:47:03 +01:00
Xiang Xiao
963feca4a1 arch/sim: Don't add up_tls_size in up_use_stack before foward to up_create_stack
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 08:45:34 +01:00
Xiang Xiao
202b8141a6 arch/sim: Adjust the stack size for up_use_stack too
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 13:36:51 +08:00
Xiang Xiao
5749ea6604 arch/sim: Unify the return value of usrsock_xxx_handler
All handler should return the result of usrsock_send_[dack|event]

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 13:18:19 +08:00
raiden00pl
bc178344a9 net/can: add an option to control CAN EXTID support 2022-02-06 17:09:11 +08:00
raiden00pl
341bbe38d5 arch/stm32: add FDCAN SocketCAN support 2022-02-06 17:09:11 +08:00
Petro Karashchenko
e545c440f4 arch/arm/samv7/sam_progmem: insert DMB instruction into data write loop
This change fix the regression that was introduced with
https://github.com/apache/incubator-nuttx/pull/4904

In case if D-Cache in configured in Write-Through mode there is
Cortex-M7 erata 1313001 that describes a situation when linefill
buffer or cache contains stale data. Even if progmem write loop
does not fully matches the description there is a possibility
to program stale data if there is no DMB instruction after each
write operation to progmem latch buffer.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-05 03:14:07 +08:00
Petro Karashchenko
47a09ed255 arch/arm/samv7: add arm_systemreset.c to CMN_CSRCS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-02-04 16:40:50 +08:00
Abdelatif Guettouche
f826e053ae arch/xtensa/esp32: Remove the QEMU special case when initializing the
heap.

QEMU had a different ROM image that used the regions of PRO CPU for both
CPUs.  This was causing crashes when running SMP mode as the heap was
being corrupted when the APP CPU starts.

QEMU is now loading the same image as the hardware chip and thus this
special case doesn't exist anymore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-02-03 16:18:09 -03:00
chao.an
3ab557e748 arch/xtensa: correct the netlock handling
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-03 11:09:18 -03:00
chao.an
ed4f852073 arch/arm: correct the sched_lock/spin_lock handling
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-03 11:09:18 -03:00
zouboan
ad3f16358e enable sparc's daily ci and eliminate some warnings 2022-02-03 14:43:21 +01:00
chao.an
0be55bef64 arch/renesas: fix nxstyle warning
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
chao.an
8e004839b6 arch/renesas: fix leaving from critical section
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
chao.an
d59931159a arch/arm: fix leaving from critical section
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-02-02 21:45:13 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
Xiang Xiao
f987668068 serial: Consolidate the general termios in the common place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-01 21:22:21 -03:00
zouboan
95542f193b sparc adaptive patch 2022-02-01 17:16:21 +08:00
Petro Karashchenko
601a0e8a32 arch/arm/samv7: fix leaving from critical section in HSMCI callback
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-31 16:56:52 -03:00
Abdelatif Guettouche
f49a579721 esp32c3/: Remove unused exported variables from ROM and add declaration
for the one used.
2022-01-31 23:35:50 +08:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-30 11:04:35 +09:00
David Sidrane
0f1342f36b stm32:Add OTG ID GPIO disable 2022-01-30 01:50:37 +08:00
David Sidrane
99083b8dd1 stm32{f|h}7:Fixed typo in Kconfig help 2022-01-30 01:49:57 +08:00
chao.an
7d8c2c1ad6 cortex-m/doirq: do not update the CURRENT_REGS on nested interrupt handling
current implementation incorrectly update CURRENT_REGS to interrupt context if
trigger nested interrupt, (e.g, hard fault occurs during interrupt handling)
this would ambiguous for programs using CURRENT_REGS, this patch will prohibit
the update of CURRENT_REGS on nested interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-29 01:04:00 +08:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-28 12:02:38 +01:00
Alexander Lunev
b2f3cefe3d sim/netdev,tapdev: implemented emulation of TX done and RX ready interrupts
and removed two tcp_send_txnotify() calls from tcp_sendfile (they are not needed anymore).

As a result, the TX throughput of both the tcp_send_buffered and tcp_send_unbuffered
is significantly boosted in case of TUN/TAP network device.
2022-01-28 18:16:42 +08:00
Gustavo Henrique Nihei
b0d24f53c4 xtensa: Add initial support for ESP32-S3
Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00
Fotis Panagiotopoulos
f8ba016d72 sim: Added Kconfig option for UART buffer size. 2022-01-27 17:15:17 +01:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Petro Karashchenko
0ffffe19b1 typo: change evernt to event in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-27 09:57:31 -03:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
2022-01-27 10:22:30 +01:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error.
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
2022-01-27 15:13:08 +08:00
Petro Karashchenko
311efcd180 arch/z80: fix garbage collector option to linker
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-26 16:50:59 +08:00
Petro Karashchenko
48211f90d3 ci: select ARMV7A_TOOLCHAIN_GNU_EABIL for ARMv7-A based builds
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-25 20:24:28 +08:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine
This way old PMP configurations are removed upon warm reset.
2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Masayuki Ishikawa
7b1cf2dfac arch: arm: Fix make export for armv7-a SoCs
Summary:
- I noticed that make export does not work with swama5d4-ek:knsh
- This commit fixes this issue.
- NOTE: apps/Makefile also needs to be updated.

Impact:
- CONFIG_BUILD_KERNEL=y only

Testing:
- Build (make and make export) with sama5d4-ek:knsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-01-25 11:05:22 +08:00
Jukka Laitinen
49085eebae arch/risc-v/src: Cleanups for opensbi
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
5bb3936212 arch/risc-v/src/opensbi: Update 3rd party opensbi version into Make.defs
This fixes build errors with more strict compiler settings

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
8a6d62423d Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit d611e2d99b.
2022-01-25 00:10:46 +08:00
Eero Nurkkala
eb462a2eb3 risc-v/mpfs: configure harts according to CONFIG_MPFS_HART*_SBI
The following options need to be taken in account while determining
the proper hart_index2id -table:
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART3_SBI
  CONFIG_MPFS_HART4_SBI

Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Huang Qi
71d3ff1045 arch/risc-v: Remove g_serial_ok
`WFI` is enough to wait the ready signal from master core,
so we can remove it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Huang Qi
422e005183 arch/risc-v: Move xxx_cpustart.c to common
It's a common solution for MSIP and IPI based risc-v smp soc,
also works on qemu-rv smp (WIP).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Norman Rasmussen
da5659138b Fix regression where used code was marked as unused
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
2022-01-23 14:57:19 +08:00
raiden00pl
4c2dd3924a include/nuttx/can.h: rename CAN_ERR_CTRL to CAN_ERR_CRTL for compatibility with libcanutils 2022-01-23 01:34:34 +08:00
Petro Karashchenko
6c27f3c19d toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 15:36:29 +08:00
Alexander Lunev
f73abc76d5 sim/netdev: retrieve all the queued RX frames from the network device on every poll.
As a result, the RX throughput is increased significantly w/o harming the TX throughput.
2022-01-22 15:34:58 +08:00
Xu Xingliang
021363f1db driver/mmcsd: add option to limit block count in multiple-block transfer mode.
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2022-01-22 14:59:26 +08:00
Petro Karashchenko
d611e2d99b risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 14:58:56 +08:00
Huang Qi
b803919b9d arch/risc-v: Merge mcause.h into irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-22 14:57:05 +08:00
Jukka Laitinen
9061c92ec8 arch/risc-v/src/mpfs: Make each hart entry configurable for bootloader
Add two config flags for each hart for a bootloader nuttx:

CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.

CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
  from SBI if CONFIG_MPFS_HARTx_SBI is set

This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Jukka Laitinen
36b73fd0a3 arch/risc-v/src/mpfs/mpfs_opensbi.c: Ensure stack alignment of 16 bytes
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Eero Nurkkala
2a22c0e32d risc-v/mpfs: OpenSBI: utilize an index2id table
Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-21 13:40:58 -03:00
Abdelatif Guettouche
8c582c27b8 esp32c3_irq.c: Add a comment explaining the assigment of CURRENT_REGS to
regs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Abdelatif Guettouche
e335d44028 esp32c3_irq.c: Skip over ECALL instruction.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Petro Karashchenko
a32381ca32 Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit 1dccc374ab.
2022-01-21 21:38:31 +08:00
YAMAMOTO Takashi
f356ff34a7 arch/sim/src/sim/up_macho_init.c: Fix an assertion
Handle the case of no constructors.
2022-01-21 11:01:53 +01:00
Petro Karashchenko
1dccc374ab risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-21 17:12:22 +08:00
zouboan
0342272e5a up_progmem_erasesize for stm32f20xxf40xx_flash.c 2022-01-21 14:57:32 +08:00
Huang Qi
d846bb0235 arch/risc-v: Remove dupped irq code from mpfs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f arch/risc-v: Remove dupped irq code from rv32m1
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090 arch/risc-v: Remove dupped irq code from litex
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5 arch/risc-v: Remove dupped irq code from c906
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c arch/risc-v: Remove dupped irq code from bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc arch/risc-v: Remove dupped irq code from qemu-rv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e arch/risc-v: Unify common irq code to arch/irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Xiang Xiao
2935751bfd Fix error: implicit declaration of function 'up_cpu_index'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
aa2cdcd848 xtensa/esp32: Change "cpu <= CONFIG_SMP_NCPUS" to "cpu < CONFIG_SMP_NCPUS"
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
04297c3ca3 board: Remove -fno-omit-frame-pointer from Make.defs
except sim arch, since this flag is set inside Toolschain.defs now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Ville Juven
0a1a1e9b79 Fix user PGT flags (don't map them globally)
A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31 Add pte getter to RISC-V MMU driver
Like the title says, a getter to read one PTE.
2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937 RISC-V MMU driver: fix region setting for L1/L2 page tables
The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
2022-01-20 20:30:13 +08:00
Ville Juven
e676d2985d Present common MMU flags in common MMU driver header
Flags to use for intermediate page tables, as well as leaf entries
2022-01-20 20:30:13 +08:00
Ville Juven
33435e76da Changes to Sv39 MMU driver public header
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
  combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
2022-01-20 20:30:13 +08:00
Ville Juven
926a19217e Add simple MMU driver for RISC-V (Sv39)
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.

The driver is tested with mpfs only, but it should work with any riscv
implementation.
2022-01-20 20:30:13 +08:00
Eero Nurkkala
133faf203d risc-v/mpfs: don't reset uart1 while entering OpenSBI
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-20 18:37:08 +08:00
Eero Nurkkala
54a4eb01ce risc-v/mpfs: avoid OpenSBI redefinition conflicts
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-20 18:37:08 +08:00
Xiang Xiao
67fc54dd3d boards/sim: Change CONFIG_LIBCXX to CONFIG_HAVE_CXXINITIALIZE
since the contructor is required with other libc++ implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:20:41 +08:00
Xiang Xiao
af7fd718cc arch/sim: Don't add -lc++abi to STDLIBS
link libs/libxx/libcxxabi instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:20:41 +08:00
YAMAMOTO Takashi
10f7ad85e6 arch/sim/src/nuttx-names.in: Add mprotect and sysconf
For up_macho_init.c.
2022-01-20 15:09:17 +08:00
YAMAMOTO Takashi
f0acf8e62a arch/sim/src/sim/up_macho_init.c: Add a workaround for Monterey 2022-01-20 15:09:17 +08:00
Petro Karashchenko
08043fb5bc net: unify FAR keyword usage for all net buffer memory mapped buffers
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-20 01:42:56 +08:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Jukka Laitinen
6428c1fdc4 arch/riscv/mpfs: Switch to use riscv_exception_common
Clean up mpfs port by using the common code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Jukka Laitinen
7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
  support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
  only on one hart, but the startup code executes on all harts and handles SW IRQs

Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Petro Karashchenko
767cf282c7 boards/arm/samv7: move HSMCI interface to common
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-20 01:24:14 +08:00
yinshengkai
face0514b6 touchscreen: update sim_touchscreen, using touch_upperhalf
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-01-20 01:22:25 +08:00
YAMAMOTO Takashi
a94c52b204 sim: Postpone constructor calls on macOS
For Linux, we rename the section so that they are not invoked.
However, it doesn't work for macOS.

Notes:

* Renaming the sections (as the Linux version does) doesn't work
  because the section is looked by its flags, not by its names.

* No convenient tools available to alter the relevant bit in
  the section flags.

* The constructors are invoked before the program entry point.
2022-01-20 01:16:56 +08:00
Daniel Agar
12c8a9626c stm32f7 serial fix PM_CONFIG build 2022-01-20 01:08:06 +08:00
zhuyanlin
793ec6c909 arch:xtensa:vectors:fix bugs in a0 save
Use right EXCSAVE_X

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
a1a9ce3d1e arch:xtensa_panic: use right interrupt pointer in xtensa_panic
When enable interrupt stack, use a12 instead of sp

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
88f5a209ce xtensa: move a3 save in handler instead of _xtensa_context_save
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
561fa88ed1 xtensa: add svcall handler
svcall.c for xtensa

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
zhuyanlin
662f071d9a xtensa: fix svccall enter error
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-19 16:28:03 +01:00
Petro Karashchenko
a6147109b1 arch/arm/src/armv6-m: fix typo
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-19 15:32:58 +01:00
Xiang Xiao
8bcdefafc9 board: Remove -fno-strength-reduce
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-19 00:14:03 +01:00
ligd
0a51f13ca5 rpmsg_rtc: merge the rpmsg_rtc_init to same place
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-18 22:48:15 +08:00
Petro Karashchenko
9551de7115 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-18 10:59:47 +01:00
Gustavo Henrique Nihei
04723a89f2 xtensa: Fix core voltage level when SPI Flash runs at 80Mhz
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-18 02:21:46 +08:00
raiden00pl
e140ba1a21 arch/stm32: fdcan cosmetics 2022-01-17 09:36:00 -03:00
raiden00pl
c450dea6e5 stm32: add FDCAN support
based on PR #2987
2022-01-17 09:36:00 -03:00
Petro Karashchenko
4f98ac4879 arch/arm/samv7: implement quadrature encoder driver
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-17 09:35:12 -03:00
zouboan
74aeb5d0c5 port nuttx to sparc-v8 commit
includes following parts:
add support of sparc in arch/Kconfig
add support of sparc in boards/Kconfig
add sparc dir in arch, add sparc dir in boards
add support of sparc in libs/libc/machine
modify all the coding style problem about saprc
2022-01-17 09:09:29 -03:00
Huang Qi
676d35f007 risc-v: Make exception_common 8 byte align
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-17 11:44:50 +08:00
Huang Qi
e97ba17451 arch/risc-v: Refine riscv_cpupause.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-16 23:11:32 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
Xiang Xiao
41b9cf3cd8 rtc/rpmsg: Add sync parameter to control whether call clock_synchronize
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-16 11:58:13 +01:00
Xiang Xiao
93b0b9678f sim: Forward /dev/rtc0 operation to rpmsg rtc driver
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-16 11:58:13 +01:00
Huang Qi
3200c936cc arch/risc-v: Refine riscv_cpuindex.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 21:54:05 +08:00
Huang Qi
56a95ad0b5 risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Huang Qi
74cce59ac6 arch/risc-v: Make ISA configurable for qemu-rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Alan C. Assis
dfd972a534 z80: Fix z80sim build system 2022-01-15 11:37:28 +08:00
chao.an
3544fc1fd6 risc-v/assert: add CURRENT_REGS check to avoid null pointer reference
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-15 02:20:01 +08:00
chao.an
c27839f98e arm/xtensa: save the running registers to xcp context
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-15 02:20:01 +08:00
Alexander Lunev
019fc0ad78 sim/netdev: eliminated RX data stream congestion in case of high TX network traffic.
In case of high TX network traffic, netdriver_loop() that reads data from netdev
was invoked via up_idle() only after high TX network traffic had stopped.
That resulted in massive delay and drop of TCP ACK packets and
any other packets from netdev (tun/tap device).
2022-01-14 19:39:39 +08:00
Eero Nurkkala
09bf8a5f89 risc-v/mpfs: mpfs_opensbi: fix fw_size calculation
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.

Also add the next_arg1 initialization.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Jukka Laitinen
122b907b91 arch/risc-v/src/mpfs/mpfs_opensbi_utils.S: Remove unncessary mv
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-14 10:10:24 +01:00
Jari van Ewijk
3aed0aa641 S32K1XX: implement uniqueid 2022-01-13 15:34:47 -08:00
Huang Qi
6f1011a85e arch/risc-v: Rename bl602_entry.S to bl602_head.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 22:06:49 +01:00
Gustavo Henrique Nihei
c372e1e295 xtensa: Fix typo in xchal_cpX_store macros' invocation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-13 21:07:04 +01:00
Huang Qi
7c93e96908 arch/risc-v: Fix typo in riscv_assert.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Huang Qi
3c15ae23cf arch/risc-v: Make __tarp_vec 4 byte align
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-13 14:53:18 +01:00
Alan C. Assis
7b32849b84 esp32s2: Fix data cache option in menuconfig 2022-01-12 21:45:04 +01:00
Gustavo Henrique Nihei
80436dd7be xtensa/esp32s2: Fix some wrong definitions related to IRQ management
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-12 21:28:40 +01:00
Jari van Ewijk
0fc613f0b3 S32K1XX Reset Cause PROCFS: Add Kconfig option and cleanup 2022-01-13 01:29:42 +08:00
Huang Qi
e47a915f4c arch/risc-v: Refine riscv_vectors.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-12 18:53:01 +08:00
Xiang Xiao
1b77ae88ef fs/procfs: Remove the unnecessary strcmp
since the procfs already make the same check for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-12 07:19:40 +01:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-11 23:24:33 +08:00
Gustavo Henrique Nihei
efca63e9e3 xtensa/esp32s2: Fix missing parenthesis on macro expression
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-11 23:21:13 +08:00
ligd
3cfc6761ff xtensa: fix lack of float register save & resotre
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-11 12:17:09 +01:00
Petro Karashchenko
a743fed63d file_operations: get back C89 compatible initializer
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-11 02:14:00 +08:00
Alan C. Assis
2079cc0f6e esp32: Add support to RS485 2022-01-10 10:49:16 +08:00
Petro Karashchenko
1fd51ccbe2 arch/arm/samv7: rework SAMv7 timer counter implementation
There are two issues that are addressed with this change:
 - According to SAM E70/S70/V70/V71 Family datasheet the
   timer counter channels are 16-bit so timer counter
   value should be changed from uint32_t to uint16_t
 - The interrupt handling for timer counter channels can
   be simplified

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-09 17:43:31 +08:00
Xiang Xiao
bbf5511e3a arch/sim: Move the dummy ioe driver to drivers/ioexpender
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-09 11:06:06 +08:00
Xiang Xiao
b054bd9d37 arch/sim: Move the dummy foc driver to drivers/motor/foc
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-09 11:06:06 +08:00
Alan C. Assis
4ca38c6c50 esp32: Add PWM support using the LEDC peripheral
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-08 14:46:51 +01:00
Petro Karashchenko
e7f9c7af21 typos: fix typos in Kconfig files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-08 06:46:26 -03:00
Gustavo Henrique Nihei
73ea0c1627 xtensa: Improve Kconfig description of ESP32-S2 arch family
Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are
composed of a single Xtensa LX7 core.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-07 22:25:05 +01:00
Xiang Xiao
3156a96a1b arch/sim: Move qspiflash simulation to drivers/spi instead
since it's common implementation can be used in other arch too

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-07 23:50:11 +08:00
Xiang Xiao
d296f9c085 arch/sim: Move spiflash simulation to drivers/spi instead
since it's common implementation can be used in other arch too

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-07 23:50:11 +08:00
ligd
ee916bdb91 CEVA: add ceva platform xc5 xm6 support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-01-07 09:31:59 -03:00
Xiang Xiao
49c00e0361 arch/sim: Rename up_vfork[32|64].S to up_vfork_x86[_64].S
to follow other arch/x86 arch/x86_64 convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-07 15:59:34 +08:00
Xiang Xiao
1a02556265 Revert "arch/sim: Rename up_vfork[32|64].S to up_vfork_x[32|64].S"
This reverts commit 3982296294.
2022-01-07 15:59:34 +08:00
chao.an
8c35d31808 Kconfig: Remove CONFIG_ prefix from config definition
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-01-07 13:16:18 +08:00
Xiang Xiao
3982296294 arch/sim: Rename up_vfork[32|64].S to up_vfork_x[32|64].S
to align with up_vfork_arm.S naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-06 09:42:44 +01:00
raiden00pl
6fe95d8314 stm32: add SocketCAN support, based on stm32_can.c 2022-01-05 06:16:41 -08:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
2022-01-05 21:36:44 +09:00
raiden00pl
5b9b3814f8 stm32: add CAN error support 2022-01-05 18:33:06 +08:00
Jukka Laitinen
9aea5d5dbb arch/risc-v/src/mpfs/mpfs_serial.c: Correct setting of nbits
Number of bits was set wrongly in TCSETS for mpfs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-05 12:21:38 +08:00
Huang Qi
3a0e86c99b arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 23:22:43 +08:00
Eero Nurkkala
c87ae33459 risc-v/opensbi: update to version 1.0
OpenSBI recently introduced version 1.0. Use the latest
version here as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-04 15:50:25 +08:00
Huang Qi
845168ce12 arch/risc-v: Refine riscv_assert.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 14:46:24 +08:00
Huang Qi
a6662c2887 arch/risc-v: Refine arch.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-04 14:46:24 +08:00
Abdelatif Guettouche
4edc5fb701 xtensa: Rename up_stack_color to xtensa_stack_color since it's an
internal function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-04 02:45:45 +08:00
Petro Karashchenko
4b190fbce1 arch/arm/samv7: correct number on interrupts
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 22:10:22 +08:00
Petro Karashchenko
6c2b40f98a typos: fix typos in many files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 22:10:07 +08:00
Gustavo Henrique Nihei
c04fbb0365 risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Gustavo Henrique Nihei
78362b0949 xtensa/esp32: Use ROM implementations of libc functions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-03 10:37:04 -03:00
Petro Karashchenko
c7d3a674fd drivers/sensors/as5048b: fix lower half init issue
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-03 11:38:44 +08:00
Xiang Xiao
d2309195da boards/sim: Add vncserver config for test
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-03 11:19:32 +08:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-02 20:50:30 +01:00
Huang Qi
b11e90f384 arch/risc-v: Refine riscv_initialstate.c
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei
c1fac720ec xtensa/esp32: Add missing param documentation for SPI Flash function
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Gustavo Henrique Nihei
f130d8b91e xtensa/esp32s2: Remove unavailable support for ROM Basic Console
This feature is only available for ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Gustavo Henrique Nihei
74c02fbadb risc-v/esp32c3: Remove unavailable support for ROM Basic Console
This feature is only available on ESP32 chips.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-31 00:56:08 +08:00
Huang Qi
33df35f003 arch/risc-v: Correct epc adjustment with C ISA
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 22:54:17 +09:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-30 16:57:40 +08:00
Gustavo Henrique Nihei
80da9abd6a xtensa/esp32: Move assertions after logging to improve debugging
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
b6addaa4c7 xtensa/esp32: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Gustavo Henrique Nihei
340e0c8a8f xtensa/esp32: Build MCUboot bootloader with Flash Encryption support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-30 12:35:41 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Huang Qi
2de22980e5 arch/risc-v: Refine syscall interface
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-30 11:47:42 +08:00
Norman Rasmussen
091322ba4a Add backtrace to risc-v common sources 2021-12-30 01:30:08 +08:00
Xiang Xiao
b92c90ee81 arch/arm: Fix rebase error in arm_backtrace_thumb.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 20:42:05 +08:00
Huang Qi
c15195b126 arch/risc-v: Refine riscv_testset.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 06:06:01 -06:00
Xiang Xiao
228442ee23 arch/renesas: Undefine macro B0 to avoid the confliction
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 08:11:08 -03:00
Huang Qi
901361be48 arch/risc-v: Move more files to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
Huang Qi
22ae2e0121 arch/risc-v: Refine riscv_fpu.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-29 01:19:30 -06:00
ChenWen
6ce335fa84 xtensa/esp32: Fix some Wi-Fi issues
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
    2. Update Wi-Fi driver code to fix issue of failure to send pkt.
    3. Replace software random with hardware random
2021-12-28 23:48:25 -06:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 23:47:10 -06:00
Xiang Xiao
186ac17f1f arch: Select ARCH_HAVE_BACKTRACE in Kconfig for supported arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 13:34:02 +08:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 12:09:54 +08:00
Xiang Xiao
f302e8fd40 arch/sim: Implement up_backtrace
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-29 11:03:08 +08:00
Xiang Xiao
f061766801 video/fb: Fix typo error in include/nuttx/video/fb.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-28 17:21:18 -03:00
Huang Qi
e75321e61c arch/risc-v: Move riscv_blocktask.c to common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 11:32:15 -06:00
Norman Rasmussen
934a79736a Use userspace chosen channel numbers when starting bl602 pwm
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
2021-12-28 06:27:51 -06:00
chao.an
cf2dfa8985 arch/arm/assert: move the arm_assert to common code
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 05:09:30 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
chao.an
579738c8fa arch/arm: move the backtrace implement to common code
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-28 03:02:01 -06:00
Norman Rasmussen
1e2f067181 pwm: add option to break the loops when using multiple PWM channels
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
2021-12-28 03:01:27 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
chao.an
8eb999ff03 arch/arm: select ARM_THUMB by default for Cortex-M
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:30:53 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
Huang Qi
0751bcd4ca arch/sim: Support vncserver as display device
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-24 11:59:43 -06:00
Alan C. Assis
01e4e249cc Add WiFi/BLE Coexistence support
Co-authored-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Co-authored-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-23 20:42:23 -06:00
chao.an
6069433d2d arch/arm/cortex-a/r: dump all registers with alias
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-23 06:54:32 -06:00
Eero Nurkkala
3394dca826 risc-v/opensbi: Make.defs: use a wildcard for file listing
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-23 02:42:09 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
David Sidrane
74e692b3c1 stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite
For FAT the same buffer is used for read and writes, there
  is a possibility a cache line is dirty. But the fs is
  not dirty and will not write the sector to disk. This can
  be seen  https://github.com/PX4/NuttX/pull/175

  When the system is busy that cache line can be evicted after the
  RX DMA has completed and overwrite the data in memory. The solution
  is to invalidate before the DMA to prevent an evection causing an
  overwite, and after the DMA it to insure coherency.
2021-12-22 20:44:04 -06:00
chao.an
fe2830ec94 xtensa: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
362fe2c6f8 arch/risc-v: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
chao.an
a0b61bbf6f arm/cortex-a/r: enhance the task dump
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-22 11:46:02 -03:00
Abdelatif Guettouche
4f0dd95fe1 arch/Kconfig: Add HAVE_SYSCALL_HOOKS configs to Xtensa arch.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-22 06:26:36 -06:00
Xiang Xiao
b03886415f sim/netdev: Update IFF_RUNNING flag by netdev_carrier_on and netdev_carrier_off
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-22 07:15:00 -03:00
chao.an
2737701996 cortex-m/hardfault: add secure-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 07:08:13 -06:00
ChenWen
6d165506d5 risc-v/esp32c3: Initialize rtc and peripheral parameters by default when chip starts 2021-12-21 10:03:58 -03:00
Gustavo Henrique Nihei
c471f0fe96 risc-v/esp32c3: Remove deprecated note about Flash Detect feature
Flash Detect option is already available on esptool.py installed via pip

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
1c8e84b341 risc-v/esp32c3: Add Secure Boot support on top of MCUboot
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
f542ab4564 xtensa/esp32s2: Add Secure Boot support on top of MCUboot
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
d22a2aa7a0 xtensa/esp32: Refactor makefiles for compliance to Function Call Syntax
According to Make documentation:
- "Commas and unmatched parentheses or braces cannot appear in the text
  of an argument as written";
- "Leading spaces cannot appear in the text of the first argument as
  written".

Although in the current state it was not resulting in parsing issues, it
is better to fix it.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Gustavo Henrique Nihei
6c3223289f xtensa/esp32: Add Secure Boot support on top of MCUboot
This adds the capabitlity of building signed images on NuttX.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-12-21 07:02:40 -06:00
Juha Niskanen
54b652235c Update arch/Kconfig
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
2021-12-21 03:26:16 -06:00
Juha Niskanen
422ceec99b Fix typos in comments and Kconfig files
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-21 03:26:16 -06:00
chao.an
287348475c sim/usrsock: increase the sim usrsock buffer size
1. Increase the sim usrsock buffer size:
arch/sim/src/sim/up_usrsock.c

2. Fix build break
arch/sim/src/sim/up_usrsock_host.c

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-21 00:53:31 -06:00
Simon Filgis
6cc48ff6ff arch/arm/samv7: initial support for LIN bus communication
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 18:23:05 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:02:12 -03:00
Petro Karashchenko
67d8a82393 Kconfig: fix non-string default values uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-20 00:10:57 +01:00
David Sidrane
e269b5fa28 Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working."
This reverts commit 0aecfe8691.
2021-12-19 01:40:35 -06:00
chao.an
c1c1882783 sim/usrsock: Reuse all addresses to avoid bind fail
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-18 13:15:46 -06:00
raiden00pl
87a8b1bed9 nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832 2021-12-18 12:27:59 -06:00
raiden00pl
f3fdd5a019 arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice 2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4 arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected 2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79 arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes 2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support 2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0 arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device 2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines 2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018 arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex 2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6 arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset 2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13 arch/arm/src/nrf52/Kconfig: fix typos 2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2 arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types 2021-12-17 12:35:17 -06:00
Jiuzhu Dong
5a22d33475 up_putc: do up_putc when enable CONFIG_ARCH_LOWPUTC
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-12-17 11:43:08 -06:00
raiden00pl
07d295b8db add 5-Clause Nordic License barrier for Nordic SoftDevice Controller 2021-12-17 11:22:39 -06:00
xiewenxiang
b1d051b651 riscv/esp32c3: Initialize the BLE Mac 2021-12-16 22:31:02 -03:00
Gerson Fernando Budke
2dd5578d50 arch/arm/src/samv7/Kconfig: Define mem sizes
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691 stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode.
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
2021-12-16 01:28:05 -06:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-15 12:00:35 -06:00
chao.an
56ef1419dd arch/xtensa: set the current reg before print syslog
ensure the semantics of the up_interrupt_context() works as expected

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
2fe06ac083 arch: xtensa: save current SP before overwrting
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
chao.an
93b133fe66 arch/xtensa: correct the interrupt stack on irq handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-14 21:40:03 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Jiuzhu Dong
6b5a7a73ba sim: add CONFIG_SIM_STACKSIZE_ADJUSTMENT to reduce variability
between sim and other different platform stack size setting

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-12-13 21:15:30 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 08:31:13 -06:00
Abdelatif Guettouche
d31a0d8aca arch/xtensa/esp32: Show CPU activity on IDLE task and on interrupts.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
Abdelatif Guettouche
6262f7e99a esp32_idle.c: Change private function's name to start with esp32_
instead of up_.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-13 08:30:58 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-12 21:40:29 -06:00
lupyuen
2a87b37a69 riscv/bl602: Swap SPI MISO and MOSI 2021-12-12 20:40:49 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-12 10:19:00 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support
Signed-off-by: Huang Qi <no1wudi@qq.com>
2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-12-07 23:28:54 -06:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
raiden00pl
54e3b148e9 arch/sim/src/sim/up_assert.c: fix implicit declaration warning 2021-12-07 07:51:44 -06:00
anjiahao
9d6c92f0fa arch:move debug.h form headfile to c file
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2021-12-07 04:01:27 -08:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-06 00:47:58 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash
This can fix BLE assert when erase SPI Flash.
2021-12-06 13:13:11 +09:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-06 11:23:58 +09:00
Abdelatif Guettouche
50d217a9e8 esp32_cpustart.c: Improve comments around the usage of the inter-cpu
startup handshake.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Abdelatif Guettouche
b34951e3a0 esp32_cpustart.c: Remove the CONFIG_SMP condition on some part of code
because the whole file is only built if CONFIG_SMP is enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-12-02 11:21:49 -06:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0]
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-27 06:17:45 -06:00
Abdelatif Guettouche
251b8a3445 esp32xx_rtc: Include "clock/clock.h" to have a declaration of
g_basetime.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Abdelatif Guettouche
af11cf6cd1 esp32xx_rtc.c: Fix a duplicated assignment.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-26 15:23:47 -03:00
Dong Heng
66023da10c risc-v/esp32c3: Refactor ADC calibration
Use calibration parameters from efuse rather than self-calibration.
2021-11-26 15:23:24 -03:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-11-26 08:47:08 -06:00
Xiang Xiao
e30a5f3790 arch/sim: Add new option to enable arch specific hostfs
we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-25 14:42:23 +01:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
2021-11-24 20:38:23 -06:00
Jani Paalijarvi
4dfd3c9160 arch/riscv: Add ARCH_HAVE_SPI_CS_CONTROL for mpfs
Make it possible to override SPI CS function in board logic

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Lee Lup Yuen
6e68d55f8a Fix GPIO output 2021-11-24 06:48:50 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:48:00 -06:00
chao.an
0f76ff42eb arch/sim: add arch elf define
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
chao.an
4c76c356ef arch/arm: add more arch elf define
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-11-23 20:34:56 +09:00
Abdelatif Guettouche
65db787eff esp32_irq.c: Fix retrieving IRQ number and peripheral ID when it comes
to GPIOs in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-22 11:41:10 -06:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-11-18 19:27:07 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2021-11-18 10:59:44 -03:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-17 08:59:14 -03:00
zhuyanlin
ffb543d061 xtensa: add setjmp.h include file
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-17 02:23:45 -06:00
zhuyanlin
0e002af323 xtensa_backtrace: fix typ error
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-17 01:47:26 -06:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
2021-11-16 14:45:03 -03:00
Eero Nurkkala
6db480a7f9 mpfs: emmcsd: boost waitresponse perf
When waiting for a response to a sent command, the command
complete bit (MPFS_EMMCSD_SRS12_CC) should always guarantee
the completion of that particular command. There's no need
to have some combinations skipping the check of the command
complete bit. Thus, remove the 'waitbits' parameter as it's
unnecessary.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-16 10:25:57 -06:00
Dong Heng
92eedd93a7 risc-v/esp32c3: Fix reset triggering crash nested when crash 2021-11-16 10:44:54 -03:00
Abdelatif Guettouche
5a41572fd0 esp32c3/esp32c3_usbserial.c: Initialize cpuint to ENOMEM, otherwise the
first attempt to attaching an interrupt will trigger an assertion.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-15 12:11:45 -06:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-15 00:04:12 +01:00
Abdelatif Guettouche
6cbcbd5481 arch/risc-v&xtensa/Kconfig: Don't select LIBC_ARCH_MEMCCMP. The Kconfig
option doens't exist and we are not providing any external
implementation.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
zhuyanlin
c6c534f27b xtensa:mpu:use WRITEBACK attribute for intsram & extsram
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-13 05:59:10 -06:00
Dong Heng
fed7808d80 esp32 & esp32c3: Partition supports BIO cmd 2021-11-13 05:58:30 -06:00
anjiahao
edaa8a0ce9 fix sim_x11fb compile error
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2021-11-13 05:58:01 -06:00
Dong Heng
f5c5d77744 risc-v/esp32c3: Add hardware brownout check and reset 2021-11-12 16:50:19 -03:00
Eero Nurkkala
876b39914b mpfs: uart: add a way to configure uart3 and uart4
Currently configuring the uart3/4 as the serial console
doesn't work. Apply proper changes in mpfs_config.h that
enables the following configuration options:

 - CONFIG_UART3_SERIAL_CONSOLE
 - CONFIG_UART4_SERIAL_CONSOLE

Also, fix a typo in mpfs_lowputc.c that gives a compile
error if defined.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-11 06:02:27 -06:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug.
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Alan C. Assis
b8c33e585e esp32c3: Fix GPIO Output on pins 18 and 19 USB/JTAG 2021-11-09 20:54:34 -06:00
Abdelatif Guettouche
23039c92cf esp32c3/Make.defs: Alawys build esp32c3_serial.c
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
ebd94961c7 arch/riscv/esp32c3: Add the USB-Serial Driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Abdelatif Guettouche
17cf3edf46 arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG
controller.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Dong Heng
a59aae6927 esp32/esp32c3: Fix MMU pages number calculation error 2021-11-07 21:59:54 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
zhuyanlin
5a4140f020 arch:xtensa: add setjmp xtensa function
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-06 07:39:27 -05:00
zhuyanlin
580d17cc02 arch:xtensa: make xtensa_abi.h global include and usage
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2021-11-06 07:39:27 -05:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
Eero Nurkkala
f8832f7d86 mpfs: emmcsd: fix uninitialized value
cppcheck reports the following:

arch/risc-v/src/mpfs/mpfs_emmcsd.c:2375:22: error: Uninitialized variable: waitbits [uninitvar]
  while (!(status & (waitbits | MPFS_EMMCSD_SRS12_EINT))

The finding is positive and this patch initializes it to
zero properly.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-05 11:47:49 +01:00
David Sidrane
c077361a8a imxrt:usb Fix EP type allocation 2021-11-04 13:23:25 -05:00
David Sidrane
95f7f4b9e6 imxrt:usb DMA cache aligned Buffers for Endpoints 2021-11-04 13:23:25 -05:00
David Sidrane
bd2bc1e351 imxrt:usbdev Clean up cache maintainence 2021-11-04 13:23:25 -05:00
David Sidrane
c3d10ad0aa imxrt:usbdev formatting cleanup 2021-11-04 13:23:25 -05:00
David Sidrane
532635129c imxrt:usdhc add proper support for dcache (wb) 2021-11-04 13:23:25 -05:00
David Sidrane
5022244339 imxrt mpuinit:Set Data and Code Type to Normal
Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
2021-11-04 13:23:25 -05:00
David Sidrane
34c3efcb91 imxrt mpuinit:Remove duplicate entry for ITCM (0x0) 2021-11-04 13:23:25 -05:00
David Sidrane
08d0434bad imxrt:mpu init handle dcache setting in MPU config
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
   are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   is on then buffering operations are no-ops.

   This change enables MPU_RASR_C and MPU_RASR_B if
   CONFIG_ARMV7M_DCACHE is only set.

   if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
   MPU_RASR_C is enabled.

   N.B When caching is disalbed unaligned access may cause hard faults
   so add -mno-unaligned-access

   It is always safe to enable Buffering in FLASH to achive unaligned
   access leniency, as it is not written to.
2021-11-04 13:23:25 -05:00
ChenWen
440787c0c1 risc-v/esp32c3: Fix Wi-Fi & BLE coexist issue
1. Wi-Fi and BLE use common PHY functions.
  2. Fix Wi-Fi & BLE coexist adapter error.
  3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.
2021-11-04 11:02:05 -03:00
ChenWen
65d7f4bfb3 riscv/esp32c3: Support more country codes 2021-11-04 11:02:05 -03:00
ChenWen
4fc2f6e28c riscv/esp32c3: Support debug log configuration for Wi-Fi library 2021-11-04 11:02:05 -03:00
ChenWen
02968cc124 risc-v/esp32c3: Improve Wi-Fi connection success rate 2021-11-04 11:02:05 -03:00
ChenWen
222ec556d5 riscv/esp32c3: Fix some Wi-Fi issues
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
  2. Support Wi-Fi 12/13 channel active scanning by default.
  3. Update Wi-Fi driver code to fix issue of failure to send pkt.
  4. Replace software random with hardware random
  5. Fix Wi-Fi mode start error
2021-11-04 11:02:05 -03:00
chenwen
33031a2813 riscv/esp32c3: Fix the issue of Wi-Fi automatic disconnection 2021-11-04 11:02:05 -03:00
chenwen
afbad5ca9d riscv/esp32c3: Clear station configuration when connection fails or disconnect 2021-11-04 11:02:05 -03:00
Eero Nurkkala
8e43f39141 mpfs: cache: provide L1/L2 cache enablers
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-04 11:00:55 -03:00
Alexander Lunev
60de445ab3 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
2021-11-03 22:50:14 -05:00
Xiang Xiao
3e967f784e sim: Split SIM_SANITIZE to SIM_ASAN and SIM_UBSAN
align the naming style with MM_ASAN

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-02 21:02:43 +01:00
mage1
c82a676630 sim: fix sim runtime err under sanitize check mode.
since gcc sanitize can not stub proper code in nuttx kernel code.
2021-11-02 21:02:43 +01:00
Jani Paalijarvi
a16a9f80e2 mpfs: i2c: Add support for adaptive I2C bus frequency
Select the closest possible frequency which is smaller
than or equal to requested in I2C msg
2021-11-02 04:10:08 -05:00
ligd
2f4662c513 arch/arm: Remove -mcpu for fix warning
warning: switch '-mcpu=cortex-m55' conflicts with '-march=armv8-m.main' switch

Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-11-01 21:28:10 -05:00
ligd
8417b4726b Revert "arch/armv8-m: use -mfpu=auto based on -mcpu=cortex-m55"
This reverts commit d9a5b92c1a306a70df52d50a02a80dc8ef20bf0d.

Revert "arch/arm: Remove -march and -mtune"

This reverts commit b8e99cf12f3a287311a2d341f285c71a5da3e4d4.
2021-11-01 21:28:10 -05:00
Abdelatif Guettouche
860370284e esp32c3_dma: Remove the DMA test included in the driver along with its
defconfig.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-01 13:49:59 -05:00
Alexander Vasiljev
aeb1d3098d stm32h7/dmamux: correct bit fields 2021-11-01 14:40:33 -03:00
Abdelatif Guettouche
73f15ed544 esp32/Kconfig: Make ESP32_BT_RESERVE_DRAM default to 0 again if
Bluetooth is not enabled.  When Bluetooth is enbaled then it defaults to
64KB.  This will not wast those 64KB of memory when Bluetooth is not enabled.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-01 10:01:38 -05:00
Alexander Lunev
33d236121f stm32h7 sdmmc: added missing sdio_set_sdio_card_isr() function to initialize SDIO in-band interrupt logic 2021-10-31 22:26:13 -05:00
Xiang Xiao
b58379b738 arch/arm: Add l suffix for INT32_C macro
since int32_t typedef to signed long

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-10-31 12:56:41 -03:00
Michal Lenc
a64903acc7 samv7: adds support for QSPI driver in SPI Mode
This commit adds new files that support functionality of QSPI driver in
SPI Master Mode. This functionality is included in new files sam_qspi_spi.x
to avoid too much mess in the source code. QSPI in SPI mode can be turn
on by config option SAMV7_QSPI_SPI_MODE.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-10-30 01:24:31 -05:00
yinshengkai
ee17ae5ba1 tool: add code coverage tool 2021-10-29 19:21:23 +02:00
raiden00pl
bb5e3fee44 arch/arm/src/stm32/stm32_foc.c: define missing FOC1_PWM_FZ_BIT for G4 2021-10-29 07:49:59 -05:00
raiden00pl
8e9e54cad3 arch/arm/src/stm32/hardware/stm32_dbgmcu.h: fix invalid STM32_DBGMCU_APB2_FZ offset for G4 2021-10-29 07:49:59 -05:00
Alexander Vasiljev
35e93644cf stm32h7: add low power timers 2021-10-27 10:37:05 -05:00
Jiuzhu Dong
1ed4118378 power/battery: add baterr, batinfo, batwarn for debug log
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-10-26 13:59:42 -03:00
chao.an
b90d094138 arch/sim: add native socket support based on usrsock
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-10-26 08:01:50 -05:00
Gustavo Henrique Nihei
de0e4d4aac xtensa/esp32s2: Rename MTD-related configs to become more intuitive
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
06bb85d8a5 risc-v/esp32c3: Rename MTD-related configs to become more intuitive
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
fb00ab3242 xtensa/esp32: Rename MTD-related configs to become more intuitive
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
eb889b0884 xtensa/esp32s2: Enable Partition Table allocation at custom offset
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
eb7ffd014e risc-v/esp32c3: Enable Partition Table allocation at custom offset
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
211f899b62 risc-v/esp32c3: Refactor and reorganize Partition Table related configs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
9d7b9821b3 xtensa/esp32: Enable Partition Table allocation at custom offset
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
b555b3f89e xtensa/esp32: Refactor and reorganize Partition Table related configs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Gustavo Henrique Nihei
793266d39e espressif: Fix spacing style in Kconfig files
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
4ff754827c espressif: Fix prompt string of Wi-Fi FS mount point configs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Gustavo Henrique Nihei
a1af605973 espressif: Fix references to Wi-Fi according to Wi-Fi Alliance
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 08:01:44 -05:00
Alan C. Assis
7e8003cba1 Move chip specific file compilation to CHIP_CSRCS 2021-10-23 04:03:12 -05:00
Alan C. Assis
03738622a1 esp32s2: Add RNG driver support and board profile example 2021-10-23 04:03:12 -05:00
David Sidrane
e1a0a1188e stm32h7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
e66423229a stm32f7:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00
David Sidrane
fd2c1cb216 stm32:Support CONFIG_MPU_RESET and CONFIG_ARM_MPU_EARLY_RESET 2021-10-23 03:58:26 -05:00