sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
27,286 Commits 1 Branch 0 Tags 291 MiB
5a9d3b20fa
Commit Graph

9655 Commits

Author SHA1 Message Date
Frank Benkert
573b1d415c * SAMV7: SPI: SPI-Freq. 40MHz; VARSELECT; hw-features 
This change adds the following improvements:
  - Increase the allowed SPI-Frequency from 20 to 40 MHz.
  - Correct and rename the "VARSELECT" option This option was included in the code as "CONFIG_SPI_VARSELECT" but nowhere  defined in a Kconfig file. The patch renames it to "CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation according the datasheet of Atmel. In short, this option switches the processor from "fixed peripheral selection" (single device) to "variable peripheral selection" (multiple devices on the bus).
  - Add a new Function to the interface to control the timing and delays of the chip according the ChipSelect lines. This function can control the delay between the assertion of the ChipSelect and the first bit, between the last bit and the de-assertion of the ChipSelect and between two ChipSelects. This is needed to tune the transfer according the specification of the connected devices.
  - Add three "hw-features" for the SAMV7, which controls the behavior of the ChipSelect:
    1. force CS inactive after transfer: this forces a (short) de-assertion of the CS after a transfer, even if more data is
      available in time
    2. force CS active after transfer: this forces the CS to stay active after a transfer, even if the chip runs out of data. Btw.: this is a prerequisit to make the LASTXFER bit working at all.
    - escape LASTXFER: this suppresses the LASTXFER bit at the end of the  next transfer. The "escape"-Flag is reset automatically.
 2016-06-14 13:12:16 -06:00
Shirshak Sengupta
078e9b7082 Bug Fix in tiva_serial.c - UART5, UART6 and UART7 were not being configured as TTYS0 for printing over serial console 2016-06-14 10:47:18 -06:00
David Sidrane
0bded28cf3 Fix some naming errors that were recently introduced with mass substirutions 2016-06-14 09:42:04 -06:00
Gregory Nutt
a98bc05f65 New debug macro: alert(). This is high priority, unconditional output and is used to simplify and stanardize crash error reporting. 2016-06-14 09:07:53 -06:00
David Sidrane
ccfcb12ef7 STM32F7: Add SPI driver. DMA not yet supported. 2016-06-14 07:11:55 -06:00
David Sidrane
189b0d004f Added Pinmap to F7 2016-06-14 07:02:41 -06:00
David Sidrane
6d88df6802 Remove duplicate settings from stm32/Kconfig 2016-06-14 07:00:06 -06:00
Gregory Nutt
93e7b5d7a0 Eliminate some warnings 2016-06-13 14:15:54 -06:00
Gregory Nutt
0f249016a0 Eliminate some warnings 2016-06-13 14:01:32 -06:00
Gregory Nutt
eac916c907 Fix some warnings 2016-06-13 11:48:20 -06:00
Gregory Nutt
40f0481478 configs/: Change some *err() message to *info() messages if what was a *dbg() message does not indicate and error condition. 2016-06-13 09:44:12 -06:00
Gregory Nutt
b9aadf7242 configs/: Change some *err() message to *info() messages if what was a *dbg() message does not indicate and error condition. 2016-06-13 08:45:54 -06:00
Gregory Nutt
26718cee5c Eliminate some warnings when CONFIG_DEBUG_FEATURES is enabled, but no output is enabled 2016-06-12 14:44:04 -06:00
Gregory Nutt
61969a5f88 Eliminate some warnings 2016-06-12 08:37:03 -06:00
Gregory Nutt
b1eb4fdd8e Rethink some recent warning removal logic 2016-06-12 07:17:04 -06:00
Gregory Nutt
cffef35644 Eliminate some warnings introduced with DEBUG changes 2016-06-11 18:09:39 -06:00
Gregory Nutt
be80a0b99c Eliminate some warnings 2016-06-11 16:40:53 -06:00
Gregory Nutt
a1469a3e95 Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err() 2016-06-11 15:50:49 -06:00
Gregory Nutt
e99301d7c2 Rename *lldbg to *llerr 2016-06-11 14:55:27 -06:00
Gregory Nutt
86b79b33cf Reserver the name 'err' for other purposes 2016-06-11 14:40:07 -06:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Gregory Nutt
fc3540cffe Replace all occurrences of vdbg with vinfo 2016-06-11 11:59:51 -06:00
Gregory Nutt
3a74a438d9 Rename CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_INFO 2016-06-11 11:50:18 -06:00
Gregory Nutt
e891a33c2e Completely trivial changes from review of last PR 2016-06-10 14:59:53 -06:00
Gregory Nutt
525557c098 Merged in kfazz/nuttx/kinetis_pwm (pull request #50) 
kinetis pwm support
 2016-06-10 14:54:19 -06:00
Konstantin Berezenko
b9e7b4ed70 Correct the can2 rx irq number for stm32f10xx chips 2016-06-10 10:52:58 -07:00
Gregory Nutt
275f8988f8 Fix a cloned error in debug macro definitions 2016-06-10 10:13:30 -06:00
Gregory Nutt
ae1281d244 SAM4E AFEC: Fix some columnar alignement 2016-06-10 10:00:36 -06:00
OrbitalFox
78a2465af4 SAM4E: Fix some errors in AFEC header file. 2016-06-10 09:56:35 -06:00
kfazz
0f40ef86b9 Added kl_dumpgpio functionality as kinetis_pindump, which was 
already prototyped in kinetis.h. It is enabled when CONFIG_DEBUG_GPIO
is defined.
 2016-06-10 11:35:20 -04:00
Lok Tep
6ea61306b6 Merge remote-tracking branch 'remotes/parent/master' 2016-06-10 09:10:07 +02:00
kfazz
6e9df2adf7 support up to 8 channels per timer. TODO: port kl_dumpgpio.c to kinetis 2016-06-09 23:34:24 -04:00
Gregory Nutt
e6ca12f4c3 Changes from review of last PR 2016-06-09 16:57:05 -06:00
Konstantin Berezenko
2ebdcb463e Fix compilation errors in debug mode of stm32_pwm.c 2016-06-09 15:48:08 -07:00
ziggurat29
5db2618c3c accomodate the additional endpoint descriptors (and allocate fifo space) that are present in the 'L4 2016-06-09 14:01:59 -05:00
kfazz
3cc843480b updated copyright year and fixed comment whitespace. 2016-06-09 13:16:11 -04:00
kfazz
9e36d42859 Kinetis pwm support, based on kl_ftm driver. 
Initial commit. Compile checked only.
 2016-06-09 13:07:03 -04:00
ziggurat29
b91ce6b6b8 set power ctl USV bit as early (and required) step in initializing USB device. also various comment fixups and minor syntax error in some conditional compile blocks. 2016-06-09 11:28:23 -05:00
ziggurat29
d2b78eddec need to be able to explicitly indicate Vddusb is valid in order to use the OTFS block in this chip; done via PWR CR2 bit USV. 2016-06-09 11:26:36 -05:00
Gregory Nutt
8c9bc6da79 Trivial changes from review of last PR 2016-06-09 09:39:41 -06:00
Gregory Nutt
2dbd6b3d99 Merged in kfazz/nuttx (pull request #45) 
Teensy clock fixes.
 2016-06-09 09:36:30 -06:00
Gregory Nutt
48c9aa08a3 Merged in marten_svanfeldt/nuttx-public/for_upstream/stm32_dma_fix (pull request #43) 
Fix STM32 DMA code and configuration for STM32F37X chips
 2016-06-09 09:10:13 -06:00
David Sidrane
44ead7f40a Fix email address in file headers 2016-06-09 08:26:14 -06:00
Lok Tep
f12f115598 rename back without f7 2016-06-09 15:48:07 +02:00
kfazz
0c13208d87 Teensy clock fixes. 
The High Gain bit in MCG_C1 was preventing teensy from booting
except after a programming session. The second change doesn't appear
to change any functionality, but complies with restrictions in the k20
family reference manual on FEI -> FBE clock transiions.
 2016-06-09 00:41:01 -04:00
Marten Svanfeldt
1b36526e91 Fix STM32 DMA code and configuration for STM32F37X chips 
Signed-off-by: Marten Svanfeldt <marten@intuitiveaerial.com>
 2016-06-09 05:02:43 +02:00
Gregory Nutt
982982d62b Eliminate some warnings 2016-06-08 09:43:54 -06:00
David Sidrane
4a4f407175 STM32F7: Fix a redefinition warning the DMA header file 2016-06-08 08:29:30 -06:00
David Sidrane
d8ea955d69 Added STM32FF76xxx and STM32FF7xx families 2016-06-08 08:26:26 -06:00
Konstantin Berezenko
3fc7b6f0e5 Add stm32f105r support 2016-06-06 12:52:41 -07:00
Gregory Nutt
f75837a110 Changes from review of the last PR 2016-06-06 13:35:27 -06:00
Gregory Nutt
6b58ed820a Merged in kfazz/nuttx/kinetis (pull request #40) 
Kinetis usb driver
 2016-06-06 12:57:55 -06:00
kfazz
0a4c58e573 First attempt at a usb device controller driver for kinetis. derived from pic32mx usb driver, which uses the same usb controller. 2016-06-06 13:58:07 -04:00
Paul A. Patience
56b018d5db STM32: Fix typo 2016-06-06 12:02:11 -04:00
Gregory Nutt
053ac343fd STM32 PWM: More review changes from last commit; improve handling of unsigned types 2016-06-05 16:01:29 -06:00
Pierre-noel Bouteville
0bd444ae47 Just update duty if frequency is not changed and PSM started. This removeis glitch or blinking when only duty is frequently changed. 2016-06-05 15:35:43 -06:00
Gregory Nutt
af43ce4f46 Update ChangeLog 2016-06-05 15:01:37 -06:00
Lok Tep
88b51683bb bus busy timeout, errata 2016-06-05 11:43:06 +02:00
Gregory Nutt
7671087abc LPC32xx GPIO interrupts: Remove some old logic that should not be there. 2016-06-04 16:36:27 -06:00
Gregory Nutt
1c4d0686c8 LPC43xx: Fill out some missing GPIO interrupt logic 2016-06-04 16:05:36 -06:00
Gregory Nutt
6b84637a5b Update some comments 2016-06-04 13:04:13 -06:00
Gregory Nutt
4965d0dc99 KL and LPC11: Perform similar name change as for STM32: xyz_lowputc -> up_putc 2016-06-04 11:29:27 -06:00
Gregory Nutt
184ca294e8 Rename all references to up_lowgetc 2016-06-04 07:59:02 -06:00
Gregory Nutt
ed1535f188 Changes from review of last PR 2016-06-04 07:52:56 -06:00
Gregory Nutt
8126a3d37d Merged in v01d/nuttx/lpc43-gpio-fixes (pull request #38) 
lpc43 GPIO Interrupts enabled and fixed (not all cases tested)
 2016-06-04 07:46:04 -06:00
Alan Carvalho de Assis
86cfcfd58a Add the up_getc() function to STM32 in order to support the minnsh configuration. 2016-06-04 07:22:45 -06:00
Gregory Nutt
37e8536a88 STM32: Put timer selections in a separate menu 2016-06-04 07:11:05 -06:00
v01d
774e7f9865 lpc43 GPIO Interrupts enabled and fixed (not all cases tested) 2016-06-04 00:28:53 -03:00
Gregory Nutt
34df98d97e Use DEBUG assertions to save space 2016-06-03 14:49:05 -06:00
Gregory Nutt
704fadb0e6 STM32 TIM: Assure that a compilation error will occur if the old timer input clock frequency definitions are used 2016-06-03 14:17:18 -06:00
Gregory Nutt
3ec2386be8 STM32 TIM: There is a TIM17 on some parts too 2016-06-03 14:08:28 -06:00
Gregory Nutt
282edefab3 STM32 TIM: Add hooks for all previously unsupported timers. Also fix some PWM warnings. 2016-06-03 13:51:43 -06:00
Gregory Nutt
c11e923ad4 Fix a cut'n'paste error left from last commit. 2016-06-03 12:11:55 -06:00
Gregory Nutt
910bac65fa STM32 Timer: Generalize and extend calculation of per-timer pre-scaler value. Inspired by original proposal from Pierre-noel Bouteville. 2016-06-03 11:38:59 -06:00
Gregory Nutt
88a41862b5 Revert "STM32 Timer Driver: Change calculation of per-timer pre-scaler value" 
This reverts commit 082d32226b.
 2016-06-03 09:41:17 -06:00
Lok Tep
82cd44dbc5 adc i2c_reset 2016-06-03 17:19:22 +02:00
Pierre-noel Bouteville
082d32226b STM32 Timer Driver: Change calculation of per-timer pre-scaler value 2016-06-03 08:45:22 -06:00
Pierre-noel Bouteville
426e425a55 Correct conditional compilation in STM32 timer cpature logic 2016-06-03 08:41:53 -06:00
Pierre-noel Bouteville
6a2a0bf11f Note reserved bits in STM32 ADC 2016-06-03 08:39:17 -06:00
Pierre-noel Bouteville
94a14de190 Fix EFM32 FLASH conditional compilation 2016-06-03 08:38:11 -06:00
Gregory Nutt
fcdc17056b STM32 F4 RTC: I believe that the F405/407 has only a single alarm. Not sure. 2016-06-02 15:04:23 -06:00
Lok Tep
3bb60966e7 adc copy 2016-06-02 16:17:58 +02:00
Gregory Nutt
82c73e206e STM32 F4 RTC, trivial changes 2016-06-02 07:58:13 -06:00
pkolesnikov
beb6acc798 timer copy 2016-06-02 12:09:42 +02:00
Frank Benkert
90ccba1ad0 SAMV7: MCAN: fix missing unlock of device in mcan_txempty 2016-06-01 10:38:19 -06:00
Gregory Nutt
2f974ffeaf Merged in david_s5/nuttx/upstream_to_greg (pull request #37) 
Fix the Value Line adc IRQ number selection
 2016-05-31 19:18:11 -06:00
Gregory Nutt
82dec4acab STM32F4 RTC: Remove 24 hour limit; Fix calculation of the alarm register (was not including day of the month). Fix a bad shift value 2016-05-31 19:13:21 -06:00
David Sidrane
70f2b47a0d Fix the Value Line adc IRQ number selection 2016-05-31 14:54:04 -10:00
Gregory Nutt
6eac8bf28d Update some comments 2016-05-31 17:31:15 -06:00
Gregory Nutt
15810946b1 Update some comments 2016-05-31 17:28:02 -06:00
Gregory Nutt
8ca5daf2b3 Changes from review of last PR 2016-05-31 15:52:56 -06:00
Gregory Nutt
213c1900b0 Merged in neilh20/anuttx/bugfix_rtcalarm (pull request #36) 
The rtc examples "alarm 10" now runs to completion
 2016-05-31 15:43:36 -06:00
neilh10
639410849e alarm 10 now runs to completion 2016-05-31 14:17:52 -07:00
Gregory Nutt
b80bf20374 Fix another bungle in the last commit 2016-05-31 11:52:40 -06:00
Gregory Nutt
b5c37f0270 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:42:21 -06:00
Gregory Nutt
828c898a80 LP43: Add support for more than 63 interrupts (not currently needed) 2016-05-31 11:39:51 -06:00
Gregory Nutt
f06a06952f LPC43xx: 1KB is 1024, not 1025. Noted by phreakuencies. 2016-05-31 06:22:10 -06:00
ziggurat29
3970c98daf Merge branch 'master' into stm32l4_usb 2016-05-30 13:52:45 -05:00
Pierre-noel Bouteville
39c1e3aba2 Allow to not use all channet in a lower part of PWM 2016-05-30 11:58:22 -06:00
Gregory Nutt
f65616f872 Replace confusing references to uIP with just 'the network' 2016-05-30 09:16:32 -06:00
Gregory Nutt
815bea77ea i.MX6: Update ECSPI header file 2016-05-29 10:23:06 -06:00
Gregory Nutt
fa10927dcc Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAM3/4 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change: 
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
 2016-05-29 08:25:41 -06:00
Gregory Nutt
9071a22c28 Cosmetic fix to spacing 2016-05-29 08:25:05 -06:00
Gregory Nutt
0b17b1feb3 i.MX6: Add ECSPI configuration logic. Updated ECSPI header files 2016-05-28 17:42:29 -06:00
Gregory Nutt
16cb0a9205 i.MX6: Divide ported i.MX1/L CSPI header file into two header files 2016-05-28 17:10:58 -06:00
Gregory Nutt
13b53d87a9 i.MX6: Add ECSPI header file 2016-05-28 12:23:05 -06:00
Konstantin Berezenko
5c6cd17d46 Add support for SPI 4 and 5 on stm32f411 chips 2016-05-27 11:08:18 -07:00
Gregory Nutt
b4354cf130 Stefan Kolb's change to the SAMV7 Oneshot Timer (commit d44ecbcfbb) should also be applied to the SAMA5 oneshot time since the drivers are identical. Here are the commit commits from Stefan's original change: 
"This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started.

"In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

"Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it."
 2016-05-27 07:58:03 -06:00
Stefan Kolb
d44ecbcfbb This is a fix to a problem in the handling of the oneshot timer. Due to a wrong assumption concerning the behavior directly after the start of the timer/counter the function sam_oneshot_cancel(…) calculates the wrong remaining time. The code assumes that the counter register is zero directly after the start of the timer, but this is not true. To start the time/counter a software trigger is invoked, this trigger starts the timer/count and sets the counter register to zero, but the reset of the counter register is not performed instantly. According to the datasheet: “The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock.” Thus the counter is set to zero between 0 and USEC_PER_TICK microseconds after the clock was started. 
In my fix I use the freerun count value to determine if at least one tick passed since the start of the timer and thus if the value of the oneshot counter is correct. I also tried to use the function up_timer_gettime(…) to achieve this but, at least if compiled with no optimization the problem vanishes without using the value of the function, the function call takes too long.

Another problem treated in the fix is that if the oneshot timer/counter is canceled, we only know the remaining time with a precision of USEC_PER_TICK microseconds. This means the calculated remaining time is between 0 and USEC_PER_TICK microseconds  too long. To fix this I subtract one tick if the calculated remaining time is greater than one tick and otherwise set the remaining time to zero. By doing so the measured times are much more precise as without it.
 2016-05-27 07:51:50 -06:00
Gregory Nutt
3d3b7b5422 EFM32, STM32, TIVA: Allow lower half driver to build if any ADC is selected. Should not depend on CONFIG_ADC. 2016-05-27 06:46:33 -06:00
Lok Tep
c00bb5d4a7 i2c 2016-05-27 00:16:55 +02:00
Gregory Nutt
31ac3f5123 STM32 ADC: Missed on adc_receive 2016-05-26 12:42:34 -06:00
Gregory Nutt
aa05767a00 Add ADC bind method to the Tiva ADC drivers 2016-05-26 12:39:22 -06:00
Gregory Nutt
8f2a660c8b Add ADC bind method to the STM32 ADC drivers 2016-05-26 12:25:54 -06:00
Gregory Nutt
2f5221ed91 Add ADC bind method to the LPC43xx and SAMA5Dx ADC drivers 2016-05-26 12:19:17 -06:00
Gregory Nutt
957634519d Missed a few adc_receive calls in the LPC17xx ADC driver. That design has several. 2016-05-26 12:04:17 -06:00
Gregory Nutt
9d6845b7ec Add ADC bind method to the EFM32 and LPC17xx ADC drivers 2016-05-26 11:57:18 -06:00
Gregory Nutt
783bab6c82 Costmetic changes from review of last PR 2016-05-25 18:04:39 -06:00
Gregory Nutt
0d2698a710 Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #30) 
get I2C working for STM32L4
 2016-05-25 17:58:19 -06:00
Gregory Nutt
3603dc6218 1-wire: Initialization/uninitialization functions are not use MCU-independent up_ naming. Should use STM32-specific stm32_ naming. These are not globally accessible but only accessible from STM32 board logic. 2016-05-25 17:56:47 -06:00
ziggurat29
003c2c737a get I2C working. some more work regarding clocking computation is needed, as is some inhertited 'todo's from the basis code. but it does work with the devices tested so far. 2016-05-25 18:43:37 -05:00
Paul A. Patience
d31aefe4ef STM32 CAN: Add support for both RX FIFOs 2016-05-25 16:11:18 -04:00
Gregory Nutt
add152bf24 Update README 2016-05-25 14:07:59 -06:00
Gregory Nutt
78e08bbeea Purely cosmetic change from review of last PR 2016-05-25 13:29:01 -06:00
Gregory Nutt
fafc56ae80 Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #28) 
complete logic in 'create stack' and 'use stack' to support stack coloration.  Fix some booboos breaking compatibility with TLS in libc.
 2016-05-25 13:22:03 -06:00
Gregory Nutt
4afc4964ed SAM34 TWI: Missing semicolon 2016-05-25 13:05:03 -06:00
Gregory Nutt
4a63a7760a STM32: Hook 1-Wire driver into the build system 2016-05-25 12:31:32 -06:00
Gregory Nutt
9ec104834a Remove CONFIG_USARTn_ISUART 2016-05-25 11:21:48 -06:00
Gregory Nutt
c089a2f241 Rename CONFIG_ARCH_HAVE_OTHER_UART to CONFIG_OTHER_UART_SERIALDRIVER 2016-05-25 10:48:33 -06:00
Gregory Nutt
e2e6ce3f1b Rename CONFIG_ARCH_HAVE_SCIn to CONFIG_SCIn_SERIALDRIVER 2016-05-25 10:46:55 -06:00
Gregory Nutt
2a87741e72 Rename CONFIG_ARCH_HAVE_UARTn to CONFIG_UARTn_SERIALDRIVER 2016-05-25 10:45:01 -06:00
Gregory Nutt
249a2e48e5 Rename CONFIG_ARCH_HAVE_USARTn to CONFIG_USARTn_SERIALDRIVER 2016-05-25 10:39:23 -06:00
ziggurat29
05d2036334 complete logic in 'create stack' and 'use stack' to support stack coloration. Fix some booboos breaking compatibility with TLS in libc. 2016-05-25 10:37:38 -05:00
Aleksandr Vyhovanec
52c6cb1799 Fix typographical naming error in STM32 U[S]ART bit defintiions. 2016-05-25 09:04:03 -06:00
Aleksandr Vyhovanec
9a2002a302 1-wire driver based on U[S]ART in single-wire, half-duplex mode. 2016-05-25 08:59:47 -06:00
Frank Benkert
04223a9618 SAMV7: USBHS: Remove disabling of whole usb on suspend 
This fix removes the disabling of the whole USB peripheral on suspend
interrupt. Its enough to freeze the clock instead.

When disabling the whole peripheral, the next wakeup-interrupt comes
up with an disabled clocking. The unfreeze clock has no effect, because
the master clock is disabled. This makes all registers, including the
IDR unwriteable and the IRQ falls in an endless loop blocking the whole
system.

Furthermore the disabling of the peripheral clock prevents hotplugging
or reconnecting the USB.
 2016-05-25 07:20:48 -06:00
pkolesnikov
9ee3fe3f19 clocking for 54mhz 2016-05-25 14:30:47 +02:00
Lok Tep
4c96755219 Merge remote-tracking branch 'origin/master' 2016-05-24 23:23:57 +02:00
unknown
c89a5494b8 spi, copy 2016-05-24 16:57:39 +01:00
Gregory Nutt
317bf064a8 i.MX6: Clean up some initializers 2016-05-24 07:44:36 -06:00
Alexander Vasiljev
ad6f37edfa Adds definitions for the LPC4337jet100 chip. 2016-05-24 07:03:50 -06:00
Gregory Nutt
3a8ff78f87 Restore PR. I have no idea where it went. 2016-05-23 17:45:15 -06:00
Gregory Nutt
e929066042 Fix an error in the last commit 2016-05-23 17:11:36 -06:00
David Sidrane
c41e6d823a Add the up_systemreset interface to the samv7 arch. The approach is slightly different in that: 1) It enables ARCH_HAVE_RESET and allows the user to set if, and for how long, to drive External nRST signal. It also does not contain a default board_reset, as that really should be done in the config's src if CONFIG_BOARDCTL_RESET is defined. 2016-05-23 17:05:02 -06:00
David Sidrane
fca329945b This patch ensures that the TWIHS (i2c) hw get's its clock set when the sequence of 
sam_i2cbus_initialize
sam_i2cbus_uninitialize
sam_i2cbus_initialize

Or twi_reset is called.

I found this a while back in the stm32 family, so there may be more arch-es with this sort of bug. I suppose any driver that has the notion of "do not set the freq if it is already set" could be suspect.
 2016-05-23 13:38:34 -06:00
Alexander Vasiljev
b43fcd6f99 LPC43xx: Add AES support. 2016-05-23 08:03:32 -06:00
pkolesnikov
eb9cfd1255 i2c copy, right include 2016-05-23 15:59:24 +02:00
pkolesnikov
7630b9db5d i2c copy 2016-05-23 15:56:56 +02:00
Gregory Nutt
80d0b2736e Reorder some logic: (1) set initial CPU IDLE task regsters AFTER allocating stack, (2) invalidate cache in CPU start-up BEFORE handling first interrupt. 2016-05-22 15:01:49 -06:00
Gregory Nutt
e47714322e Merged in K-man23/nuttx/stm32f411e-disco (pull request #25) 
Add basic configuration for stm32f411e-disco board with STM32F411VE chip
 2016-05-20 17:54:07 -06:00
Konstantin Berezenko
a2253cdd3e Add basic configuration for stm32f411e-disco board with STM32F411VE chip 2016-05-20 16:38:25 -07:00
Gregory Nutt
356692d70e SMP: Need to enable FPU on other CPUs as well 2016-05-20 13:35:58 -06:00
Gregory Nutt
07acd5327a SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started. 2016-05-20 12:39:02 -06:00
David Sidrane
916153fb75 Fix build if the config is not updated 2016-05-19 12:44:58 -10:00
Gregory Nutt
e27e87a957 Backing out part of last commit 2016-05-19 15:46:07 -06:00
David Sidrane
8fac871cc9 Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins 
• SYSIO4: PB4 or TDI Assignment
0: TDI function selected.
1: PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0: TDO/TRACESWO function selected.
1: PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0: TMS/SWDIO function selected.
1: PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0: TCK/SWCLK function selected.
1: PB7 function selected.
• SYSIO12: PB12 or ERASE Assignment
0: ERASE function selected.
1: PB12 function selected.

The thing I did not add is warning or compilation failure, (to save the next guy the hassle), at ALL the driver points that uses the these pins.

I did remove this

  /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
   * instead of TDI
   */

  uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
  sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
  putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);

in sam_lowputc.c in favor of an #error - because the default is an input TDI and driving it blindly to an output TXD1, would be a contention.
 2016-05-19 14:33:54 -06:00
Gregory Nutt
7f7d4e664c Completely trivial changes from review of last PR 2016-05-19 14:09:00 -06:00
Sebastien Lorquet
ef66f641e9 small fix left from stm32 2016-05-19 21:57:59 +02:00
Sebastien Lorquet
6642898ee4 Merge branch 'master' into can 2016-05-19 21:49:31 +02:00
Sebastien Lorquet
8aae953f67 CAN support for STM32L4 2016-05-19 19:13:04 +02:00
Gregory Nutt
c364faeefc SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface. 2016-05-18 19:47:48 -06:00
Gregory Nutt
5d574549bd stm32f103-minimum: Add schematic; remove unused watchdog driver logic 2016-05-18 15:37:42 -06:00
Gregory Nutt
f454b38d6e ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes 2016-05-18 09:17:02 -06:00
Gregory Nutt
72de45b7cf Merged in david_s5/nuttx/upstream_to_greg (pull request #21) 
Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
 2016-05-17 18:09:23 -06:00
David Sidrane
f444f061d6 Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build 2016-05-17 14:04:51 -10:00
Gregory Nutt
5fc619eb1b Changes from review of last PR 2016-05-17 17:39:27 -06:00
Gregory Nutt
4aeb06a79d Merged in david_s5/nuttx/upstream_to_greg (pull request #20) 
Upstream_to_greg
 2016-05-17 17:30:45 -06:00
David Sidrane
bef5552eba Support BSD compatible breaks on stm32fl4 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
3ffe7c378f Support BSD compatible breaks on stm32f7 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
b11f49e7f1 Support BSD compatible breaks on stm32 U[S]ART 2016-05-17 13:09:34 -10:00
David Sidrane
55d8b0e277 Use the correct register and bit to send an STM32 non-bsd compatible break 2016-05-17 07:55:33 -10:00
Gregory Nutt
fb484a581f All GCC final arch/*/src/Makefiles: Allow --start-group and --end-group to be redefined for the case where GCC is used to link (instead of LD). Suggested by Paul Alexander Patience. 2016-05-17 10:43:15 -06:00
Gregory Nutt
0fe64839db i.MX6: Fix comparison values in system timer setup. Clock was running 3x too fast. 2016-05-17 10:08:06 -06:00
Gregory Nutt
4c08492c0f i.MX6: Fix a bit setting in the timer configuration 2016-05-17 07:21:18 -06:00
Gregory Nutt
e6728bac29 Cortex-A9 GIC: Add an interface to set interrupt edge/level trigger 2016-05-16 14:42:55 -06:00
Gregory Nutt
4feeb0c2b4 Cortex-A9 GIC: Some fixes that I don't fully understand but do indeed give me serial interrupts 2016-05-16 12:50:35 -06:00
Gregory Nutt
a0cdbcb58f Update README 2016-05-16 08:44:18 -06:00
ziggurat29
aa51ace46d initial code for USB OTG support in STM32L4. Builds, but needs debugging. 2016-05-14 08:15:48 -05:00
Gregory Nutt
a3f3cc12c0 Update some comments; Fix grammatic error in ChangeLog. 2016-05-13 17:36:08 -06:00
Gregory Nutt
faca2fb1e7 ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently 2016-05-13 11:39:42 -06:00
Gregory Nutt
d14d84c1a6 ARMv7M/i.MX6: Implement CPUn n=1,2,3 startup logic 2016-05-13 09:11:55 -06:00
Gregory Nutt
e5388ad127 i.MX6: Need to set VBAR register for each CPU 2016-05-12 15:32:53 -06:00
Gregory Nutt
70782b0f14 ARMv7-A i.MX6: More SMP logic. Still untested. 2016-05-12 15:04:46 -06:00
Gregory Nutt
99e695398c Rename up_boot to arm_boot 2016-05-12 13:42:49 -06:00
Gregory Nutt
ba4ae6fdc4 Cosmetic fixes to last commit 2016-05-12 13:42:48 -06:00
David Sidrane
8a4e185c84 Kconfig edited online with Bitbucket 2016-05-12 18:50:43 +00:00
Gregory Nutt
7887b2d164 i.MX6: Add SRC register definition header file 2016-05-12 12:23:07 -06:00
Gregory Nutt
c00e3e55dc Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:42:59 -06:00
Gregory Nutt
f64f7407ba SAMDL DMAC: Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:30:04 -06:00
Gregory Nutt
f07ea1bb94 SAM (all): Fix several places in DMA logic where a spurious semicolon causes bad conditional logic 2016-05-11 17:26:59 -06:00
David Sidrane
8517a303a5 sam_xdmac.c edited online with Bitbucket 2016-05-11 23:13:24 +00:00
Gregory Nutt
f69b7d41db Merged in young-mu/nuttx/developing (pull request #15) 
Fix a bug of GPIO falling-edge interrupt for tiva
 2016-05-08 01:40:56 -06:00
Gregory Nutt
5c1c5079ea Cosmetic changes from review of last PR 2016-05-08 01:40:31 -06:00
Gregory Nutt
0143b3869a Merged in ziggurat29/nuttx/stm32l4_update_rtc_impl (pull request #14) 
Stm32l4_update_rtc_impl
 2016-05-08 01:24:09 -06:00
Young
863db15b56 Fix a bug of GPIO falling-edge interrupt for tiva 2016-05-08 13:54:51 +08:00
ziggurat29
48fc8b9dd7 problem with resetting backup domain clears clocking options set up before in *rcc.c 
use INITS flag to avoid magic reg value to detect power up reset state of rtc
correct a problem clearing interrupt flags (they weren't) which prevented an alarm from ever being used more than once per reset cycle
 2016-05-07 11:35:08 -05:00
Stefan Kolb
da1fc98a51 Fix a copy and paste error concerning the CAN driver. In the file sam_matrix.h the define SAM_MATRIX_CAN0_OFFSET is set to the wrong value. 
Error is only triggered if the global variable g_mcan0_msgram is located in RAM at an address beyond 0x20400000 + 0x0000ffff. In this case all send CAN messages have the length zero and the CAN-ID is zero as well.
 2016-05-06 04:02:28 -06:00
Gregory Nutt
050f544782 Fix typo in variable name in serial BREAK logic. Review other serial implementations for similar naming problems. 2016-05-05 11:30:47 -06:00
ziggurat29
4e57c36a8c when setting an alarm, ensure that the respective alarm triggered flag is reset, because the alarms are edge-triggered interrupts 2016-05-05 11:47:58 -05:00
ziggurat29
0d659de226 fix nasty bug in ISR handler, where interrupt was not properly acknowleged (write to CR instead of ISR, as intended). Also, minor, set the LSI prescaler values more appropriately (though not critical since LSI is so low precision anyway). 2016-05-05 11:39:19 -05:00
ziggurat29
e0371de24d correct the RTC_ALRMR_ENABLE value, it needs to ignore the date/dow component since that is not set. Also, the prescaler value for HSE (which presumes 1 MHz, anyway) had transposed digits. 2016-05-05 11:28:41 -05:00
ziggurat29
67b1f89159 address thread safety in lower half driver with a driver mutex acquired/released in public api 2016-05-05 11:22:09 -05:00
ziggurat29
273680a6e9 update RTC implementation to include the various alarm related stuff recently added to STM32 arch 2016-05-05 11:16:00 -05:00
ziggurat29
dedcbeba2e add unique id function to arch, modded board to support unique id boardctl 2016-05-03 11:09:23 -05:00
Gregory Nutt
a95e426d35 Costmetic changes from last PR 2016-04-30 09:04:38 -06:00
ziggurat29
2fe0565437 added support for HSE and MSI clocks, and auto trim of MSI to LSE (needed for USB). 2016-04-29 22:13:32 -05:00
ziggurat29
31870b22f5 booboo in config sanity check; wasn't preventing insanity 2016-04-29 07:29:17 -05:00
ziggurat29
31e7f6fd00 add configuration options to allow SRAM2 to be used for heap, or not at all, and to zero-init it on OS start, or not at all. 2016-04-26 10:12:13 -05:00
ziggurat29
1218ee5f51 bug in binding peripheral to dma channel; inverted sense of a bitmask 2016-04-25 10:27:02 -05:00
ziggurat29
8d4dccb3b9 add DMA support to QSPI; tested. Updated Kconfig to more cleanly present the options and defaults. 2016-04-24 16:28:30 -05:00
ziggurat29
0f8dc3e7b4 fixed missing DMA peripheral selection and some header defines, updated various comments to be accurate 2016-04-24 16:23:47 -05:00
Gregory Nutt
aed10e0e49 Cosmetic changes from last PR 2016-04-23 12:51:46 -06:00
Gregory Nutt
0d3a0bf603 Merged in ziggurat29/nuttx/stm32l4_qspi_004 (pull request #5) 
add QSPI memory mapped mode support.  tested.  QSPI may enter and exit memory mapped mode; while in effect, other operations (e.g. command, memory) will fail with -EBUSY.
 2016-04-23 12:46:19 -06:00
ziggurat29
8c0c70ab12 add QSPI memory mapped mode support. tested. QSPI may enter and exit memory mapped mode; while in effect, other operations (e.g. command, memory) will fail with -EBUSY. 2016-04-23 11:54:03 -05:00
Marco Krahl
8b36a83df1 stm32: fix wrong FSCM pin mapping for stm32f42x 2016-04-22 07:27:00 -06:00
Gregory Nutt
2cb52786b6 STM32F7: Add dummy stm32_spi.h header file to workaround some compilation issues. Suggest by Martin Davey. 2016-04-20 06:49:21 -06:00
Gregory Nutt
4e04b3e931 Correct configuration of GPIO pin interrupts on Kinetis K60. Fromo mrechte. 2016-04-20 06:41:51 -06:00
Gregory Nutt
b8ee28cb57 lpc4357fet256_pinconfig.h has wrong ethernet pins configuration (slow slew rate, somewhere inbuffer should be used). From Vytautas Lukenskas 2016-04-20 06:37:26 -06:00
Frank Benkert
885cd812e6 SAME70: USBHS device workaround for errata; EP7 does not support DMA on some parts 2016-04-20 06:22:04 -06:00
Gregory Nutt
8bcb5f0251 Cosmetic changes from review of last PR 2016-04-19 07:11:18 -06:00
ziggurat29
ca6cb85456 QSPI interrupt driven mode is now implemented 2016-04-19 06:55:12 -05:00
Gregory Nutt
26ba3a2b96 Cosmetic changes from review of last PR 2016-04-18 06:50:45 -06:00
Gregory Nutt
c5cce5603e Merged in ziggurat29/nuttx/stm32l4_qspi_002 (pull request #2) 
basic support for QSPI in STM32L4; verified via 'examples/media'
 2016-04-18 06:30:28 -06:00
ziggurat29
499fea73ec basic support for QSPI in STM32L4; verified via 'examples/media' 2016-04-17 21:08:25 -05:00
Gregory Nutt
aa64214877 FB: Add a display number to the framebuffer planeinfo structure 2016-04-17 10:08:27 -06:00
Gregory Nutt
46846c0c24 Framebuffer driver: Add a display number to each interface in order to support multiple displays 2016-04-14 12:23:15 -06:00
Sebastien Lorquet
bef518095f Fix the STM32L4 SPI driver. That SPI driver is quite different. They now handle frames of arbitrary size between 4 and 16 bits. It was broken before a new bit has to be set (rx fifo threshold) to handle <= 8-bit transactions. If not set, the default is 16-bit packed >=8-bit frames and the RXNE bit is never set (it is set when 16-bits are received). weird things as always. 
This also add 8-bit access routines to the data register, because a 16-bit access to the data register when the frame size is below 9 bits is interpreted as a packed dual frame exchange.
 2016-04-13 17:21:49 -06:00
Gregory Nutt
99d981c3fc Kinetis SDHC: May work queue dependencies clearer 2016-04-12 09:07:25 -06:00
Stefan Kolb
fec1931def SAMv7 Kconfig: Correct range of SAMV7_PROGMEM_NSECTORS 2016-04-11 06:21:04 -06:00
Gregory Nutt
b3a177618f Oops: Forgot to add file in previous commit 2016-04-10 09:11:50 -06:00
Sergei Ustinov
8a5bf3c230 STM32 DAC output buffers correct enable. 2016-04-10 08:51:59 -06:00
Gregory Nutt
48106e605a Merge in arch/ submodule 2016-04-10 07:49:41 -06:00
Sebastien Lorquet
8f15af280a Sort DMA by function; Fix one misnamed definition. 2016-04-04 09:49:44 -06:00
Gregory Nutt
b4fc040783 RTC: Fix some compile issues when RTC_ALARM is disabled 2016-04-04 09:24:06 -06:00
Gregory Nutt
8a076d4c09 Eliminate a warning 2016-04-04 08:30:03 -06:00
Gregory Nutt
1e4674e535 STM32 RTC alarm: Use modifyreg32 for consistency 2016-04-04 08:28:01 -06:00
Gregory Nutt
1ea7b48677 RTC lower half was missing call to F4 alarm cancel function 2016-04-04 08:23:09 -06:00
Gregory Nutt
531b9f6626 STM32 RTC alarm: remove some if 0ed out logic. 2016-04-04 08:16:53 -06:00
Gregory Nutt
19aa5880e7 STM32 RTC Alarm: Add Neil's alarm cancellation logic 2016-04-04 08:15:48 -06:00
Gregory Nutt
65dc922a2e STM32 RTC: Fix compile errors for STM32 F1 2016-04-03 13:26:29 -06:00
Gregory Nutt
a573617f33 Costmetic renaming 2016-04-03 12:38:02 -06:00
Gregory Nutt
9f0df8180a STM32 RTC: Fix some errors when RTC debug is enabled 2016-04-03 09:52:08 -06:00
Gregory Nutt
6b3b12ee0a STM32 RTC: Move the logic to set a relative alarm from the low level RTC driver up higher into the RTC device driver lower half. 2016-04-03 09:22:02 -06:00
Gregory Nutt
e904d98915 STM32 RTC: Add implementation of logic to set the alarm relative to the current time 2016-04-02 18:17:46 -06:00
Gregory Nutt
a609880839 STM32 F4 RTC: Add support for setting alarm via driver 2016-04-02 17:38:19 -06:00
Gregory Nutt
d46156c2ba Merge branch 'master' of https://bitbucket.org/nuttx/arch 2016-04-02 14:48:59 -06:00
Gregory Nutt
0fccd81eff cosmetic update 2016-04-02 14:58:01 -06:00
Gregory Nutt
29f1c90b82 Eliminate a warning 2016-04-02 14:48:51 -06:00
Gregory Nutt
9bc38d19d9 RTC: Further simplications of the RTC driver interface; Add sample implementation of alarms for F1 2016-04-02 13:54:18 -06:00
Gregory Nutt
5fdefa1aad Minor cleanup of STM32 alarm stuff 2016-04-02 13:11:57 -06:00
Gregory Nutt
476301e5a4 STM32: Adapt the lower half RTC driver to the new, simplified interface 2016-04-02 12:58:47 -06:00
Neil Hancock
5ac54013d2 STM32 F4: Add a custom RTC driver 2016-04-02 10:46:10 -06:00
Aleksandr Vyhovanec
472115eda9 ARMv7-M: Add support for the IAR compiler 2016-04-02 08:14:09 -06:00
Gregory Nutt
bd2da2f543 ARMv7-M: Add toolchain option to select the IAR tools. Move ARMv7-M assembly language into a gnu/ subdirectory. Makefile selects iar/ or gnu/ directory based upon tool configuration 2016-04-02 07:53:52 -06:00
Aleksandr Vyhovanec
29ab0fb991 STM32: Add support for the IAR compiler 2016-04-02 06:58:55 -06:00
Frank Benkert
2234d7d8e5 SAMV7: USBHS: make the last patch also working for non-control-endpoints 2016-04-02 06:12:27 -06:00
Gregory Nutt
02978c797a i.MX6: Straighten up some glock gating 2016-04-01 14:52:17 -06:00
Gregory Nutt
84b399136e GIC: Level or edge sensitive interrupt? 2016-04-01 13:26:57 -06:00
Gregory Nutt
f698f3dcbe ARMv7-A GIC: Fix another initialization errors 2016-04-01 08:53:43 -06:00
Gregory Nutt
ddc1b88027 ARMv7-A GIC: Fix some initialization errors 2016-04-01 08:40:51 -06:00
Gregory Nutt
855c9a5225 ARMv7-A GIC: Move debug logic to a separate file; fix some errors in debug logic. 2016-04-01 06:58:49 -06:00
Gregory Nutt
37cacc6178 ARMv7 GIC: Fix some formatting errors in GIC debug output 2016-03-31 18:26:15 -06:00
Gregory Nutt
70683d08bc i.MX6: Add GIC debug output 2016-03-31 17:25:04 -06:00
Frank Benkert
d1065e876f SAMV7: USBHS: Reset the TXIN bit not before new data was written or all requests are completed. 2016-03-31 14:20:36 -06:00
Sebastien Lorquet
6d96f24d98 Enable RNG interrupts only when needed. 2016-03-31 13:43:00 -06:00
Gregory Nutt
29cae97367 i.MX6: Fix several problems with peripheral pin configuration 2016-03-31 13:36:06 -06:00
Gregory Nutt
9a9566faba i.MX6 Add more debug instrumentation; Fix setting of CCM register. 2016-03-31 10:49:35 -06:00
Gregory Nutt
756e6050e4 ARMv7-A: Need to set bits in the ICDDCR to enable forwarding of interrupts 2016-03-31 09:18:55 -06:00
Gregory Nutt
12064b276a ARMv7-A: Fix an error in GIC initialization 2016-03-31 08:05:12 -06:00
Gregory Nutt
9b81319fb1 i.MX6: OCRAM should be cacheable 2016-03-31 07:25:30 -06:00
Gregory Nutt
eb6fbc3059 Trivial changes from review of last PR 2016-03-30 14:44:29 -06:00
Gregory Nutt
8b1bcecbb1 Merged in ziggurat29/arch/stm32l4_rtc_001 (pull request #61) 
Stm32l4_rtc_001
 2016-03-30 14:32:47 -06:00
ziggurat29
624e6c1ebe correct #define errors in the 'debug output' and 'alarms' options code paths 2016-03-30 15:25:43 -05:00
Gregory Nutt
05fe9cb393 i.MX6: Fix UART baud rate calculation 2016-03-30 13:54:56 -06:00
ziggurat29
600a9b6981 basic RTC functionality implemented 2016-03-30 14:46:36 -05:00
Gregory Nutt
84f2fcfa80 i.MX6: Fix a few UART and GPIO initialization problems. 2016-03-30 12:31:49 -06:00
Gregory Nutt
8df80e6615 Kconfigs: All RNG selections also must select ARCH_HAVE_RNG 2016-03-30 07:56:03 -06:00
Gregory Nutt
6e000dc4fa i.MX6: Need to mapping OCRAM before enabling MMU because the page table lies in OCRAM 2016-03-29 17:51:58 -06:00
Gregory Nutt
426a6dae74 i.MX6: Fix missing DRAM mapping 2016-03-29 17:16:46 -06:00
Gregory Nutt
679a26cdf8 Update some comments 2016-03-29 15:35:47 -06:00
Gregory Nutt
1c56b8dd87 Update some ARM registers for Cortex-A9 2016-03-29 11:47:35 -06:00
Michael Spahlinger
940075f629 SAMV71/SAME70: Error in UART1 Pinmapping corrected 2016-03-29 07:25:37 -06:00
Dave
f9c2f70b36 STM32L4 PWR: Fix reversed parameters in putreg32() 2016-03-29 07:19:00 -06:00
Sebastien Lorquet
8fdef878ba Minor optimization to PR #60 2016-03-29 07:13:24 -06:00
Gregory Nutt
446618a644 Misc. trivial changes from review of last PR 2016-03-27 13:15:49 -06:00
Gregory Nutt
2a54bf91e5 Merged in ziggurat29/arch/stm32l4_lse (pull request #60) 
Stm32l4_lse support
 2016-03-27 13:06:55 -06:00
Gregory Nutt
267e20c729 PM: Add domain to all PM interfaces. Internal PM data structures now handle multiple PM domains. 2016-03-27 13:01:32 -06:00
Gregory Nutt
32acc35c88 PM: Add activity domain to all PM callbacks 2016-03-27 11:18:54 -06:00
ziggurat29
5bd7b7b54c add support for LSE oscillator configuration; requires also initial support of PWR control block 2016-03-27 12:07:47 -05:00
ziggurat29
cc53b25dbd fix typos in names of some LSE-related constants 2016-03-27 10:48:02 -05:00
ziggurat29
860a139ba0 trivial; update stm32l4 readme indicating things recently completed 2016-03-26 11:58:30 -05:00
Gregory Nutt
a52f638d7e Eliminate a warning 2016-03-25 14:59:53 -06:00
Gregory Nutt
03a31fca25 Misc costmetic changes from review of last PR 2016-03-25 14:35:35 -06:00
ziggurat29
c856bbb264 support RNG on STM32L4. add support for SAI1PLL and SAI2PLL. fix some errors in defines and configs. 2016-03-25 11:31:23 -05:00
Sebastien Lorquet
b2e7f63a7b Fix for bad type in stm32l4_spi.c 2016-03-24 08:18:30 -06:00
Gregory Nutt
ad611e2cca Merged in paulpatience/nuttx-arch (pull request #58) 
STM32 DAC: Fix DMA support for STM32F2xxx and STM32F4xxx
 2016-03-20 15:33:55 -06:00
Paul A. Patience
2f187f8714 STM32 DAC: Fix DMA support for STM32F2xxx and STM32F4xxx 2016-03-20 17:26:40 -04:00
Gregory Nutt
748edc0445 Fix a error in the previous commit 2016-03-20 14:23:45 -06:00
Gregory Nutt
e0249bd025 STM32L4: Fix incorrect and conflicting definitions for STM32L4_NGPIOS and STM32L4_NGPIO_PORTS. Now there is only STM32L4_NPORTS. 2016-03-20 14:12:07 -06:00
Gregory Nutt
f7d3b8147f Rename CONFIG_NET_MULTICAST to avoid name conflicts 2016-03-20 13:14:36 -06:00
Gregory Nutt
47b36e9de4 i.MX6: Fix uninitialized variable warning in GPIO logic 2016-03-19 13:59:50 -06:00
Gregory Nutt
2a15f73fd3 SAMV7 USB: Eliminate a warning 2016-03-17 17:43:29 -06:00
Gregory Nutt
0ff29023f1 SAMV7 USB: Fix a DMA related issue. When DMA completes with NBUSYBK greater than zero, need to way for NBUSYBK interrupt. 2016-03-17 17:43:29 -06:00
Gregory Nutt
bd846c2e72 All architectures: Register the schedule note driver if enabled 2016-03-17 17:00:59 -06:00
Gregory Nutt
b1c09dc0c5 i.MX6: Hmm.. I think the i.MX6 Solo Lite has global and private timers. Note cleare from the reference manual 2016-03-16 10:54:55 -06:00
Gregory Nutt
e1ff2af690 All i.MX6 family members have GIC 390; SoloLite does not seem to have MPCore timers 2016-03-14 13:41:53 -06:00
Gregory Nutt
dcc93a7a44 Make it clear that GIC support is GICv2 2016-03-14 10:50:54 -06:00
Gregory Nutt
41b3af52b7 i.MX6: Revamp GIC initialization logic; add missing register bit definitions and initialization of GIC control register for secure cases 2016-03-13 10:12:45 -06:00
Gregory Nutt
411cf0ba1f SMP: Add per-CPU initialization logic 2016-03-13 07:16:26 -06:00
Gregory Nutt
6288e381ee Conform to revised SMP interfaces. Improve i.MX6 SMP startup handshake. 2016-03-12 15:22:45 -06:00
Gregory Nutt
8ad1188fe5 i.MX6: Finish initial cut at all SMP support 2016-03-12 13:23:49 -06:00
Gregory Nutt
9addc363f5 i.MX6 no longer depends on EXPERIMENTAL 2016-03-12 11:46:53 -06:00
Gregory Nutt
11f3554153 i.MX6: Kconfg needs to autoselect ARCH_HAVE_TRUSTZONE 2016-03-12 11:40:27 -06:00
Gregory Nutt
cbe7321508 i.MX6: Finish GIC initialization 2016-03-12 11:38:16 -06:00
Gregory Nutt
08fa7a0c6b Rename CONFIG_SAMA5_HAVE_TRUSTZONE to CONFIG_ARCH_HAVE_TRUSTZONE; Eliminate CONFIG_SAMA5_SECURE; Add CONFIG_ARCH_TRUSTZONE_SECURE 2016-03-12 10:53:22 -06:00
Gregory Nutt
a1ee5ae6e5 EFM32 Serial: Fix typo in initializer. Noted by Pierre-noel Bouteville 2016-03-12 08:53:41 -06:00
Gregory Nutt
4d484399a9 ARM: Remove some obsolete and incorrect conditional compilation 2016-03-11 12:42:58 -06:00
Michael Spahlinger
faa0c4f1ca SAMV7: MCAN: Correct typo in MCAN0 configuration 2016-03-11 12:30:57 -06:00
Gregory Nutt
4e07680554 TLS: Forgot to add a file before last commit 2016-03-11 12:30:04 -06:00
Gregory Nutt
87e7e135ba i.MX6: GIC decode and prioritization logic 2016-03-11 09:49:00 -06:00
Gregory Nutt
bc0fb5453a i.MX6: A little more GIC initialization logic 2016-03-11 09:00:49 -06:00
Gregory Nutt
1909dc8239 TLS: Move up_tls_info() to an inline function. Simplify TLS implementation. 2016-03-11 07:17:02 -06:00
Gregory Nutt
78e4ca2bc7 ARM: Partial implementation of TLS 2016-03-10 19:29:21 -06:00
Gregory Nutt
5445a1af83 Add a common ARM implementation of up_tls_info() 2016-03-10 18:10:17 -06:00
Gregory Nutt
a9b880a02b STM32L4: Fix a small error that prevent a clean compilation 2016-03-10 15:58:08 -06:00
Gregory Nutt
3d6519a223 Implement Cortex-A9 up_cpu_index() using the MPIDR register. Thanks Alan. 2016-03-10 14:02:58 -06:00
Sebastien Lorquet
1e5c4a83de Add stm32L4 I2C driver 2016-03-10 11:00:41 -06:00
Gregory Nutt
8e66043d7a Rename current_regs in STM32L4 for consistency with other platforms 2016-03-10 10:08:40 -06:00
Sebastien Lorquet
f4f03e6f02 Add port to the stm32L4 2016-03-10 09:59:16 -06:00
Gregory Nutt
a94febb551 MPCore: Fix missing header file inclusion; Add GIC-based implementations of up_enabable_irq(0 and up_disable_irq() 2016-03-10 08:37:34 -06:00
Gregory Nutt
5c75f83b55 ARMv7-A GIC: Add definitions for shared interrupt IDs 2016-03-10 07:13:40 -06:00
Gregory Nutt
4a8ac55c9d All SAM TWI: g_twiops should be both static and const 2016-03-09 18:11:55 -06:00
Gregory Nutt
400aead74a i.MX6: Add definitions for private processor interrupt IDs 2016-03-09 18:11:28 -06:00
Gregory Nutt
51be83aa3a ARM: Fix missing header file. Update comments in all *_irq.c files. 2016-03-09 15:08:58 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
7b0a696498 i.MX6: Add a system timer based on the i.MX6 GPT 2016-03-09 12:16:44 -06:00
Gregory Nutt
725e6878c4 i.MX6: Finish bit definitions in GPT header file 2016-03-09 09:31:36 -06:00
Gregory Nutt
80dce6dba1 i.MX6: Add incomplete GPT header file 2016-03-09 09:08:01 -06:00
Gregory Nutt
613786ff3d ARMv7-A: Add global timer header file 2016-03-09 08:36:22 -06:00
David Sidrane
a2052d006c Fix what I believe to be typos in SAMV7 timer 2016-03-08 17:26:01 -06:00
David Sidrane
72eef9f628 Ensure that CONFIG_ARMV7M_STACKCHECK works on the samv7 2016-03-08 17:22:07 -06:00
Gregory Nutt
85a7ca1ddd i.MX6: Fill in some 'Missing logic' that depended on CCM definitions. Correct confusion with boot media configuration. 2016-03-08 16:49:09 -06:00
Gregory Nutt
145853a930 i.MX6: Complete CCM header file 2016-03-08 13:54:43 -06:00
Frank Benkert
73de0d9114 SAMV7: TWIHS: Correct Error Handling 2016-03-08 06:47:22 -06:00
Frank Benkert
945e137382 SAMV7: TWIHS: Correct timeout calculation; correct some issues with Multi-Message-Transfer 2016-03-08 06:44:41 -06:00
Gregory Nutt
f46298105a i.MX6: Add skeleton clockconfig file. Fix some naming problems. Add some warnings. 2016-03-07 16:14:13 -06:00
Gregory Nutt
0d7edfd370 i.MX6: Add CCM header file 2016-03-07 15:01:38 -06:00
Gregory Nutt
3b1812b50f i.MX6 UART: Update periperal clock logic; Remove use of UART bits from i.MX1 that don't exist in i.MX6 2016-03-07 14:08:53 -06:00
Gregory Nutt
912008a883 i.MX6: Finish off some missing IOMUXC register bit definitions 2016-03-07 12:22:27 -06:00
Gregory Nutt
012f1c0e90 i.MX6: Some fixes for compiling imx_lowput.c. Still some missing clocking definitions. 2016-03-07 09:02:29 -06:00
Gregory Nutt
a67de9ce24 i.MX6: Add imx_lowputc.c; repartition some serial logic 2016-03-07 08:21:03 -06:00
Gregory Nutt
1992d57294 i.MX6: Add pin multiplexing header file 2016-03-06 21:30:37 -06:00
Gregory Nutt
dd7a4fb6a4 i.MX6: Modify encoding of GPIOs; add support for peripherals 2016-03-06 16:19:14 -06:00
Gregory Nutt
be594b8932 i.MX6 Add more IOMUX logic 2016-03-06 15:44:54 -06:00
Gregory Nutt
2b0124b9f2 i.MX6: Add a little more GPIO/IOMUX logic 2016-03-06 13:49:34 -06:00
Gregory Nutt
cbf7401dfb i.MX6 GPIO: Add IOMUXC logic to set pin as a GPIO 2016-03-06 12:24:24 -06:00
Gregory Nutt
0f825eed3d i.MX6: Add PADCTL register offsets 2016-03-06 09:37:43 -06:00
Gregory Nutt
af76adf06f i.MX6: Simply some IOMUXC naming 2016-03-06 08:54:45 -06:00
Gregory Nutt
dd27fce4eb Remove some whitespace at the end of the line 2016-03-05 09:18:30 -06:00
Gregory Nutt
56eebbbfe1 i.MX6: Add some basic, incomplete GPIO controls 2016-03-05 09:16:08 -06:00
Gregory Nutt
d938c1cd8c SAMV7: Use sem_reset() instead of sem_init() to set a semaphore count 2016-03-05 07:44:18 -06:00
Gregory Nutt
5c881e6d2e i.MX6: minor updates to last commit 2016-03-04 18:44:30 -06:00
Gregory Nutt
5100e7a623 i.MX6: Add some preliminary definitions to handle other family members 2016-03-04 18:43:16 -06:00
Gregory Nutt
f41189d828 i.MX6: Add IOMUXC header file 2016-03-04 16:19:34 -06:00
Frank Benkert
2297fdb714 SAMV71 and SAME70: Place the Main Oscillator Enable in the board.h 2016-03-04 12:31:54 -06:00
Gregory Nutt
88f0d35bce i.MX6: Add high-level GPIO header file 2016-03-04 12:27:11 -06:00
Gregory Nutt
910e649616 Add a debug assertion for logic error in previous commit 2016-03-04 10:28:13 -06:00
Frank Benkert
a115e13e06 SAMV7 MCAN: use FIFO mode instead of QUEUE mode; improve error reporting 
When using QUEUE mode sometimes the counting semaphore indicates there is no space left in the TX buffers, but in fact there is.  This leads to a situation, where all TX buffers are empty and the driver
still waits for space in the buffers.  The switch from QUEUE mode to FIFO mode is just a workarround to make the semaphore counting self repairing.

The Error reporting is changed due to some Error Interrupts not reporting states, they are reporting state changes. To keep this into Account the static Error conditions like WARNING, PASSIVE or BUS_OFF are filled in
every time.
 2016-03-04 10:15:35 -06:00
Gregory Nutt
7fd57d1591 Some fixes to last commit 2016-03-04 08:20:28 -06:00
Gregory Nutt
7887971ea5 i.MX6: Add GPIO header file 2016-03-04 08:17:13 -06:00
Gregory Nutt
f74d2a9f51 i.MX1: Rename imx_boardinitialize to imx_board_initialize 2016-03-03 16:42:07 -06:00
Gregory Nutt
16e93f5d41 i.MX6: Bring i.MX1 serial driver into i.MX6. Basically the same IP but does not yet compile due to some small differences, missign GPIO configuration logic, and missing clocking logic 2016-03-03 16:31:56 -06:00
Gregory Nutt
bff9eaab1e i.MX6: Add UART header file 2016-03-03 15:11:26 -06:00
Gregory Nutt
c404eae718 Costmetic update to comments 2016-03-03 09:12:13 -06:00
Gregory Nutt
3a14a4c4c6 i.MX6: Put in basic framework for interrupt handling 2016-03-03 08:50:56 -06:00
Gregory Nutt
a0783791a9 GIC: Fix some name collisions and naming inconsistencies 2016-03-03 08:50:25 -06:00
Gregory Nutt
c75e594350 SAMV7 USBHS Device: Reorder some interrupt handling logic to avoid losing an interrupt and to avoid a race condition 2016-03-02 14:58:17 -06:00
Gregory Nutt
52d499ba33 ARMv7-A: Add hooks for some common GIC logic 2016-03-02 14:56:54 -06:00
Gregory Nutt
5703f72a94 i.MX6: Add some boot logic. Mostly just cloned from the SAMA5D 2016-03-02 12:59:41 -06:00
Gregory Nutt
bed5aa8731 Add IMX_NCPUS to i.MX6 chip.h file 2016-03-02 10:28:09 -06:00
Gregory Nutt
0270530f75 Cosmetic change to spacing 2016-03-01 14:42:13 -06:00
Gregory Nutt
b466f18daf i.MX6: Some fixes for early compile issues 2016-03-01 14:15:43 -06:00
Gregory Nutt
db61cdefe7 Merge branch 'master' of bitbucket.org:nuttx/arch 2016-03-01 12:56:58 -06:00
Gregory Nutt
c05ae8ee99 i.MX6: Add basic memory map tables 2016-03-01 12:56:36 -06:00
Gregory Nutt
db331d47dd ARMv7-A: Clean up some kruft in gic.h 2016-03-01 12:55:48 -06:00
Gregory Nutt
2cafb5cf6c ARMv7-A: Clean up some kruft in gic.h 2016-03-01 12:55:39 -06:00
Gregory Nutt
52d777fa8d Merged in paulpatience/nuttx-arch/stm32f469 (pull request #56) 
STM32: Add support for STM32F46xxx
 2016-03-01 11:53:07 -06:00
Gregory Nutt
f552aa3ee8 Merged in paulpatience/nuttx-arch/stm32f30xxx_pinmap (pull request #55) 
STM32: Rename STM32F30xxx ADC pins to be more consistent
 2016-03-01 11:38:44 -06:00
Paul A. Patience
099990f3da STM32: Add support for STM32F46xxx 2016-03-01 12:18:07 -05:00
Paul A. Patience
221b49cf05 STM32: Rename STM32F30xxx ADC pins to be more consistent 2016-03-01 09:55:59 -05:00
Gregory Nutt
a496c9e755 i.MX6: Make naming of MPCore address regions consistent 2016-03-01 08:38:13 -06:00
Gregory Nutt
f2eb90cd1c i.MX6: Add definition of base address of ARM multi-core registers 2016-03-01 08:26:30 -06:00
Gregory Nutt
6949ff553b ARMv7-A: Revamp gic.h. Add mpcore.h 2016-03-01 08:21:26 -06:00
Gregory Nutt
bb62237c80 ARMv7-A: gic.h: Use register names from MPCore spec 2016-02-29 19:25:59 -06:00
Gregory Nutt
1fdc8db30c ARMv7-A: Add GIC register definition header file 2016-02-29 18:13:51 -06:00
Gregory Nutt
fe7331900c i.MX6 add dummy chip.h header files 2016-02-29 14:08:16 -06:00
Gregory Nutt
0d54cfa7ad i.MX6: Some tweaks to the Kconfig files 2016-02-29 13:17:18 -06:00
Gregory Nutt
ad69f9d045 i.MX6: Add memory map header file 2016-02-29 12:26:21 -06:00
Gregory Nutt
a0cdd1ddb1 Add a rudimentary arch/arm/src/imx6 directory for the i.MX6 family 2016-02-28 15:32:36 -06:00
Gregory Nutt
75973db9cc Change name IMX to IMX1 in configuration variable names to make room for i.MX6 2016-02-28 15:18:43 -06:00
Gregory Nutt
0a9920a87a i.MX6: Add IRQ header file 2016-02-28 14:07:53 -06:00
Gregory Nutt
74e5336b39 Rename the imx/ directories to imx1/ to make room in the namespace for other members of the i.MX family 2016-02-27 10:29:24 -06:00
Frank Benkert
2980985933 SAMV7 SPI: Revise support for Peripheral Chip Select Decoding to address up to 15 slaved 2016-02-25 08:13:33 -06:00
Gregory Nutt
f1a196cd40 Revert "SAMV7 SPI: Add support for Peripheral Chip Select Decoding to address up to 15 slaved" 
This reverts commit 733010246bc55e28b8c99bc13798955a207c9860.
 2016-02-25 08:05:39 -06:00
Gregory Nutt
0da57e1b53 It is too late to be doing this... Fix the spacing error introduced with the second correction to the spelling error 2016-02-24 17:56:40 -06:00
Gregory Nutt
29297da2a7 Another spelling error 2016-02-24 17:55:30 -06:00
Gregory Nutt
550e0f945b STM32 I2C: Fix some spelling; duplicate I2C reset fix on other variants of the driver 2016-02-24 16:45:45 -06:00
David Sidrane
3b871c4fa2 No really removed spaces 2016-02-24 22:23:39 +00:00
David Sidrane
052b45db0a Added spacing back 2016-02-24 22:21:07 +00:00
David Sidrane
aa6968dcd5 Ensures frequency is updated on reinitalized bus 2016-02-24 12:02:11 -10:00
Frank Benkert
c263fe1c8b SAMV7 SPI: Add support for Peripheral Chip Select Decoding to address up to 15 slaved 2016-02-24 13:47:15 -06:00
Gregory Nutt
9c9107171d Fix Kconfig help comments 2016-02-23 06:38:29 -06:00
Gregory Nutt
11d17572a1 Update Kconfig help comments 2016-02-23 06:37:44 -06:00
Gregory Nutt
52d4bb24b5 Cosmetic: Remove some harmless kruft left in last commit 2016-02-22 16:58:42 -06:00
Gregory Nutt
d493e13792 Missed a couple of places in the last commit 2016-02-22 16:52:26 -06:00
Gregory Nutt
08f0086771 SAMV7 HSCMI: Don't assert of the data buffer is unaligned. Instead, return -EFAULT. This will allow the FAT file system to utilize the CONFIG_FAT_DMAMEMORY option and fix the problem from the file system 2016-02-22 16:44:33 -06:00
Gregory Nutt
1446784fbd Cosmetic: Improve some comments; correct some code indentation. 2016-02-22 15:43:58 -06:00
Gregory Nutt
557756c8b4 Improve a debug assertion 2016-02-22 15:02:07 -06:00
Gregory Nutt
9e9c50a1a3 SAMV7 HSMCI: Add a configuration otpion to allow HSMCI to handle unaligned I/O buffers 2016-02-22 14:52:24 -06:00
Gregory Nutt
07bde1fd73 Missing semicolon in prototype 2016-02-22 13:40:27 -06:00
Michael Spahlinger
96f3d618a1 SAMV7: Add CHIP ID and RSTC header file 2016-02-22 09:08:39 -06:00
Gregory Nutt
9c63736c98 Standard some naming if code sectino comments 2016-02-21 18:06:09 -06:00
Gregory Nutt
9b3651f7a9 Remove comments before empty sections in C files 2016-02-21 11:26:43 -06:00
Gregory Nutt
e9bf66989e LPC43xx: Add RS485 configuration settings to Kconfig; For RS485, add an option to select DTR as the DIR pin 2016-02-19 07:59:24 -06:00
Gregory Nutt
9b96057dc0 LPC43 VBUS sensing option should also depend on CONFIG_USDBDEV 2016-02-18 19:14:38 -06:00
Dave Marples
41b56a5f09 Enable the Ethernet for the LPC4330 and autonegotiation when the MAC is a LAN8720. 2016-02-18 19:07:33 -06:00
Gregory Nutt
441cd2bf1c Fix a typo introduced in last set of name changes 2016-02-14 19:58:30 -06:00
Gregory Nutt
349e5bc3ec Fix some LPC31 and LPC43 errors introduced by a recent pull request 2016-02-14 19:35:40 -06:00
Gregory Nutt
8b7dd552a3 Fix a typo introduced in last big set of name changes 2016-02-14 17:44:45 -06:00
Gregory Nutt
666cc280f4 Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable() 2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
2cd8d279d2 Missed a few name changes 2016-02-13 19:16:51 -06:00
Gregory Nutt
70e502adb0 Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
Gregory Nutt
3caffdd82e Standardization of some naming in preparation for a large automated change 2016-02-13 12:57:09 -06:00
Gregory Nutt
e7d077a389 LPC31: Fix some definitions to match LPC43 2016-02-12 16:30:30 -06:00
Gregory Nutt
6181711942 Correct some comments 2016-02-09 13:48:16 -06:00
Gregory Nutt
a6eb9a351c Add spinlock support for ARMv7-M architectures 2016-02-09 13:44:22 -06:00
Gregory Nutt
98e9e7d768 Add spinlock support for ARMv7-R architectures 2016-02-09 13:01:32 -06:00
Gregory Nutt
5d449e9991 Add spinlock support for ARMv7-A architectures 2016-02-09 12:53:10 -06:00
Gregory Nutt
ed4e3c0a9e ARM: Replace explicit references to g_readytorun with indirect references via the macro this_task() 2016-02-06 13:41:28 -06:00
Gregory Nutt
03b382d443 SAM3/4, SAMA5, SAMv7 Tickless: Refuse to call lower-level timer logic if not yet initialized 2016-02-05 10:22:11 -06:00
Gregory Nutt
341fbe1186 Rename all tiva_spi functions to tiva_ssi 2016-02-04 10:33:15 -06:00
Gregory Nutt
ef64f8b3f4 Missed spiinitialize name change 2016-02-04 10:15:51 -06:00
Gregory Nutt
d511afd507 LPC31: Fix an unmatching function prototype 2016-02-03 18:11:42 -06:00
Gregory Nutt
1166e311b0 Networking: Remove the HSEC argument from devif_timer. 2016-02-03 11:17:15 -06:00
Gregory Nutt
578402f8b5 Fix some spacing in a comment 2016-02-03 10:33:59 -06:00
Gregory Nutt
d2b2cd3415 Duplicate Manuel's EMAC driver fix to every other driver that supports CONFIG_NET_NOINTS 2016-02-03 10:33:22 -06:00
Manuel Stuehn
7236e742ab STM32 Ethernet: Fix a cornercase where the TX poll timer is not restarted. 2016-02-03 08:24:49 -06:00
Gregory Nutt
1e4f2ae2c1 Rename up_i2c initialize and uninitialize functions using the correct MCU-specific naming 2016-02-02 12:08:23 -06:00
Gregory Nutt
d2571985ef I2C: up_i2creset should not be a global function; Now it is an I2C interface method 2016-02-02 11:21:45 -06:00
Gregory Nutt
f1a5a6dfc7 I2C: Fixes/improvements from last massive I2C commits 2016-02-02 07:12:50 -06:00
Gregory Nutt
30624c8dfa EFM32, STM32, and Tiva I2C Drivers: Clean up some kruft that is no longer needed after the last massive I2C interfcase change 2016-02-01 19:51:55 -06:00
Gregory Nutt
c9a7d48cb2 I2C: Fix some compile time issues found with tools/testbuild.sh 2016-02-01 18:02:39 -06:00
Gregory Nutt
0693e76be8 I2C: Remove the setfrequency method from the interface 2016-02-01 16:30:29 -06:00
Gregory Nutt
a64f36a63e I2C: Remove setaddress method 2016-02-01 12:14:20 -06:00
Gregory Nutt
ce988c7ed3 Remove the read and write methods from the I2C interface 2016-02-01 09:22:10 -06:00
Gregory Nutt
91fa0b9616 More SPI initialize naming clarification 2016-01-31 15:38:28 -06:00
Gregory Nutt
2171438c61 I2C_TRANSFER support is no longer optional 2016-01-31 14:00:53 -06:00
Gregory Nutt
b5019c4b54 Backport the LPC17xx I2C driver to the LPC2378 in order to get the I2C_TRANSFER method. 2016-01-30 13:06:18 -06:00
Gregory Nutt
8f1b9886a9 Backport the new LPC17xx I2C driver to the LPC11xx in order to get the I2C_TRANSFER method 2016-01-30 12:17:01 -06:00
Gregory Nutt
8a37072e87 Backport the LPC32xx I2C driver to the LPC17xx in order to get the I2C_TRANSFER method 2016-01-30 11:26:38 -06:00
Gregory Nutt
531d73af41 Remove I2C slave methods from I2C master interface; rename i2c_dev_s to i2c_master_s. 2016-01-30 08:35:46 -06:00
Gregory Nutt
9f9b85a932 Move include/nuttx/i2c.h to include/nuttx/i2c/i2c_master.h 2016-01-30 07:59:44 -06:00
Freddie Chopin
8203659ee5 stm32_rtc_endwr(): wait for RTC_CRL_RTOFF bit to be set. This ensures that the write "reaches" RTC registers before access is disabled by stm32_pwr_enablebkp(). 2016-01-28 16:58:02 -06:00
Gregory Nutt
5d0c914121 LPC2148: Missing spi initializatin prototype 2016-01-28 09:52:46 -06:00
Gregory Nutt
9f2ae5bb86 LPC43: Fix a naming collision with i2c_read 2016-01-28 07:47:32 -06:00
Gregory Nutt
4d2e423cf6 Calypso: Fix some typos in last SPI changes 2016-01-27 16:40:29 -06:00
Gregory Nutt
215dfe778b For LPC2378 MCUs, rename up_spiinitialize to lpc23_spibus_initialize 2016-01-27 09:02:15 -06:00
Gregory Nutt
b4f0ad1af5 For i.MX1 MCUs, rename up_spiinitialize to imx_spibus_initialize 2016-01-27 08:57:34 -06:00
Gregory Nutt
bd5e6f784b For STR71xx MCUs, rename up_spiinitialize to str71_spibus_initialize 2016-01-27 08:50:01 -06:00
Gregory Nutt
120f7ccebf For Calypso MCUs, rename up_spiinitialize to calypso_spibus_initialize 2016-01-27 08:13:51 -06:00
Gregory Nutt
c958d83ee1 For LPC43xx MCUs, rename lpc17_spiinitialize to lpc43_spibus_initialize 2016-01-26 17:17:12 -06:00
Gregory Nutt
6305c4274a For LPC17xx MCUs, rename lpc17_spiinitialize to lpc17_spibus_initialize 2016-01-26 17:07:47 -06:00
Gregory Nutt
cc68a24972 For LPC31xx MCUs, rename up_spiinitialize to lpc31_spibus_initialize 2016-01-26 16:56:28 -06:00
Gregory Nutt
aa2ae3f26a For Kinetis MCUs, rename up_spiinitialize to kinetis_spibus_initialize 2016-01-26 16:25:50 -06:00
Gregory Nutt
3b6a502eff For LK MCUs, rename up_spiinitialize to kl_spibus_initialize 2016-01-26 16:19:03 -06:00
Gregory Nutt
d06fae98a3 EFM32: Rename efm_spi_initialize to efm_spibus_initialize for compatibility with corresponding changes to other platforms 2016-01-26 15:58:33 -06:00
Gregory Nutt
8864c78e57 For Tiva/LM MCUs, rename up_spiinitialize to tiva_spibus_initialize 2016-01-26 15:20:31 -06:00
Gregory Nutt
d16978be7f For SAM MCUs, rename up_spiinitialize to sam_spibus_initialize 2016-01-26 13:03:17 -06:00
Gregory Nutt
04bbd8c67f For STM32, rename up_spiinitialize to stm32_spibus_initialize 2016-01-26 12:22:27 -06:00
Gregory Nutt
c0fb4e34a7 I2C: Eliminate the I2C_WRITEREAD method 2016-01-26 10:23:09 -06:00
Gregory Nutt
b64a45d667 Add a missing semicolon 2016-01-26 08:00:29 -06:00
Gregory Nutt
c9295c5152 Merge branch 'master' of bitbucket.org:nuttx/arch 2016-01-25 13:26:28 -06:00
Gregory Nutt
a2ce7cc30f Add SAMV7 AFEC header file 2016-01-25 13:25:12 -06:00
Gregory Nutt
f4115ab45c Correct LPC11xx priority definitions + fix some typos in comments 2016-01-25 07:36:26 -06:00
Lok Tep
1f4ce9e7f9 LPC43xx: Fix some NVIC priority definitions 2016-01-25 07:23:28 -06:00
Gregory Nutt
fb3baae5a4 Trivial: Change ASSERT to DEBUGASSERT 2016-01-24 10:48:35 -06:00
Gregory Nutt
7a7bb6387b Fix initialization of a semaphore 2016-01-24 09:25:39 -06:00
Gregory Nutt
52109ade2d Flesh out unfinished lock() method implementations in al SPI drivers 2016-01-24 09:15:57 -06:00
Gregory Nutt
b7cbbab761 Remove CONFIG_SPI_OWNBUS: Now it is not just a good idea, it is the law 2016-01-23 18:10:21 -06:00
Gregory Nutt
00aaceaf2f All SPI-based device drivers needs to call SPI_HWFEATURES() with zero in order to co-exist with drivers that use H/W features 2016-01-23 16:17:42 -06:00
Gregory Nutt
3850b9b70c Remove carriage returns from a file 2016-01-23 15:19:57 -06:00
Gregory Nutt
4bd6adb725 Add dummy hwfeatures method to all SPI interfaces 2016-01-23 15:09:38 -06:00
Gregory Nutt
ece6517607 Kinetis ENET: Move ioctl function; add prototype and function header; split up some long lines 2016-01-21 19:14:04 -06:00
Andrew Webster
43303a5786 Kinetis: add MK60N512VLL100 support 2016-01-21 19:07:18 -06:00
Andrew Webster
9d0c378dbc Kinetis enet: switch to built-in byte swapper. Depends on GCC __builtin functions 2016-01-21 19:05:51 -06:00
Andrew Webster
d3238e6f95 Kinetis enet: buffer management update 
This patch manages the packet buffer used by the upper layers by making sure it is always set to a valid transmit buffer that can be used by the MAC-NET core.  The only exception to this is when the upper layer re-uses a receive buffer to send a response. In this case, the updated receive buffer is swapped with an empty transmit buffer.  If there is no empty transmit buffer available, the packet will be dropped.

Signed-off-by: Andrew Webster <awebster@arcx.com>

Kinetis enet: add support for DBSWP

Signed-off-by: Andrew Webster <awebster@arcx.com>
 2016-01-21 19:00:21 -06:00
Andrew Webster
64a0f54767 Kinetis enet: add PHY ioctl support. 2016-01-21 18:54:04 -06:00
Andrew Webster
a118233a59 Kinetis enet: set the MII_MODE bit. The RM states that this bit should always be 1. 2016-01-21 18:50:53 -06:00
Andrew Webster
36408697ca Kinetis enet: leave the write buffer wrap bit alone. The wrap buffer bit is initialized when the buffers are set up and should not be changed later 2016-01-21 18:49:23 -06:00